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authorAnton Vorontsov <avorontsov@ru.mvista.com>2009-06-24 20:30:28 +0400
committerKumar Gala <galak@kernel.crashing.org>2009-07-29 23:14:18 -0500
commitc4673f9a32d7b02bcd2057763d3d368efe5809c3 (patch)
treeb314ef84f8f28d7ec7d24aa23dfd9c6804ee51e3 /arch/powerpc
parent5156ddce6c0a152ee7ccab2c976c6a8abc8a49b5 (diff)
powerpc/85xx: Fix ethernet link detection on MPC8569E-MDS boards
Linux isn't able to detect link changes on ethernet ports that were used by U-Boot. This is because U-Boot wrongly clears interrupt polarity bit (INTPOL, 0x400) in the extended status register (EXT_SR, 0x1b) of Marvell PHYs. There is no easy way for PHY drivers to know IRQ line polarity (we could extract it from the device tree and pass it to phydevs, but that'll be quite a lot of work), so for now just reset the PHYs to their default states. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 60ed9c067b1..bfb32834ab0 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -233,6 +233,19 @@ static void __init mpc85xx_mds_setup_arch(void)
/* Turn UCC1 & UCC2 on */
setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+ } else if (machine_is(mpc8569_mds)) {
+#define BCSR7_UCC12_GETHnRST (0x1 << 2)
+#define BCSR8_UEM_MARVELL_RST (0x1 << 1)
+ /*
+ * U-Boot mangles interrupt polarity for Marvell PHYs,
+ * so reset built-in and UEM Marvell PHYs, this puts
+ * the PHYs into their normal state.
+ */
+ clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+ setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+ setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+ clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
}
iounmap(bcsr_regs);
}