aboutsummaryrefslogtreecommitdiff
path: root/post/cache_8xx.S
blob: 2d41b5566a8f9f7f2b0bb567c0a601908da6bb50 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
/*
 *  Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>

#ifdef CONFIG_POST
#if defined(CONFIG_MPC823) || \
    defined(CONFIG_MPC850) || \
    defined(CONFIG_MPC855) || \
    defined(CONFIG_MPC860) || \
    defined(CONFIG_MPC862)

#include <post.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>

#if CONFIG_POST & CFG_POST_CACHE

	.text

cache_post_dinvalidate:
	lis	r10, IDC_INVALL@h
	mtspr	DC_CST, r10
	blr

cache_post_iinvalidate:
	lis	r10, IDC_INVALL@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_ddisable:
	lis	r10, IDC_DISABLE@h
	mtspr	DC_CST, r10
	blr

cache_post_dwb:
	lis	r10, IDC_ENABLE@h
	mtspr	DC_CST, r10
	lis	r10, DC_CFWT@h
	mtspr	DC_CST, r10
	blr

cache_post_dwt:
	lis	r10, IDC_ENABLE@h
	mtspr	DC_CST, r10
	lis	r10, DC_SFWT@h
	mtspr	DC_CST, r10
	blr

cache_post_idisable:
	lis	r10, IDC_DISABLE@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_ienable:
	lis	r10, IDC_ENABLE@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_iunlock:
	lis	r10, IDC_UNALL@h
	mtspr	IC_CST, r10
	isync
	blr

cache_post_ilock:
	mtspr	IC_ADR, r3
	lis	r10, IDC_LDLCK@h
	mtspr	IC_CST, r10
	isync
	blr

/*
 * turn on the data cache
 * switch the data cache to write-back or write-through mode
 * invalidate the data cache
 * write the negative pattern to a cached area
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test1
cache_post_test1:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_dwb
	bl	cache_post_dinvalidate

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

/*
 * turn on the data cache
 * switch the data cache to write-back or write-through mode
 * invalidate the data cache
 * write the zero pattern to a cached area
 * turn off the data cache
 * write the negative pattern to the area
 * turn on the data cache
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test2
cache_post_test2:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_dwb
	bl	cache_post_dinvalidate

	/* Write the zero pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_ddisable

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_dwb

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

/*
 * turn on the data cache
 * switch the data cache to write-through mode
 * invalidate the data cache
 * write the zero pattern to a cached area
 * flush the data cache
 * write the negative pattern to the area
 * turn off the data cache
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test3
cache_post_test3:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Write the zero pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_dwt
	bl	cache_post_dinvalidate

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

/*
 * turn on the data cache
 * switch the data cache to write-back mode
 * invalidate the data cache
 * write the negative pattern to a cached area
 * flush the data cache
 * write the zero pattern to the area
 * invalidate the data cache
 * read the area
 *
 * The negative pattern must be read at the last step
 */
	.global cache_post_test4
cache_post_test4:
	mflr	r0
	stw	r0, 4(r1)

	stwu	r3, -4(r1)
	stwu	r4, -4(r1)

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Write the negative pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0xff
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_dwb
	bl	cache_post_dinvalidate

	/* Write the zero pattern to the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	li	r0, 0
	lwz	r3, 4(r1)
	subi	r3, r3, 1
1:
	stbu	r0, 1(r3)
	bdnz	1b

	bl	cache_post_ddisable
	bl	cache_post_dinvalidate

	/* Read the test area */
	lwz	r0, 0(r1)
	mtctr	r0
	lwz	r4, 4(r1)
	subi	r4, r4, 1
	li	r3, 0
1:
	lbzu	r0, 1(r4)
	cmpli	cr0, r0, 0xff
	beq	2f
	li	r3, -1
	b	3f
2:
	bdnz	1b
3:

	addi	r1, r1, 8

	lwz	r0, 4(r1)
	mtlr	r0
	blr

cache_post_test5_1:
	li	r3, 0
cache_post_test5_2:
	li	r3, -1

/*
 * turn on the instruction cache
 * unlock the entire instruction cache
 * invalidate the instruction cache
 * lock a branch instruction in the instruction cache
 * replace the branch instruction with "nop"
 * jump to the branch instruction
 * check that the branch instruction was executed
*/
	.global cache_post_test5
cache_post_test5:
	mflr	r0
	stw	r0, 4(r1)

	bl	cache_post_ienable
	bl	cache_post_iunlock
	bl	cache_post_iinvalidate

	/* Compute r9 = cache_post_test5_reloc */
	bl	cache_post_test5_reloc
cache_post_test5_reloc:
	mflr	r9

	/* Copy the test instruction to cache_post_test5_data */
	lis	r3, (cache_post_test5_1 - cache_post_test5_reloc)@h
	ori	r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test5_data - cache_post_test5_reloc)@h
	ori	r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Lock the branch instruction */
	lis	r3, (cache_post_test5_data - cache_post_test5_reloc)@h
	ori	r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l
	add	r3, r3, r9
	bl	cache_post_ilock

	/* Replace the test instruction */
	lis	r3, (cache_post_test5_2 - cache_post_test5_reloc)@h
	ori	r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test5_data - cache_post_test5_reloc)@h
	ori	r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Execute to the test instruction */
cache_post_test5_data:
	nop

	bl	cache_post_iunlock

	lwz	r0, 4(r1)
	mtlr	r0
	blr

cache_post_test6_1:
	li	r3, -1
cache_post_test6_2:
	li	r3, 0

/*
 * turn on the instruction cache
 * unlock the entire instruction cache
 * invalidate the instruction cache
 * lock a branch instruction in the instruction cache
 * replace the branch instruction with "nop"
 * jump to the branch instruction
 * check that the branch instruction was executed
 */
	.global cache_post_test6
cache_post_test6:
	mflr	r0
	stw	r0, 4(r1)

	bl	cache_post_ienable
	bl	cache_post_iunlock
	bl	cache_post_iinvalidate

	/* Compute r9 = cache_post_test6_reloc */
	bl	cache_post_test6_reloc
cache_post_test6_reloc:
	mflr	r9

	/* Copy the test instruction to cache_post_test6_data */
	lis	r3, (cache_post_test6_1 - cache_post_test6_reloc)@h
	ori	r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test6_data - cache_post_test6_reloc)@h
	ori	r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Replace the test instruction */
	lis	r3, (cache_post_test6_2 - cache_post_test6_reloc)@h
	ori	r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l
	add	r3, r3, r9
	lis	r4, (cache_post_test6_data - cache_post_test6_reloc)@h
	ori	r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
	add	r4, r4, r9
	lwz	r0, 0(r3)
	stw	r0, 0(r4)

	bl	cache_post_iinvalidate

	/* Execute to the test instruction */
cache_post_test6_data:
	nop

	lwz	r0, 4(r1)
	mtlr	r0
	blr

#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */
#endif /* CONFIG_POST & CFG_POST_CACHE */
#endif /* CONFIG_POST */