diff options
Diffstat (limited to 'include/configs')
29 files changed, 1070 insertions, 297 deletions
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 145c3c37d..b386057c0 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -1,4 +1,8 @@ /* + * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com> + * + * based on previous work by + * * Ulf Samuelsson <ulf@atmel.com> * Rick Bronson <rick@efn.org> * @@ -23,40 +27,52 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __AT91RM9200EK_CONFIG_H__ +#define __AT91RM9200EK_CONFIG_H__ -#define CONFIG_AT91_LEGACY +#include <asm/sizes.h> -/* ARM asynchronous clock */ /* - * from 18.432 MHz crystal - * (18432000 / 4 * 39) + * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz + * AT91C_MAIN_CLOCK is the frequency of PLLA output + * AT91C_MASTER_CLOCK is the peripherial clock + * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely + * set in arch/arm/cpu/arm920t/at91/timer.c) + * CONFIG_SYS_HZ is the tick rate for timer tc0 */ -#define AT91C_MAIN_CLOCK 179712000 -/* - * peripheral clock - * (AT91C_MASTER_CLOCK / 3) - */ -#define AT91C_MASTER_CLOCK 59904000 +#define AT91C_XTAL_CLOCK 18432000 +#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) +#define CONFIG_SYS_HZ 1000 -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +/* CPU configuration */ +#define CONFIG_ARM920T +#define CONFIG_AT91RM9200 +#define CONFIG_AT91RM9200EK +#define CONFIG_CPUAT91 +#define USE_920T_MMU -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +/* + * Memory Configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_32M + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) /* * LowLevel Init */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +#define CONFIG_SYS_USE_MAIN_OSCILLATOR /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ @@ -73,50 +89,26 @@ #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#else -#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ -#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 - -/* - * Memory Configuration - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144) - /* * Hardware drivers */ - /* - * UART Configuration - * - * define one of these to choose the DBGU, - * USART0 or USART1 as console + * Choose a USART for serial console + * CONFIG_DBGU is DBGU unit on J10 + * CONFIG_USART1 is USART1 on J14 */ #define CONFIG_AT91RM9200_USART #define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 -/* don't include RTS/CTS flow control support */ -#undef CONFIG_HWFLOW -/* disable modem initialization stuff */ -#undef CONFIG_MODEM_SUPPORT #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_BAUDRATE 115200 @@ -130,156 +122,75 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_MII #define CONFIG_CMD_PING - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_IMI +#define CONFIG_CMD_USB #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_LOADS - -#include <asm/arch/AT91RM9200.h> /* needed for port definitions */ -/* Options for MMC/SD Card */ -#define CONFIG_DOS_PARTITION 1 -#undef CONFIG_MMC -#define CONFIG_SYS_MMC_BASE 0xFFFB4000 -#define CONFIG_SYS_MMC_BLOCKSIZE 512 /* * Network Driver Setting */ -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -/* - * AC Characteristics - * DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns - */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#if defined(CONFIG_HAS_DATAFLASH) -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 -#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 -/* Logical adress for CS0 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 -/* Logical adress for CS3 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 -#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1 -#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22 -#endif +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_RMII +#define CONFIG_MII /* * NOR Flash */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8MB */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE +#define PHYS_FLASH_SIZE SZ_8M +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_FLASH_PROTECTION /* - * Environment Settings - */ -#ifdef CONFIG_ENV_IS_IN_DATAFLASH -/* - * Datasflash Environment Settings + * USB Config */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -/* 8 * 1056 really , but start.s is not OK with this*/ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 -#else -/* - * NOR Flash Environment Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT /* - * between boot.bin and u-boot.bin.gz + * Environment Settings */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000) -#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ -#else +#define CONFIG_ENV_IS_IN_FLASH + /* * after u-boot.bin */ #define CONFIG_ENV_ADDR \ (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */ /* The following #defines are needed to get flash environment right */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN \ - (CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE) -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#endif /* CONFIG_ENV_IS_IN_DATAFLASH */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* * Boot option */ #define CONFIG_BOOTDELAY 3 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -/* boot.bin, env, u-boot.bin.gz */ -#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000) -#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -#else -/* u-boot.bin */ -#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ -#define CONFIG_ENV_OVERWRITE 1 - -/* - * USB Config - */ -#define CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * I2C - */ -#define CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ -#endif +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M +#define CONFIG_ENV_OVERWRITE /* * Shell Settings */ -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ @@ -288,41 +199,18 @@ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CONFIG_SYS_HZ 1000 -/* - * AT91C_TC0_CMR is implicitly set to - * AT91C_TC_TIMER_DIV1_CLOCK - */ -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \ - , 0x1000) +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ + SZ_4K) /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ -#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/ -#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/ -#endif +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ + - CONFIG_SYS_GBL_DATA_SIZE) + +#define CONFIG_STACKSIZE SZ_32K /* regular stack */ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/ +#endif /* __AT91RM9200EK_CONFIG_H__ */ diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h new file mode 100644 index 000000000..ae60f2eb3 --- /dev/null +++ b/include/configs/balloon3.h @@ -0,0 +1,274 @@ +/* + * Balloon3 configuration file + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_BALLOON3 1 /* Balloon3 board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOOTCOMMAND \ + "fpga load 0x0 0x50000 0x62638; " \ + "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ + "bootm 0xd0000;" +#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_SYS_TEXT_BASE 0x0 +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_STUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_USB +#define CONFIG_CMD_FPGA +#undef CONFIG_LCD + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR \ + (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_ENV_IS_IN_FLASH +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x000000 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd +#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e +#define CONFIG_SYS_GPSR2_VAL 0x7131c000 +#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff + +#define CONFIG_SYS_GPCR0_VAL 0x0 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPCR3_VAL 0x0 + +#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02 +#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7 +#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff +#define CONFIG_SYS_GPDR3_VAL 0x000201fe + +#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b +#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa +#define CONFIG_SYS_GAFR3_L_VAL 0x54510003 +#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0xffffffff +#define CONFIG_SYS_CCCR 0x00000290 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8 +#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 +#define CONFIG_SYS_MSC2_VAL 0x74a42491 +#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3 +#define CONFIG_SYS_MDREFR_VAL 0x001d8018 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 +#define CONFIG_SYS_MEM_BUF_IMP 0x0f + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MCMEM1_VAL 0x00014307 +#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT1_VAL 0x0001c787 +#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO1_VAL 0x0001430f + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_BALLOON3LCD +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3" +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#endif + +/* + * FPGA + */ +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 +#define CONFIG_MAX_FPGA_DEVICES 1 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 477b94aa6..98b69e371 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -161,6 +161,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 277ff67bf..5f457f80d 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -169,6 +169,9 @@ #define CONFIG_SYS_LOAD_ADDR (0xa1000000) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 200b61e0c..d1c1a48e0 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -145,6 +145,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ @@ -339,8 +342,6 @@ #define LED_IRDA1 2 #define LED_IRDA2 4 #define LED_IRDA3 6 -#define CRADLE_LED_SET_REG GPSR2 -#define CRADLE_LED_CLR_REG GPCR2 /* SuperIO defines */ #define CRADLE_SIO_INDEX 0x2e diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 0661d65ab..ae05734a0 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -181,6 +181,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + # if 0 /* FIXME: switch to _documented_ registers */ /* diff --git a/include/configs/delta.h b/include/configs/delta.h index 9c46c5bdb..d53acbfeb 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -28,6 +28,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_DELTA 1 /* Delta board */ /* #define CONFIG_LCD 1 */ @@ -217,6 +218,9 @@ #undef CONFIG_SYS_SKIP_DRAM_SCRUB +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NAND Flash */ diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 4ff4a85cb..8d8af9379 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -42,7 +42,7 @@ #define CONFIG_MISC_INIT_R /*--------------------------------------------------------------------------*/ - +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ @@ -98,12 +98,14 @@ */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - PHYS_SDRAM_SIZE - 0x00400000 - \ + CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ @@ -249,6 +251,7 @@ /* FLASH organization */ /* NOR-FLASH */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_FLASH_CFI_DRIVER 1 @@ -396,16 +399,6 @@ "nandboot=run bootargsdefaults;" \ "set bootargs $(bootargs) root=initramfs boot=nand " \ ";bootm $(kerneladdr)\0" \ - "uu=run update_uboot\0" \ - "ur=run update_root;run nk\0" \ - "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ - "boot=local " \ - ";echo $(bootargs)" \ - ";dhcp uImage_cpux9k2;bootm\0" \ - "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ - "boot=nand " \ - ";echo $(bootargs)" \ - ";dhcp uImage_cpux9k2;bootm\0" \ " " /*--------------------------------------------------------------------------*/ diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index ccfc66053..43e5e870f 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -223,4 +223,9 @@ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 #define CONFIG_SYS_MAXARGS 16 +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* _CONFIG_EDMINIV2_H */ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 88c62d11e..94252371b 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -147,6 +147,13 @@ #define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#undef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + /*----------------------------------------------------------------------- * FLASH and environment organization */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 9cb0d42ea..007ccebf4 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -192,6 +192,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * JFFS2 partitions * diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 0a6921044..3a99ec25c 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -176,6 +176,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + #define FPGA_REGS_BASE_PHYSICAL 0x08000000 /* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 8864f3ab7..616547327 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -30,8 +30,8 @@ #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ -#define CONFIG_MX51_CLK32 32768 +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index bbb1073a7..900dbd3f7 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -55,6 +55,15 @@ #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R +#define CONFIG_OF_LIBFDT 1 +/* + * The early kernel mapping on ARM currently only maps from the base of DRAM + * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. + * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, + * so that leaves DRAM base to DRAM base + 0x4000 available. + */ +#define CONFIG_SYS_BOOTMAPSZ 0x4000 + #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 diff --git a/include/configs/palmld.h b/include/configs/palmld.h new file mode 100644 index 000000000..926728b15 --- /dev/null +++ b/include/configs/palmld.h @@ -0,0 +1,276 @@ +/* + * Palm LifeDrive configuration file + * + * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_PALMLD 1 /* Palm LifeDrive board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "source 0xa0000000; " \ + "else " \ + "bootm 0x0x60000; " \ + "fi; " +#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_IDE +#define CONFIG_LCD + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_LQ038J7DH53 +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 + +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SIZE 0x4000 + +/* + * IDE + */ +#ifdef CONFIG_CMD_IDE +#define CONFIG_LBA48 +#undef CONFIG_IDE_LED +#undef CONFIG_IDE_RESET + +#define __io + +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 + +#define CONFIG_SYS_ATA_DATA_OFFSET 0x10 +#define CONFIG_SYS_ATA_REG_OFFSET 0x10 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x10 + +#define CONFIG_SYS_ATA_STRIDE 1 +#endif + +/* + * GPIO settings + */ +#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012 +#define CONFIG_SYS_GAFR1_L_VAL 0x69988056 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa +#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x01040001 +#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c +#define CONFIG_SYS_GAFR3_U_VAL 0x00000009 +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0xc26b0000 +#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93 +#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff +#define CONFIG_SYS_GPDR3_VAL 0x006ff38d +#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee +#define CONFIG_SYS_GPSR1_VAL 0x03affdae +#define CONFIG_SYS_GPSR2_VAL 0x07554000 +#define CONFIG_SYS_GPSR3_VAL 0x01bc0785 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x01ffffff +#define CONFIG_SYS_CCCR 0x02000210 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x7ff844c8 +#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 +#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 +#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd +#define CONFIG_SYS_MDREFR_VAL 0x201fa031 +#define CONFIG_SYS_MDMRS_VAL 0x00320032 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000003 +#define CONFIG_SYS_MCMEM0_VAL 0x0001c391 +#define CONFIG_SYS_MCMEM1_VAL 0x0001c391 +#define CONFIG_SYS_MCATT0_VAL 0x0001c391 +#define CONFIG_SYS_MCATT1_VAL 0x0001c391 +#define CONFIG_SYS_MCIO0_VAL 0x00014611 +#define CONFIG_SYS_MCIO1_VAL 0x0001c391 + +#endif /* __CONFIG_H */ diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h new file mode 100644 index 000000000..fe87648ac --- /dev/null +++ b/include/configs/palmtc.h @@ -0,0 +1,248 @@ +/* + * Palm Tungsten|C configuration file + * + * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/pxa-regs.h> + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA250 1 /* Intel PXA255 CPU */ +#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "source 0xa0000000; " \ + "else " \ + "bootm 0x80000; " \ + "fi; " +#define CONFIG_BOOTARGS \ + "console=tty0 console=ttyS0,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + * STUART - the lower serial port on Colibri board + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MMC +#define CONFIG_LCD + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_ACX517AKN +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */ +#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 64 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_ADDR 0x40000 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GAFR0_L_VAL 0x00011004 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008 +#define CONFIG_SYS_GAFR1_L_VAL 0x60888050 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa +#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 +#define CONFIG_SYS_GPCR0_VAL 0x0 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPDR0_VAL 0xcfff8140 +#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3 +#define CONFIG_SYS_GPDR2_VAL 0x0001ffff +#define CONFIG_SYS_GPSR0_VAL 0x00010f8f +#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5 +#define CONFIG_SYS_GPSR2_VAL 0x03fe0800 + +#define CONFIG_SYS_PSSR_VAL PSSR_RDH + +/* Clock setup: + * CKEN[1] - PWM1 ; CKEN[6] - FFUART + * CKEN[12] - MMC ; CKEN[16] - LCD + */ +#define CONFIG_SYS_CKEN 0x00011042 +#define CONFIG_SYS_CCCR 0x00000161 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x800092c2 +#define CONFIG_SYS_MSC1_VAL 0x80008000 +#define CONFIG_SYS_MSC2_VAL 0x80008000 +#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9 +#define CONFIG_SYS_MDREFR_VAL 0x00118018 +#define CONFIG_SYS_MDMRS_VAL 0x00220032 +#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00010504 +#define CONFIG_SYS_MCMEM1_VAL 0x00010504 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00010504 +#define CONFIG_SYS_MCIO0_VAL 0x00010e04 +#define CONFIG_SYS_MCIO1_VAL 0x00010e04 + +#endif /* __CONFIG_H */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index 9e694118c..3b6e60afe 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -179,6 +179,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 6c1defc9a..4581674ed 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -292,6 +292,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/qong.h b/include/configs/qong.h index f26ced1d7..426d90d7d 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -102,6 +102,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #endif /* CONFIG_CMD_USB */ @@ -124,25 +125,16 @@ #include <config_cmd_default.h> #define CONFIG_CMD_CACHE -#define CONFIG_CMD_PING +#define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR #define CONFIG_CMD_SPI -#define CONFIG_CMD_DATE -#define BOARD_LATE_INIT -/* - * You can compile in a MAC address and your custom net settings by using - * the following syntax. - * - * #define CONFIG_ETHADDR xx:xx:xx:xx:xx:xx - * #define CONFIG_SERVERIP <server ip> - * #define CONFIG_IPADDR <board ip> - * #define CONFIG_GATEWAYIP <gateway ip> - * #define CONFIG_NETMASK <your netmask> - */ +#define BOARD_LATE_INIT #define CONFIG_BOOTDELAY 5 @@ -164,7 +156,7 @@ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addmisc=setenv bootargs ${bootargs}\0" \ "uboot_addr=A0000000\0" \ - "kernel_addr=A00A0000\0" \ + "kernel_addr=A00C0000\0" \ "ramdisk_addr=A0300000\0" \ "u-boot=qong/u-boot.bin\0" \ "kernel_addr_r=80800000\0" \ @@ -296,10 +288,14 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_LZO #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \ + "nand0=gen_nand" #define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ - "128k(env2),2432k(kernel),13m(ramdisk),-(user)" + "mtdparts=physmap-flash.0:" \ + "512k(U-Boot),128k(env1),128k(env2)," \ + "2304k(kernel),13m(ramdisk),-(user);" \ + "gen_nand:" \ + "128m(nand)" /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index fa5aae8a5..474349537 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -212,6 +212,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/tx25.h b/include/configs/tx25.h index bcc8140df..996afa3b0 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 -#define CONFIG_SYS_NAND_U_BOOT_DST (0x81fc0000) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000) #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 44a6f8be6..a2ecbe50d 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -29,8 +29,8 @@ #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_L2_OFF -#define CONFIG_MX51_HCLK_FREQ 24000000 -#define CONFIG_MX51_CLK32 32768 +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index d3e22d901..c9d9c69cd 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -10,7 +10,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -19,8 +19,8 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_H +#define __CONFIG_H /* * High Level Board Configuration Options @@ -28,20 +28,13 @@ #define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ -#undef BOARD_LATE_INIT -#undef CONFIG_SKIP_RELOCATE_UBOOT -#undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT - /* * Environment settings */ -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 - -#define CONFIG_ENV_OVERWRITE /* override default environment */ - +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ @@ -49,13 +42,16 @@ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ "fi; " \ - "bootm 0x40000;" + "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ + "bootm 0x60000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -79,7 +75,7 @@ #undef CONFIG_LCD #define CONFIG_CMD_IDE -#ifdef CONFIG_ONENAND_U_BOOT +#ifdef CONFIG_ONENAND #undef CONFIG_CMD_FLASH #define CONFIG_CMD_ONENAND #else @@ -97,9 +93,9 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ +#define DM9000_IO (CONFIG_DM9000_BASE) +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_BOOTP_BOOTFILESIZE @@ -116,6 +112,7 @@ #define CONFIG_PXA_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION #endif @@ -123,8 +120,8 @@ * KGDB */ #ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -133,29 +130,27 @@ #define CONFIG_SYS_HUSH_PARSER 1 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " #endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_DEVICE_NULLDEV 1 /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ -#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ +#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ /* * Stack sizes - * - * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ @@ -166,33 +161,58 @@ /* * DRAM Map */ -#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +#ifdef CONFIG_RAM_256M #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#endif #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ +#else +#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ +#endif -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR (0x5c000000) +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 +#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR \ + (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) /* * NOR FLASH */ +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x4000 + #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#ifdef CONFIG_RAM_256M #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ +#endif #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } +#else +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#endif #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) @@ -200,26 +220,30 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 #define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH 1 + +/* + * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the + * flash consists of 0x20000 bytes big sectors. + */ +#if (CONFIG_ENV_ADDR <= 0x18000) +#define CONFIG_ENV_SECT_SIZE 0x8000 +#else +#define CONFIG_ENV_SECT_SIZE 0x20000 +#endif #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ONENAND_BASE 0x00000000 + #define CONFIG_ENV_IS_IN_ONENAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 #else /* No flash */ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ENV_IS_NOWHERE #endif -#define CONFIG_SYS_MONITOR_BASE 0x000000 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - /* * IDE */ @@ -230,15 +254,15 @@ #define __io -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 +#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 -#define CONFIG_SYS_ATA_REG_OFFSET 0x120 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 +#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 +#define CONFIG_SYS_ATA_REG_OFFSET 0x120 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 #define CONFIG_SYS_ATA_STRIDE 2 #endif @@ -284,7 +308,11 @@ #define CONFIG_SYS_MSC0_VAL 0x3ffc95fa #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 +#else +#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 +#endif #define CONFIG_SYS_MDREFR_VAL 0x201fe01e #define CONFIG_SYS_MDMRS_VAL 0x00000000 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 @@ -306,13 +334,13 @@ * LCD */ #ifdef CONFIG_LCD -#define CONFIG_VOIPAC_LCD +#define CONFIG_VOIPAC_LCD #endif /* * USB */ -#ifdef CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_BOARD_INIT diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index 9a20cce45..a961a2792 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -183,6 +183,10 @@ #define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */ #define CONFIG_ENV_SIZE 0x2000 +#define PHYS_SDRAM_1 WEP_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + #undef CONFIG_ENV_OVERWRITE /* env is not writable now */ /* diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 1329f0f3d..67d4106d6 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -167,6 +167,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index cd56ce72e..2ff9a2813 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -174,6 +174,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index f68461bb2..9606b5316 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -53,6 +53,9 @@ #define CONFIG_SYS_DRAM_BASE 0xa0000000 #define CONFIG_SYS_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* FLASH organization */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index a5a873ba3..ce65d1f1c 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -41,8 +41,9 @@ #define CONFIG_ENV_ADDR 0x40000 #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE) +#define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 512 +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ @@ -56,7 +57,7 @@ #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -175,6 +176,9 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048) + /* * NOR FLASH */ @@ -218,7 +222,7 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_GPCR3_VAL 0x00000000 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab -#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff +#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a #define CONFIG_SYS_GPSR0_VAL 0x06080400 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index d0fc13888..c33ca2de9 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -35,6 +35,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_ZYLONITE 1 /* Zylonite board */ /* #define CONFIG_LCD 1 */ @@ -189,6 +190,8 @@ #undef CONFIG_SYS_SKIP_DRAM_SCRUB +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) /* * NAND Flash |