diff options
Diffstat (limited to 'board')
176 files changed, 9088 insertions, 4475 deletions
diff --git a/board/AndesTech/adp-ag101p/Makefile b/board/AndesTech/adp-ag101p/Makefile new file mode 100644 index 000000000..03c3ff41e --- /dev/null +++ b/board/AndesTech/adp-ag101p/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> +# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := adp-ag101p.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c new file mode 100644 index 000000000..8dd20430d --- /dev/null +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <faraday/ftsdc010.h> +#include <faraday/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ + +int board_init(void) +{ + /* + * refer to BOOT_PARAMETER_PA_BASE within + * "linux/arch/nds32/include/asm/misc_spec.h" + */ + gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P; + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + + ftsmc020_init(); /* initialize Flash */ + return 0; +} + +int dram_init(void) +{ + unsigned long sdram_base = PHYS_SDRAM_0; + unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size((void *)sdram_base, expected_size); + + gd->ram_size = actual_size; + + if (expected_size != actual_size) { + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + } + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ftmac100_initialize(bd); +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else { + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ + ftsdc010_mmc_init(0); + return 0; +} diff --git a/board/BuS/EB+MCF-EV123/config.mk b/board/BuS/EB+MCF-EV123/config.mk index 50185aead..18fb84eb3 100644 --- a/board/BuS/EB+MCF-EV123/config.mk +++ b/board/BuS/EB+MCF-EV123/config.mk @@ -22,7 +22,6 @@ # MA 02111-1307 USA # -sinclude $(OBJTREE)/board/$(BOARDDIR)/textbase.mk ifndef CONFIG_SYS_TEXT_BASE CONFIG_SYS_TEXT_BASE = 0xFE000000 endif diff --git a/board/BuS/EB+MCF-EV123/textbase.mk b/board/BuS/EB+MCF-EV123/textbase.mk deleted file mode 100644 index b97c034b2..000000000 --- a/board/BuS/EB+MCF-EV123/textbase.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0xFFE00000 diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile new file mode 100644 index 000000000..f5ad4949d --- /dev/null +++ b/board/CarMediaLab/flea3/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := flea3.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c new file mode 100644 index 000000000..64f4b57f1 --- /dev/null +++ b/board/CarMediaLab/flea3/flea3.c @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011, Stefano Babic <sbabic@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx35_pins.h> +#include <asm/arch/iomux.h> +#include <i2c.h> +#include <linux/types.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include <netdev.h> + +#ifndef CONFIG_BOARD_EARLY_INIT_F +#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" +#endif + +#define CCM_CCMR_CONFIG 0x003F4208 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_PRECHARGE 0x00000400 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 +#define ESDCTL_DELAY_LINE5 0x00F49F00 + +static inline void dram_wait(unsigned int count) +{ + volatile unsigned int wait = count; + + while (wait--) + ; +} + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + + return 0; +} + +static void board_setup_sdram_bank(u32 start_address) + +{ + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + u32 *cfg_reg, *ctl_reg; + u32 val; + + switch (start_address) { + case CSD0_BASE_ADDR: + cfg_reg = &esdc->esdcfg0; + ctl_reg = &esdc->esdctl0; + break; + case CSD1_BASE_ADDR: + cfg_reg = &esdc->esdcfg1; + ctl_reg = &esdc->esdctl1; + break; + default: + return; + } + + /* Initialize MISC register for DDR2 */ + val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST | + ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN; + writel(val, &esdc->esdmisc); + val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST); + writel(val, &esdc->esdmisc); + + /* + * according to DDR2 specs, wait a while before + * the PRECHARGE_ALL command + */ + dram_wait(0x20000); + + /* Load DDR2 config and timing */ + writel(ESDCTL_DDR2_CONFIG, cfg_reg); + + /* Precharge ALL */ + writel(ESDCTL_0x92220000, + ctl_reg); + writel(0xda, start_address + ESDCTL_PRECHARGE); + + /* Load mode */ + writel(ESDCTL_0xB2220000, + ctl_reg); + writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */ + writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */ + writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ + writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */ + + /* Precharge ALL */ + writel(ESDCTL_0x92220000, + ctl_reg); + writel(0xda, start_address + ESDCTL_PRECHARGE); + + /* Set mode auto refresh : at least two refresh are required */ + writel(ESDCTL_0xA2220000, + ctl_reg); + writel(0xda, start_address); + writel(0xda, start_address); + + writel(ESDCTL_0xB2220000, + ctl_reg); + writeb(0xda, start_address + ESDCTL_DDR2_MR); + writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT); + + /* OCD mode exit */ + writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */ + + /* Set normal mode */ + writel(ESDCTL_0x82228080, + ctl_reg); + + dram_wait(0x20000); + + /* Do not set delay lines, only for MDDR */ +} + +static void board_setup_sdram(void) +{ + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + + /* Initialize with default values both CSD0/1 */ + writel(0x2000, &esdc->esdctl0); + writel(0x2000, &esdc->esdctl1); + + board_setup_sdram_bank(CSD1_BASE_ADDR); +} + +static void setup_iomux_uart3(void) +{ + mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7); + mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7); +} + +static void setup_iomux_i2c(void) +{ + int pad; + + mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); + + pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \ + | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); + + mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); + mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); + + mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1); + mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1); + + mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad); + mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad); +} + + +static void setup_iomux_spi(void) +{ + mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); + mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); +} + +static void setup_iomux_fec(void) +{ + /* setup pins for FEC */ + mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); + mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); + +} + +int board_early_init_f(void) +{ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + /* setup GPIO3_1 to set HighVCore signal */ + mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5); + gpio_direction_output(65, 1); + + /* initialize PLL and clock configuration */ + writel(CCM_CCMR_CONFIG, &ccm->ccmr); + + writel(CCM_MPLL_532_HZ, &ccm->mpctl); + writel(CCM_PPLL_300_HZ, &ccm->ppctl); + + /* Set the core to run at 532 Mhz */ + writel(0x00001000, &ccm->pdr0); + + /* Set-up RAM */ + board_setup_sdram(); + + /* enable clocks */ + writel(readl(&ccm->cgr0) | + MXC_CCM_CGR0_EMI_MASK | + MXC_CCM_CGR0_EDI0_MASK | + MXC_CCM_CGR0_EPIT1_MASK, + &ccm->cgr0); + + writel(readl(&ccm->cgr1) | + MXC_CCM_CGR1_FEC_MASK | + MXC_CCM_CGR1_GPIO1_MASK | + MXC_CCM_CGR1_GPIO2_MASK | + MXC_CCM_CGR1_GPIO3_MASK | + MXC_CCM_CGR1_I2C1_MASK | + MXC_CCM_CGR1_I2C2_MASK | + MXC_CCM_CGR1_I2C3_MASK, + &ccm->cgr1); + + /* Set-up NAND */ + __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); + + /* Set pinmux for the required peripherals */ + setup_iomux_uart3(); + setup_iomux_i2c(); + setup_iomux_fec(); + setup_iomux_spi(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +u32 get_board_rev(void) +{ + int rev = 0; + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S new file mode 100644 index 000000000..2f42fc97a --- /dev/null +++ b/board/CarMediaLab/flea3/lowlevel_init.S @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * Copyright (C) 2011, Stefano Babic <sbabic@denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm-offsets.h> +#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> + +/* + * Configuration for the flea3 board. + * These defines are used by the included macros and must + * be defined first + */ +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 + +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 + +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define CCM_PDR0_CONFIG 0x00801000 + +/* + * includes MX35 utility macros + */ +#include <asm/arch/lowlevel_macro.S> + +.globl lowlevel_init +lowlevel_init: + + core_init + + init_aips + + init_max + + init_m3if + + mov pc, lr diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg new file mode 100644 index 000000000..590720af8 --- /dev/null +++ b/board/LaCie/netspace_v2/kwbimage-is2.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000618 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x35143000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000008 # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000632 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg index 361feeb6f..7e5364912 100644 --- a/board/LaCie/netspace_v2/kwbimage.cfg +++ b/board/LaCie/netspace_v2/kwbimage.cfg @@ -69,8 +69,8 @@ DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) # bit12-11: TW2W # bit31-13: zero required -DATA 0xFFD01410 0x0000CCCC # DDR Address Control -# bit1-0: 01, Cs0width=x16 +DATA 0xFFD01410 0x0000000C # DDR Address Control +# bit1-0: 00, Cs0width=x8 # bit3-2: 11, Cs0size=1Gb # bit5-4: 00, Cs2width=nonexistent # bit7-6: 00, Cs1size =nonexistent diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 3bb83f359..7c4b15ec4 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -24,6 +24,7 @@ #include <miiphy.h> #include <netdev.h> #include <command.h> +#include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index 13b401361..31b73c98b 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -27,6 +27,7 @@ #include <common.h> #include <miiphy.h> +#include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> #include "dreamplug.h" diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index cab3a8394..a1de0dc4d 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -29,6 +29,8 @@ #include <miiphy.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> #include "dockstar.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ait/cam_enc_4xx/Makefile b/board/ait/cam_enc_4xx/Makefile new file mode 100644 index 000000000..2b221246a --- /dev/null +++ b/board/ait/cam_enc_4xx/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c new file mode 100644 index 000000000..135135829 --- /dev/null +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -0,0 +1,446 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <linux/mtd/nand.h> +#include <nand.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/nand_defs.h> +#include <asm/arch/davinci_misc.h> +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SPL_BUILD +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +static struct davinci_timer *timer = + (struct davinci_timer *)DAVINCI_TIMER3_BASE; + +static unsigned long get_timer_val(void) +{ + unsigned long now = readl(&timer->tim34); + + return now; +} + +static void stop_timer(void) +{ + writel(0x0, &timer->tcr); + return; +} + +int checkboard(void) +{ + printf("Board: AIT CAM ENC 4XX\n"); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +int board_eth_init(bd_t *bis) +{ + davinci_emac_initialize(); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_DAVINCI +static int +davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + struct nand_chip *this = mtd->priv; + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); + + chip->read_buf(mtd, oob, mtd->oobsize); + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask); + + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + chip->ecc.hwctl(mtd, NAND_ECC_READSYN); + + if (chip->ecc.prepad) + oob += chip->ecc.prepad; + + stat = chip->ecc.correct(mtd, p, oob, NULL); + + if (stat == -1) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + + oob += eccbytes; + + if (chip->ecc.postpad) + oob += chip->ecc.postpad; + } + + /* Calculate remaining oob bytes */ + i = mtd->oobsize - (oob - chip->oob_poi); + if (i) + chip->read_buf(mtd, oob, i); + + return 0; +} + +static void davinci_std_write_page_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE]; + struct nand_chip *this = mtd->priv; + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; + int offset = 0; + const uint8_t *p = buf; + uint8_t *oob = chip->oob_poi; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + chip->ecc.hwctl(mtd, NAND_ECC_WRITE); + chip->write_buf(mtd, p, eccsize); + + /* Calculate ECC without prepad */ + chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad); + + if (chip->ecc.prepad) { + offset = (chip->ecc.steps - eccsteps) * chunk; + memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + offset = ((chip->ecc.steps - eccsteps) * chunk) + + chip->ecc.prepad; + memcpy(&davinci_ecc_buf[offset], oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + offset = ((chip->ecc.steps - eccsteps) * chunk) + + chip->ecc.prepad + eccbytes; + memcpy(&davinci_ecc_buf[offset], oob, + chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + /* + * Write the sparebytes into the page once + * all eccsteps have been covered + */ + for (i = 0; i < mtd->oobsize; i++) + writeb(davinci_ecc_buf[i], this->IO_ADDR_W); + + /* Calculate remaining oob bytes */ + i = mtd->oobsize - (oob - chip->oob_poi); + if (i) + chip->write_buf(mtd, oob, i); +} + +static int davinci_std_write_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + int pos, status = 0; + const uint8_t *bufpoi = chip->oob_poi; + + pos = mtd->writesize; + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); + + chip->write_buf(mtd, bufpoi, mtd->oobsize); + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + return status & NAND_STATUS_FAIL ? -1 : 0; +} + +static int davinci_std_read_oob_syndrome(struct mtd_info *mtd, + struct nand_chip *chip, int page, int sndcmd) +{ + struct nand_chip *this = mtd->priv; + uint8_t *buf = chip->oob_poi; + uint8_t *bufpoi = buf; + + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); + + chip->read_buf(mtd, bufpoi, mtd->oobsize); + + return 1; +} + +static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + unsigned long wbase = (unsigned long) this->IO_ADDR_W; + unsigned long rbase = (unsigned long) this->IO_ADDR_R; + + if (chip == 1) { + __set_bit(14, &wbase); + __set_bit(14, &rbase); + } else { + __clear_bit(14, &wbase); + __clear_bit(14, &rbase); + } + this->IO_ADDR_W = (void *)wbase; + this->IO_ADDR_R = (void *)rbase; +} + +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + nand->select_chip = nand_dm365evm_select_chip; + + return 0; +} + +struct nand_ecc_ctrl org_ecc; +static int notsaved = 1; + +static int nand_switch_hw_func(int mode) +{ + struct nand_chip *nand; + struct mtd_info *mtd; + + if (nand_curr_device < 0 || + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || + !nand_info[nand_curr_device].name) { + printf("Error: Can't switch hw functions," \ + " no devices available\n"); + return -1; + } + + mtd = &nand_info[nand_curr_device]; + nand = mtd->priv; + + if (mode == 0) { + printf("switching to uboot hw functions.\n"); + memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl)); + } else { + /* RBL */ + printf("switching to RBL hw functions.\n"); + if (notsaved == 1) { + memcpy(&org_ecc, &nand->ecc, + sizeof(struct nand_ecc_ctrl)); + notsaved = 0; + } + nand->ecc.mode = NAND_ECC_HW_SYNDROME; + nand->ecc.prepad = 6; + nand->ecc.read_page = davinci_std_read_page_syndrome; + nand->ecc.write_page = davinci_std_write_page_syndrome; + nand->ecc.read_oob = davinci_std_read_oob_syndrome; + nand->ecc.write_oob = davinci_std_write_oob_syndrome; + } + return mode; +} + +static int hwmode; + +static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + if (argc != 2) + goto usage; + if (strncmp(argv[1], "rbl", 2) == 0) + hwmode = nand_switch_hw_func(1); + else if (strncmp(argv[1], "uboot", 2) == 0) + hwmode = nand_switch_hw_func(0); + else + goto usage; + + return 0; + +usage: + printf("Usage: nandrbl %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + nandrbl, 2, 1, do_switch_ecc, + "switch between rbl/uboot NAND ECC calculation algorithm", + "[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm" +); + + +#endif /* #ifdef CONFIG_NAND_DAVINCI */ + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .input_clk = 121500000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + int err; + + /* Add slot-0 to mmc subsystem */ + err = davinci_mmc_init(bis, &mmc_sd0); + + return err; +} +#endif + +int board_late_init(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank45; + + /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */ + while (get_timer_val() < 0x186a00) + ; + + /* 1 sec reached -> stop timer, clear all LED */ + stop_timer(); + clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK); + return 0; +} + +void reset_phy(void) +{ + char *name = "GENERIC @ 0x00"; + + /* reset the phy */ + miiphy_reset(name, 0x0); +} + +#else /* #ifndef CONFIG_SPL_BUILD */ +static void cam_enc_4xx_set_all_led(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank45; + + setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK); +} + +/* + * TIMER 0 is used for tick + */ +static struct davinci_timer *timer = + (struct davinci_timer *)DAVINCI_TIMER3_BASE; + +#define TIMER_LOAD_VAL 0xffffffff +#define TIM_CLK_DIV 16 + +static int cam_enc_4xx_timer_init(void) +{ + /* We are using timer34 in unchained 32-bit mode, full speed */ + writel(0x0, &timer->tcr); + writel(0x0, &timer->tgcr); + writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr); + writel(0x0, &timer->tim34); + writel(TIMER_LOAD_VAL, &timer->prd34); + writel(2 << 22, &timer->tcr); + return 0; +} + +void board_gpio_init(void) +{ + struct davinci_gpio *gpio; + + cam_enc_4xx_set_all_led(); + cam_enc_4xx_timer_init(); + gpio = davinci_gpio_bank01; + clrbits_le32(&gpio->dir, ~0xfdfffffe); + /* clear LED D14 = GPIO25 */ + clrbits_le32(&gpio->out_data, 0x02000000); + gpio = davinci_gpio_bank23; + clrbits_le32(&gpio->dir, ~0x5ff0afef); + /* set GPIO61 to 1 -> intern UART0 as Console */ + setbits_le32(&gpio->out_data, 0x20000000); + /* + * PHY out of reset GIO 50 = 1 + * NAND WP off GIO 51 = 1 + */ + setbits_le32(&gpio->out_data, 0x000c0004); + gpio = davinci_gpio_bank45; + clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK); + /* + * clear LED: + * D17 = GPIO86 + * D11 = GPIO87 + * GPIO88 + * GPIO89 + * D13 = GPIO90 + * GPIO91 + */ + clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK); + gpio = davinci_gpio_bank67; + clrbits_le32(&gpio->dir, ~0x000007ff); +} + +/* + * functions for the post memory test. + */ +int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) +{ + *vstart = CONFIG_SYS_SDRAM_BASE; + *size = PHYS_SDRAM_1_SIZE; + *phys_offset = 0; + return 0; +} + +void arch_memory_failure_handle(void) +{ + cam_enc_4xx_set_all_led(); + puts("mem failure\n"); + while (1) + ; +} +#endif diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk new file mode 100644 index 000000000..b1f9b6c22 --- /dev/null +++ b/board/ait/cam_enc_4xx/config.mk @@ -0,0 +1,15 @@ +# +# AIT cam_enc_4xx board +# cam_enc_4xx board has 1 bank of 256 MB DDR RAM +# Physical Address: 8000'0000 to 9000'0000 +# +# Linux Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +PAD_TO := 12320 +UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.ubl +endif diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds new file mode 100644 index 000000000..6f6e065a9 --- /dev/null +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __start = .; + arch/arm/cpu/arm926ejs/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } >.sram + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram + + __image_copy_end = .; + _end = .; +} diff --git a/board/ait/cam_enc_4xx/ublimage.cfg b/board/ait/cam_enc_4xx/ublimage.cfg new file mode 100644 index 000000000..95182cab0 --- /dev/null +++ b/board/ait/cam_enc_4xx/ublimage.cfg @@ -0,0 +1,48 @@ +# +# (C Copyright 2011 +# Heiko Schocher DENX Software Engineering hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer doc/README.ublimage for more details about how-to configure +# and create ublimage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# UBL special mode : one of +# safe (the board has no nand neither onenand) +MODE safe + +# Entry point address for the user bootloader (absolute address) +# nand spl TEXT_BASE = 0x20 !! +ENTRY 0x00000020 + +# Number of pages (size of user bootloader in number of pages) +# @ nand spl 6 pages +PAGES 6 + +# Block number where user bootloader is present +# RBL starts always with block 1 +START_BLOCK 5 + +# Page number where user bootloader is present +# Page 0 is always UBL header +START_PAGE 0 + +LD_ADDR 0x20 diff --git a/board/alaska/flash.c b/board/alaska/flash.c index aed3b6f59..977822ac5 100644 --- a/board/alaska/flash.c +++ b/board/alaska/flash.c @@ -406,7 +406,7 @@ static unsigned char same_chip_banks (int bank1, int bank2) int flash_erase (flash_info_t * info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0, intel = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -444,7 +444,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } start = get_timer (0); - last = start; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -501,6 +500,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf (" done\n"); } } + if (flag) + enable_interrupts(); + return rcode; } @@ -666,7 +668,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) { FPWV *addr = (FPWV *) dest; ulong start; - int flag; + int flag, rc = 0; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -685,14 +687,18 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); + rc = 1; + goto OUT; } } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ +OUT: + *addr = (FPW)0x00FF00FF; /* restore read mode */ - return (0); + if (flag) + enable_interrupts(); + + return rc; } /*----------------------------------------------------------------------- @@ -706,7 +712,7 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) FPWV *srcaddr = (FPWV *) src; FPWV *dstaddr = (FPWV *) dest; ulong start; - int flag, i; + int flag, i, rc = 0; /* Check if Flash is (sufficiently) erased */ for (i = 0; i < WR_BLOCK; i++) @@ -727,10 +733,10 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) start = get_timer (0); /* wait while polling the status register */ - while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); + while ((*dstaddr & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { + rc = 1; + goto OUT; } } @@ -752,9 +758,12 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) } } - *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ +OUT: + *dstaddr = (FPW)0x00FF00FF; /* restore read mode */ + if (flag) + enable_interrupts(); - return (0); + return rc; } /*----------------------------------------------------------------------- diff --git a/board/armltd/integrator/arm-ebi.h b/board/armltd/integrator/arm-ebi.h new file mode 100644 index 000000000..2d85e3fe9 --- /dev/null +++ b/board/armltd/integrator/arm-ebi.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2011 + * Linaro + * Linus Walleij <linus.walleij@linaro.org> + * Register definitions for the External Bus Interface (EBI) + * found in the ARM Integrator AP and CP reference designs + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARM_EBI_H +#define __ARM_EBI_H + +#define EBI_BASE 0x12000000 + +#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */ +#define EBI_CSR1_REG 0x04 /* CS1 = Flash */ +#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */ +#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */ +/* + * The four upper bits are the waitstates for each chip select + * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles + */ +#define EBI_CSR_WAIT_MASK 0xF0 +/* Whether memory is synchronous or asynchronous */ +#define EBI_CSR_SYNC_MASK 0xF7 +#define EBI_CSR_ASYNC 0x00 +#define EBI_CSR_SYNC 0x08 +/* Whether memory is write enabled or not */ +#define EBI_CSR_WREN_MASK 0xFB +#define EBI_CSR_WREN_DISABLE 0x00 +#define EBI_CSR_WREN_ENABLE 0x04 +/* Memory bit width for each chip select */ +#define EBI_CSR_MEMSIZE_MASK 0xFC +#define EBI_CSR_MEMSIZE_8BIT 0x00 +#define EBI_CSR_MEMSIZE_16BIT 0x01 +#define EBI_CSR_MEMSIZE_32BIT 0x02 + +/* + * The lock register need to be written with 0xa05f before anything in the + * EBI can be changed. + */ +#define EBI_LOCK_REG 0x20 +#define EBI_UNLOCK_MAGIC 0xA05F + +#endif diff --git a/board/armltd/integrator/config.mk b/board/armltd/integrator/config.mk deleted file mode 100644 index 8b57af1c5..000000000 --- a/board/armltd/integrator/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# image should be loaded at 0x01000000 -# - -CONFIG_SYS_TEXT_BASE = 0x01000000 diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h new file mode 100644 index 000000000..279dc55b3 --- /dev/null +++ b/board/armltd/integrator/integrator-sc.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2011 + * Linaro + * Linus Walleij <linus.walleij@linaro.org> + * Register definitions for the System Controller (SC) and + * the similar "CP Controller" found in the ARM Integrator/AP and + * Integrator/CP reference designs + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARM_SC_H +#define __ARM_SC_H + +#define SC_BASE 0x11000000 + +/* + * The system controller registers + */ +#define SC_ID_OFFSET 0x00 +#define SC_OSC_OFFSET 0x04 +/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */ +#define SC_OSC_DIVXY (1 << 8) +#define SC_CTRLS_OFFSET 0x08 +#define SC_CTRLC_OFFSET 0x0C +/* Set bits by writing CTRLS, clear bits by writing CTRLC */ +#define SC_CTRL_SOFTRESET (1 << 0) +#define SC_CTRL_FLASHVPP (1 << 1) +#define SC_CTRL_FLASHWP (1 << 2) +#define SC_CTRL_UART1DTR (1 << 4) +#define SC_CTRL_UART1RTS (1 << 5) +#define SC_CTRL_UART0DTR (1 << 6) +#define SC_CTRL_UART0RTS (1 << 7) +#define SC_DEC_OFFSET 0x10 +#define SC_ARB_OFFSET 0x14 +#define SC_PCI_OFFSET 0x18 +#define SC_PCI_PCIEN (1 << 0) +#define SC_PCI_PCIBINT_CLR (1 << 1) +#define SC_LOCK_OFFSET 0x1C +#define SC_LBFADDR_OFFSET 0x20 +#define SC_LBFCODE_OFFSET 0x24 + +#define SC_ID (SC_BASE + SC_ID_OFFSET) +#define SC_OSC (SC_BASE + SC_OSC_OFFSET) +#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET) +#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET) +#define SC_DEC (SC_BASE + SC_DEC_OFFSET) +#define SC_ARB (SC_BASE + SC_ARB_OFFSET) +#define SC_PCI (SC_BASE + SC_PCI_OFFSET) +#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET) +#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET) +#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET) + +/* + * The Integrator/CP as a smaller set of registers, at a different + * offset - probably not to disturb old software. + */ + +#define CP_BASE 0xCB000000 + +#define CP_IDFIELD_OFFSET 0x00 +#define CP_FLASHPROG_OFFSET 0x04 +#define CP_FLASHPROG_FLVPPEN (1 << 0) +#define CP_FLASHPROG_FLWREN (1 << 1) +#define CP_FLASHPROG_FLASHSIZE (1 << 2) +#define CP_FLASHPROG_EXTRABANK (1 << 3) +#define CP_INTREG_OFFSET 0x08 +#define CP_DECODE_OFFSET 0x0C + +#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET) +#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET) +#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET) +#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET) + +#endif diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index c8d2bc7ba..a507c093a 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -35,6 +35,9 @@ #include <common.h> #include <netdev.h> +#include <asm/io.h> +#include "arm-ebi.h" +#include "integrator-sc.h" DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +58,8 @@ void show_boot_progress(int progress) int board_init (void) { + u32 val; + /* arch number of Integrator Board */ #ifdef CONFIG_ARCH_CINTEGRATOR gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; @@ -72,6 +77,37 @@ extern void cm_remap(void); cm_remap(); /* remaps writeable memory to 0x00000000 */ #endif +#ifdef CONFIG_ARCH_CINTEGRATOR + /* + * Flash protection on the Integrator/CP is in a simple register + */ + val = readl(CP_FLASHPROG); + val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN); + writel(val, CP_FLASHPROG); +#else + /* + * The Integrator/AP has some special protection mechanisms + * for the external memories, first the External Bus Interface (EBI) + * then the system controller (SC). + * + * The system comes up with the flash memory non-writable and + * configuration locked. If we want U-Boot to be used for flash + * access we cannot have the flash memory locked. + */ + writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); + val = readl(EBI_BASE + EBI_CSR1_REG); + val &= EBI_CSR_WREN_MASK; + val |= EBI_CSR_WREN_ENABLE; + writel(val, EBI_BASE + EBI_CSR1_REG); + writel(0, EBI_BASE + EBI_LOCK_REG); + + /* + * Set up the system controller to remove write protection from + * the flash memory and enable Vpp + */ + writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS); +#endif + icache_enable (); return 0; @@ -86,21 +122,30 @@ int misc_init_r (void) return (0); } +/* + * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot + * from there, which means we cannot test the RAM underneath the ROM at this + * point. It will be unmapped later on, when we are executing from the + * relocated in RAM U-Boot. We simply assume that this RAM is usable if the + * RAM on higher addresses works fine. + */ +#define REMAPPED_FLASH_SZ 0x40000 + int dram_init (void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); - unsigned long cm_reg_sdram; - unsigned long sdram_shift; + u32 cm_reg_sdram; + u32 sdram_shift; dram_query(); /* Assembler accesses to CM registers */ /* Queries the SPD values */ /* Obtain the SDRAM size from the CM SDRAM register */ - cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); + cm_reg_sdram = readl(CM_BASE + OS_SDRAM); /* Register SDRAM size * * 0xXXXXXXbbb000bb 16 MB @@ -110,16 +155,18 @@ extern void dram_query(void); * 0xXXXXXXbbb100bb 256 MB * */ - sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + REMAPPED_FLASH_SZ, 0x01000000 << sdram_shift); } #else - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + REMAPPED_FLASH_SZ, PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ + /* We only have one bank of RAM, set it to whatever was detected */ + gd->bd->bi_dram[0].size = gd->ram_size; return 0; } diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c index c833b20b7..226782903 100644 --- a/board/c2mon/pcmcia.c +++ b/board/c2mon/pcmcia.c @@ -199,7 +199,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; ushort sreg; @@ -210,12 +209,11 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(_slot_); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 2e1356f9f..5522bf085 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -206,7 +206,7 @@ static ulong flash_get_size (unsigned char * addr, flash_info_t * info) int flash_erase (flash_info_t * info, int s_first, int s_last) { - int flag, prot, sect; + int prot, sect; ulong type; int rcode = 0; ulong start; @@ -240,7 +240,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { @@ -370,7 +370,6 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) { volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; - int flag; ulong start; /* Check if Flash is (sufficiently) erased */ @@ -380,7 +379,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); *addr = 0x40; /* write setup */ *addr = data; diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 2e1356f9f..5522bf085 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -206,7 +206,7 @@ static ulong flash_get_size (unsigned char * addr, flash_info_t * info) int flash_erase (flash_info_t * info, int s_first, int s_last) { - int flag, prot, sect; + int prot, sect; ulong type; int rcode = 0; ulong start; @@ -240,7 +240,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { @@ -370,7 +370,6 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) { volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; - int flag; ulong start; /* Check if Flash is (sufficiently) erased */ @@ -380,7 +379,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); *addr = 0x40; /* write setup */ *addr = data; diff --git a/board/cogent/flash.c b/board/cogent/flash.c index e6c85b6d9..ec3f94d2d 100644 --- a/board/cogent/flash.c +++ b/board/cogent/flash.c @@ -23,6 +23,7 @@ #include <common.h> #include <board/cogent/flash.h> +#include <linux/compiler.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -292,7 +293,7 @@ flash_init(void) { unsigned long total; int i; - flash_info_t *fip; + __maybe_unused flash_info_t *fip; /* Init: no FLASHes known */ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index c81ce58b6..65482813d 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -91,8 +91,6 @@ static const u32 gpmc_lan_config[] = { int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CPS; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c deleted file mode 100644 index dd29e6265..000000000 --- a/board/csb226/csb226.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de - * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/pxa-regs.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -/** - * misc_init_r: - misc initialisation routines - */ - -int misc_init_r(void) -{ -#if 0 - uchar *str; - - /* determine if the software update key is pressed during startup */ - /* not ported yet... */ - if (GPLR0 & 0x00000800) { - printf("using bootcmd_normal (sw-update button not pressed)\n"); - str = getenv("bootcmd_normal"); - } else { - printf("using bootcmd_update (sw-update button pressed)\n"); - str = getenv("bootcmd_update"); - } - - setenv("bootcmd",str); -#endif - return 0; -} - - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of CSB226 board */ - gd->bd->bi_arch_number = MACH_TYPE_CSB226; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -/** - * csb226_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1,2) - * @param state: switch on (1) or off (0) - */ - -void csb226_set_led(int led, int state) -{ - switch(led) { - - case 0: if (state==1) { - writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0); - } else if (state==0) { - writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0); - } - break; - - case 1: if (state==1) { - writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0); - } else if (state==0) { - writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0); - } - break; - - case 2: if (state==1) { - writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0); - } else if (state==0) { - writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0); - } - break; - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - switch(status) { - case 1: csb226_set_led(0,1); break; - case 5: csb226_set_led(1,1); break; - case 15: csb226_set_led(2,1); break; - } - - return; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/csb226/flash.c b/board/csb226/flash.c deleted file mode 100644 index e10347067..000000000 --- a/board/csb226/flash.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> - * - * (C) Copyright 2003 (2 x 16 bit Flash bank patches) - * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/pxa-regs.h> - -#define FLASH_BANK_SIZE 0x02000000 -#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/** - * flash_init: - initialize data structures for flash chips - * - * @return: size of the flash - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - - return size; -} - - -/** - * flash_print_info: - print information about the flash situation - */ - -void flash_print_info (flash_info_t *info) -{ - int i, j; - - for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) { - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf("28F128J3 (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } -} - - -/** - * flash_erase: - erase flash sectors - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - ulong start; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) prot++; - } - - if (prot) return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - u32 * volatile addr = (u32 * volatile)(info->start[sect]); - - /* erase sector: */ - /* The strata flashs are aligned side by side on */ - /* the data bus, so we have to write the commands */ - /* to both chips here: */ - - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0x00B000B0; /* suspend erase*/ - *addr = 0x00FF00FF; /* read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* reset to read mode */ - } - printf("ok.\n"); - } - if (ctrlc()) printf("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (flag) enable_interrupts(); - - return rc; -} - -/** - * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each - */ - -static int write_long (flash_info_t *info, ulong dest, ulong data) -{ - u32 * volatile addr = (u32 * volatile)dest, val; - int rc = ERR_OK; - int flag; - ulong start; - - /* read array command - just for the case... */ - *addr = 0x00FF00FF; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts(); - - /* clear status register command */ - *addr = 0x00500050; - - /* program set-up command */ - *addr = 0x00400040; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while(((val = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0x00B000B0; - goto outahere; - } - } - - /* check for errors */ - if(val & 0x001A001A) { - printf("\nFlash write error %02x at address %08lx\n", - (int)val, (unsigned long)dest); - if(val & 0x00080008) { - printf("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if(val & 0x00020002) { - printf("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if(val & 0x00100010) { - printf("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - -outahere: - /* read array command */ - *addr = 0x00FF00FF; - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -/* "long" version, uses 32bit words */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ulong data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - for (; i<4 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - if ((rc = write_long(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((ulong*)src); - if ((rc = write_long(info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_long(info, wp, data); -} diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 5b2830ce4..c41f11d60 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -120,12 +120,6 @@ int board_early_init_f(void) mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); - mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -143,7 +137,7 @@ int board_early_init_f(void) mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8); + mx31_set_gpr(MUX_PGP_UH2, 1); return 0; @@ -237,7 +231,7 @@ static void board_nand_setup(void) mxc_setup_weimcs(3, &cs3); - __REG(IOMUXC_GPR) |= 1 << 13; + mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 89ae1115d..5aa7605f0 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_PRELOADER +#ifndef CONFIG_SPL_BUILD int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c index 1a01c3ce2..ac82d5cf3 100644 --- a/board/davinci/dm6467evm/dm6467evm.c +++ b/board/davinci/dm6467evm/dm6467evm.c @@ -24,6 +24,26 @@ DECLARE_GLOBAL_DATA_PTR; +#define REV_DM6467EVM 0 +#define REV_DM6467TEVM 1 +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] System clock frequency + * 0000b - 27 MHz + * 0001b - 33 MHz + */ +u32 get_board_rev(void) +{ + +#ifdef DAVINCI_DM6467TEVM + return REV_DM6467TEVM; +#else + return REV_DM6467EVM; +#endif + +} + int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM; diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 9d0f71bc5..720a3607a 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -35,11 +35,28 @@ #include <asm/arch/emac_defs.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/da8xx-fb.h> DECLARE_GLOBAL_DATA_PTR; #define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) +static const struct da8xx_panel lcd_panel = { + /* Casio COM57H531x */ + .name = "Casio_COM57H531x", + .width = 640, + .height = 480, + .hfp = 12, + .hbp = 144, + .hsw = 30, + .vfp = 10, + .vbp = 35, + .vsw = 3, + .pxl_clk = 25000000, + .invert_pxl_clk = 0, +}; + /* SPI0 pin muxer settings */ static const struct pinmux_config spi1_pins[] = { { pinmux(5), 1, 1 }, @@ -48,12 +65,18 @@ static const struct pinmux_config spi1_pins[] = { { pinmux(5), 1, 5 } }; -/* UART pin muxer settings */ +/* I2C pin muxer settings */ +static const struct pinmux_config i2c_pins[] = { + { pinmux(4), 2, 2 }, + { pinmux(4), 2, 3 } +}; + +/* UART0 pin muxer settings */ static const struct pinmux_config uart_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } + { pinmux(3), 2, 7 }, + { pinmux(3), 2, 6 }, + { pinmux(3), 2, 4 }, + { pinmux(3), 2, 5 } }; #ifdef CONFIG_DRIVER_TI_EMAC @@ -73,70 +96,136 @@ static const struct pinmux_config emac_pins[] = { #ifdef CONFIG_NAND_DAVINCI const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } + { pinmux(7), 1, 0}, /* CS2 */ + { pinmux(7), 0, 1}, /* CS3 in three state*/ + { pinmux(7), 1, 4 }, /* EMA_WE */ + { pinmux(7), 1, 5 }, /* EMA_OE */ + { pinmux(9), 1, 0 }, /* EMA_D[7] */ + { pinmux(9), 1, 1 }, /* EMA_D[6] */ + { pinmux(9), 1, 2 }, /* EMA_D[5] */ + { pinmux(9), 1, 3 }, /* EMA_D[4] */ + { pinmux(9), 1, 4 }, /* EMA_D[3] */ + { pinmux(9), 1, 5 }, /* EMA_D[2] */ + { pinmux(9), 1, 6 }, /* EMA_D[1] */ + { pinmux(9), 1, 7 }, /* EMA_D[0] */ + { pinmux(12), 1, 5 }, /* EMA_A[2] */ + { pinmux(12), 1, 6 }, /* EMA_A[1] */ + { pinmux(6), 1, 0 } /* EMA_CLK */ }; #endif +const struct pinmux_config gpio_pins[] = { + { pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/ + { pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/ + { pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/ + { pinmux(19), 8, 5 }, /* GPIO6[1] DISP_ON */ + { pinmux(14), 8, 1 } /* GPIO6[6] LCD_B_PWR*/ +}; + +const struct pinmux_config lcd_pins[] = { + { pinmux(17), 2, 1 }, /* LCD_D_0 */ + { pinmux(17), 2, 0 }, /* LCD_D_1 */ + { pinmux(16), 2, 7 }, /* LCD_D_2 */ + { pinmux(16), 2, 6 }, /* LCD_D_3 */ + { pinmux(16), 2, 5 }, /* LCD_D_4 */ + { pinmux(16), 2, 4 }, /* LCD_D_5 */ + { pinmux(16), 2, 3 }, /* LCD_D_6 */ + { pinmux(16), 2, 2 }, /* LCD_D_7 */ + { pinmux(18), 2, 1 }, /* LCD_D_8 */ + { pinmux(18), 2, 0 }, /* LCD_D_9 */ + { pinmux(17), 2, 7 }, /* LCD_D_10 */ + { pinmux(17), 2, 6 }, /* LCD_D_11 */ + { pinmux(17), 2, 5 }, /* LCD_D_12 */ + { pinmux(17), 2, 4 }, /* LCD_D_13 */ + { pinmux(17), 2, 3 }, /* LCD_D_14 */ + { pinmux(17), 2, 2 }, /* LCD_D_15 */ + { pinmux(18), 2, 6 }, /* LCD_PCLK */ + { pinmux(19), 2, 0 }, /* LCD_HSYNC */ + { pinmux(19), 2, 1 }, /* LCD_VSYNC */ + { pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */ +}; + +const struct pinmux_config halten_pin[] = { + { pinmux(3), 4, 2 } /* GPIO8[6] HALTEN */ +}; + static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_SPI_FLASH PINMUX_ITEM(spi1_pins), #endif PINMUX_ITEM(uart_pins), + PINMUX_ITEM(i2c_pins), #ifdef CONFIG_NAND_DAVINCI PINMUX_ITEM(nand_pins), #endif +#ifdef CONFIG_VIDEO + PINMUX_ITEM(lcd_pins), +#endif }; static const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_UART0 }, /* console */ { DAVINCI_LPSC_GPIO }, + { DAVINCI_LPSC_LCDC }, /* LCD */ }; -int board_init(void) +int board_early_init_f(void) { + struct davinci_gpio *gpio6_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK67; + + /* PinMux for GPIO */ + if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) + return 1; + + /* Set the RESETOUTn low */ + writel((readl(&gpio6_base->set_data) & ~(1 << 15)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir); + + /* Set U0_SW0 low for UART0 as console*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 10)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir); + + /* Set U0_SW1 low for UART0 as console*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 12)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir); + + /* Set LCD_B_PWR low to power down LCD Backlight*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 6)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir); + + /* Set DISP_ON low to disable LCD output*/ + writel((readl(&gpio6_base->set_data) & ~(1 << 1)), + &gpio6_base->set_data); + writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir); + #ifndef CONFIG_USE_IRQ irq_init(); #endif - -#ifdef CONFIG_NAND_DAVINCI /* * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ +#ifdef CONFIG_NAND_DAVINCI writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(0) | + DAVINCI_ABCR_WSTROBE(1) | DAVINCI_ABCR_WHOLD(0) | DAVINCI_ABCR_RSETUP(0) | DAVINCI_ABCR_RSTROBE(1) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(0) | DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->ab2cr); /* CS3 */ + &davinci_emif_regs->ab1cr); /* CS2 */ #endif - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_EA20; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - /* * Power on required peripherals * ARM does not have access by default to PSC0 and PSC1 @@ -150,7 +239,7 @@ int board_init(void) writel(readl(&davinci_syscfg_regs->suspsrc) & ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | - DAVINCI_SYSCFG_SUSPSRC_UART2), + DAVINCI_SYSCFG_SUSPSRC_UART0), &davinci_syscfg_regs->suspsrc); /* configure pinmux settings */ @@ -167,10 +256,60 @@ int board_init(void) /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart2_ctrl_regs->pwremu_mgmt); + &davinci_uart0_ctrl_regs->pwremu_mgmt); + + /* + * Reconfigure the LCDC priority to the highest to ensure that + * the throughput/latency requirements for the LCDC are met. + */ + writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff, + &davinci_syscfg_regs->mstpri[2]); + + /* Set LCD_B_PWR low to power up LCD Backlight*/ + writel((readl(&gpio6_base->set_data) | (1 << 6)), + &gpio6_base->set_data); + + /* Set DISP_ON low to disable LCD output*/ + writel((readl(&gpio6_base->set_data) | (1 << 1)), + &gpio6_base->set_data); + + return 0; +} + +int board_init(void) +{ + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_EA20; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + da8xx_video_init(&lcd_panel, 16); + + return 0; +} + +#ifdef BOARD_LATE_INIT + +int board_late_init(void) +{ + struct davinci_gpio *gpio8_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK8; + + /* PinMux for HALTEN */ + if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) + return 1; + + /* Set HALTEN to high */ + writel((readl(&gpio8_base->set_data) | (1 << 6)), + &gpio8_base->set_data); + writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir); + + setenv("stdout", "serial"); return 0; } +#endif /* BOARD_LATE_INIT */ #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/board/csb226/Makefile b/board/denx/m28evk/Makefile index 6fe9becaa..b6f002fe3 100644 --- a/board/csb226/Makefile +++ b/board/denx/m28evk/Makefile @@ -25,7 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := csb226.o flash.o +ifndef CONFIG_SPL_BUILD +COBJS := m28evk.o +endif + +ifdef CONFIG_SPL_BUILD +COBJS := mem_init.o mmc_boot.o power_init.o memsize.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -33,6 +39,13 @@ OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +all: $(ALL) + +ifdef CONFIG_SPL_BUILD +memsize.c: + ln -sf $(TOPDIR)/common/memsize.c $@ +endif + ######################################################################### # defines $(obj).depend target diff --git a/board/denx/m28evk/m28_init.h b/board/denx/m28evk/m28_init.h new file mode 100644 index 000000000..98d363199 --- /dev/null +++ b/board/denx/m28evk/m28_init.h @@ -0,0 +1,41 @@ +/* + * Freescale i.MX28 SPL functions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M28_INIT_H__ +#define __M28_INIT_H__ + +void early_delay(int delay); + +void mx28_power_init(void); + +#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +void mx28_power_wait_pswitch(void); +#else +static inline void mx28_power_wait_pswitch(void) { } +#endif + +void mx28_mem_init(void); + +#endif /* __M28_INIT_H__ */ diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c new file mode 100644 index 000000000..8cf3dc9d4 --- /dev/null +++ b/board/denx/m28evk/m28evk.c @@ -0,0 +1,216 @@ +/* + * DENX M28 module + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + +#ifdef CONFIG_CMD_USB + mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); + mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | + MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); + gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0); +#endif + + return 0; +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#define HW_DIGCTRL_SCRATCH0 0x8001c280 +#define HW_DIGCTRL_SCRATCH1 0x8001c290 +int dram_init(void) +{ + uint32_t sz[2]; + + sz[0] = readl(HW_DIGCTRL_SCRATCH0); + sz[1] = readl(HW_DIGCTRL_SCRATCH1); + + if (sz[0] != sz[1]) { + printf("MX28:\n" + "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" + "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" + "verify these two registers contain valid RAM size!\n"); + hang(); + } + + gd->ram_size = sz[0]; + return 0; +} + +#ifdef CONFIG_CMD_MMC +static int m28_mmc_wp(int id) +{ + if (id != 0) { + printf("MXS MMC: Invalid card selected (card id = %d)\n", id); + return 1; + } + + return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10); +} + +int board_mmc_init(bd_t *bis) +{ + /* Configure WP as output */ + gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10); + + return mxsmmc_initialize(bis, 0, m28_mmc_wp); +} +#endif + +#ifdef CONFIG_CMD_NET + +#define MII_OPMODE_STRAP_OVERRIDE 0x16 +#define MII_PHY_CTRL1 0x1e +#define MII_PHY_CTRL2 0x1f + +int fecmxc_mii_postcall(int phy) +{ + miiphy_write("FEC1", phy, MII_BMCR, 0x9000); + miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); + if (phy == 3) + miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, + CLKCTRL_ENET_TIME_SEL_RMII_CLK); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC1\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC0"); + if (!dev) { + printf("FEC MXS: Unable to get FEC0 device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXS: Unable to register FEC0 mii postcall\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC1"); + if (!dev) { + printf("FEC MXS: Unable to get FEC1 device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXS: Unable to register FEC1 mii postcall\n"); + return ret; + } + + return ret; +} + +#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP + +#define MXS_OCOTP_MAX_TIMEOUT 1000000 +void imx_get_mac_from_fuse(char *mac) +{ + struct mx28_ocotp_regs *ocotp_regs = + (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; + uint32_t data; + + memset(mac, 0, 6); + + writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); + + if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, + MXS_OCOTP_MAX_TIMEOUT)) { + printf("MXS FEC: Can't get MAC from OCOTP\n"); + return; + } + + data = readl(&ocotp_regs->hw_ocotp_cust0); + + mac[0] = 0x00; + mac[1] = 0x04; + mac[2] = (data >> 24) & 0xff; + mac[3] = (data >> 16) & 0xff; + mac[4] = (data >> 8) & 0xff; + mac[5] = data & 0xff; +} +#else +void imx_get_mac_from_fuse(char *mac) +{ + memset(mac, 0, 6); +} +#endif + +#endif diff --git a/board/denx/m28evk/mem_init.c b/board/denx/m28evk/mem_init.c new file mode 100644 index 000000000..17d1f9b6a --- /dev/null +++ b/board/denx/m28evk/mem_init.c @@ -0,0 +1,240 @@ +/* + * Freescale i.MX28 RAM init + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> + +#include "m28_init.h" + +uint32_t dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a, + 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, + 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202, + 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, + 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200, + 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27, + 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201, + 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303, + 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200, + 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001 +}; + +void init_m28_200mhz_ddr2(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); +} + +void mx28_mem_init_clock(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Gate EMI clock */ + writel(CLKCTRL_FRAC0_CLKGATEEMI, + &clkctrl_regs->hw_clkctrl_frac0_set); + + /* EMI = 205MHz */ + writel(CLKCTRL_FRAC0_EMIFRAC_MASK, + &clkctrl_regs->hw_clkctrl_frac0_set); + writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) & + CLKCTRL_FRAC0_EMIFRAC_MASK, + &clkctrl_regs->hw_clkctrl_frac0_clr); + + /* Ungate EMI clock */ + writel(CLKCTRL_FRAC0_CLKGATEEMI, + &clkctrl_regs->hw_clkctrl_frac0_clr); + + early_delay(11000); + + writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | + (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), + &clkctrl_regs->hw_clkctrl_emi); + + /* Unbypass EMI */ + writel(CLKCTRL_CLKSEQ_BYPASS_EMI, + &clkctrl_regs->hw_clkctrl_clkseq_clr); + + early_delay(10000); +} + +void mx28_mem_setup_cpu_and_hbus(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* CPU = 454MHz and ungate CPU clock */ + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, + CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU, + 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET); + + /* Set CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + /* HBUS = 151MHz */ + writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); + writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, + &clkctrl_regs->hw_clkctrl_hbus_clr); + + early_delay(10000); + + /* CPU clock divider = 1 */ + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, + CLKCTRL_CPU_DIV_CPU_MASK, 1); + + /* Disable CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); +} + +void mx28_mem_setup_vdda(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | + (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | + POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, + &power_regs->hw_power_vddactrl); +} + +void mx28_mem_setup_vddd(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | + (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW, + &power_regs->hw_power_vdddctrl); +} + +#define HW_DIGCTRL_SCRATCH0 0x8001c280 +#define HW_DIGCTRL_SCRATCH1 0x8001c290 +void data_abort_memdetect_handler(void) __attribute__((naked)); +void data_abort_memdetect_handler(void) +{ + asm volatile("subs pc, r14, #4"); +} + +void mx28_mem_get_size(void) +{ + uint32_t sz, da; + uint32_t *vt = (uint32_t *)0x20; + + /* Replace the DABT handler. */ + da = vt[4]; + vt[4] = (uint32_t)&data_abort_memdetect_handler; + + sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + writel(sz, HW_DIGCTRL_SCRATCH0); + writel(sz, HW_DIGCTRL_SCRATCH1); + + /* Restore the old DABT handler. */ + vt[4] = da; +} + +void mx28_mem_init(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mx28_pinctrl_regs *pinctrl_regs = + (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set DDR2 mode */ + writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + /* Power up PLL0 */ + writel(CLKCTRL_PLL0CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + + early_delay(11000); + + mx28_mem_init_clock(); + + mx28_mem_setup_vdda(); + + /* + * Configure the DRAM registers + */ + + /* Clear START bit from DRAM_CTL16 */ + clrbits_le32(MXS_DRAM_BASE + 0x40, 1); + + init_m28_200mhz_ddr2(); + + /* Clear SREFRESH bit from DRAM_CTL17 */ + clrbits_le32(MXS_DRAM_BASE + 0x44, 1); + + /* Set START bit in DRAM_CTL16 */ + setbits_le32(MXS_DRAM_BASE + 0x40, 1); + + /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ + while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) + ; + + mx28_mem_setup_vddd(); + + early_delay(10000); + + mx28_mem_setup_cpu_and_hbus(); + + mx28_mem_get_size(); +} diff --git a/board/denx/m28evk/mmc_boot.c b/board/denx/m28evk/mmc_boot.c new file mode 100644 index 000000000..86d3ab5e1 --- /dev/null +++ b/board/denx/m28evk/mmc_boot.c @@ -0,0 +1,273 @@ +/* + * Freescale i.MX28 Boot setup + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> + +#include "m28_init.h" + +/* + * This delay function is intended to be used only in early stage of boot, where + * clock are not set up yet. The timer used here is reset on every boot and + * takes a few seconds to roll. The boot doesn't take that long, so to keep the + * code simple, it doesn't take rolling into consideration. + */ +#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 +void early_delay(int delay) +{ + uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + st += delay; + while (st > readl(HW_DIGCTRL_MICROSECONDS)) + ; +} + +#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* LED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED, + + /* framebuffer */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, + + /* UART1 */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + MX28_PAD_AUART0_TX__DUART_RTS, + MX28_PAD_AUART0_RX__DUART_CTS, + + /* UART2 */ + MX28_PAD_AUART1_RX__AUART1_RX, + MX28_PAD_AUART1_TX__AUART1_TX, + MX28_PAD_AUART1_RTS__AUART1_RTS, + MX28_PAD_AUART1_CTS__AUART1_CTS, + + /* CAN */ + MX28_PAD_GPMI_RDY2__CAN0_TX, + MX28_PAD_GPMI_RDY3__CAN0_RX, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* TSC2007 */ + MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), + MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */ + MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */ + + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* FEC Ethernet */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SPI2 (for flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), +}; + +void board_init_ll(void) +{ + mxs_iomux_setup_multiple_pads(iomux_setup, ARRAY_SIZE(iomux_setup)); + mx28_power_init(); + mx28_mem_init(); + mx28_power_wait_pswitch(); +} + +/* Support aparatus */ +inline void board_init_f(unsigned long bootflag) +{ + for (;;) + ; +} + +inline void board_init_r(gd_t *id, ulong dest_addr) +{ + for (;;) + ; +} + +inline int printf(const char *fmt, ...) +{ + return 0; +} + +inline void __coloured_LED_init(void) {} +inline void __red_LED_on(void) {} +void coloured_LED_init(void) + __attribute__((weak, alias("__coloured_LED_init"))); +void red_LED_on(void) + __attribute__((weak, alias("__red_LED_on"))); +void hang(void) __attribute__ ((noreturn)); +void hang(void) +{ + for (;;) + ; +} diff --git a/board/denx/m28evk/power_init.c b/board/denx/m28evk/power_init.c new file mode 100644 index 000000000..27322b4ec --- /dev/null +++ b/board/denx/m28evk/power_init.c @@ -0,0 +1,913 @@ +/* + * Freescale i.MX28 Boot PMIC init + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +#include "m28_init.h" + +void mx28_power_clock2xtal(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Set XTAL as CPU reference clock */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); +} + +void mx28_power_clock2pll(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + writel(CLKCTRL_PLL0CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + early_delay(100); + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); +} + +void mx28_power_clear_auto_restart(void) +{ + struct mx28_rtc_regs *rtc_regs = + (struct mx28_rtc_regs *)MXS_RTC_BASE; + + writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) + ; + + writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) + ; + + /* + * Due to the hardware design bug of mx28 EVK-A + * we need to set the AUTO_RESTART bit. + */ + if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) + return; + + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) + ; + + setbits_le32(&rtc_regs->hw_rtc_persistent0, + RTC_PERSISTENT0_AUTO_RESTART); + writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set); + writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) + ; + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) + ; +} + +void mx28_power_set_linreg(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Set linear regulator 25mV below switching converter */ + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_LINREG_OFFSET_MASK, + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrsetbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_LINREG_OFFSET_MASK, + POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_LINREG_OFFSET_MASK, + POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); +} + +void mx28_power_setup_5v_detect(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Start 5V detection */ + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_TRSH_MASK, + POWER_5VCTRL_VBUSVALID_TRSH_4V4 | + POWER_5VCTRL_PWRUP_VBUS_CMPS); +} + +void mx28_src_power_init(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Improve efficieny and reduce transient ripple */ + writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | + POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); + + clrsetbits_le32(&power_regs->hw_power_dclimits, + POWER_DCLIMITS_POSLIMIT_BUCK_MASK, + 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET); + + setbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_EN_BATADJ); + + /* Increase the RCSCALE level for quick DCDC response to dynamic load */ + clrsetbits_le32(&power_regs->hw_power_loopctrl, + POWER_LOOPCTRL_EN_RCSCALE_MASK, + POWER_LOOPCTRL_RCSCALE_THRESH | + POWER_LOOPCTRL_EN_RCSCALE_8X); + + clrsetbits_le32(&power_regs->hw_power_minpwr, + POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); + + /* 5V to battery handoff ... FIXME */ + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + early_delay(30); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); +} + +void mx28_power_init_4p2_params(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Setup 4P2 parameters */ + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, + POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_HEADROOM_ADJ_MASK, + 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); + + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_DROPOUT_CTRL_MASK, + POWER_DCDC4P2_DROPOUT_CTRL_100MV | + POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +} + +void mx28_enable_4p2_dcdc_input(int xfer) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; + uint32_t prev_5v_brnout, prev_5v_droop; + + prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_PWDN_5VBRNOUT; + prev_5v_droop = readl(&power_regs->hw_power_ctrl) & + POWER_CTRL_ENIRQ_VDD5V_DROOP; + + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); + + clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); + + if (xfer && (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return; + } + + /* + * Recording orignal values that will be modified temporarlily + * to handle a chip bug. See chip errata for CQ ENGR00115837 + */ + tmp = readl(&power_regs->hw_power_5vctrl); + vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK; + vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT; + + pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO; + + /* + * Disable mechanisms that get erroneously tripped by when setting + * the DCDC4P2 EN_DCDC + */ + clrbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_5VDETECT | + POWER_5VCTRL_VBUSVALID_TRSH_MASK); + + writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set); + + if (xfer) { + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_DCDC_XFER); + early_delay(20); + clrbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_DCDC_XFER); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_ENABLE_DCDC); + } else { + setbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + } + + early_delay(25); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); + + if (vbus_5vdetect) + writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set); + + if (!pwd_bo) + clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); + + while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) + clrbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_VBUS_VALID_IRQ); + + if (prev_5v_brnout) { + writel(POWER_5VCTRL_PWDN_5VBRNOUT, + &power_regs->hw_power_5vctrl_set); + writel(POWER_RESET_UNLOCK_KEY, + &power_regs->hw_power_reset); + } else { + writel(POWER_5VCTRL_PWDN_5VBRNOUT, + &power_regs->hw_power_5vctrl_clr); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); + } + + while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) + clrbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_VDD5V_DROOP_IRQ); + + if (prev_5v_droop) + clrbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_ENIRQ_VDD5V_DROOP); + else + setbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_ENIRQ_VDD5V_DROOP); +} + +void mx28_power_init_4p2_regulator(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp, tmp2; + + setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); + + writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); + + writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + &power_regs->hw_power_5vctrl_clr); + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); + + /* Power up the 4p2 rail and logic/control */ + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + /* + * Start charging up the 4p2 capacitor. We ramp of this charge + * gradually to avoid large inrush current from the 5V cable which can + * cause transients/problems + */ + mx28_enable_4p2_dcdc_input(0); + + if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { + /* + * If we arrived here, we were unable to recover from mx23 chip + * errata 5837. 4P2 is disabled and sufficient battery power is + * not present. Exiting to not enable DCDC power during 5V + * connected state. + */ + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_set); + hang(); + } + + /* + * Here we set the 4p2 brownout level to something very close to 4.2V. + * We then check the brownout status. If the brownout status is false, + * the voltage is already close to the target voltage of 4.2V so we + * can go ahead and set the 4P2 current limit to our max target limit. + * If the brownout status is true, we need to ramp us the current limit + * so that we don't cause large inrush current issues. We step up the + * current limit until the brownout status is false or until we've + * reached our maximum defined 4p2 current limit. + */ + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_BO_MASK, + 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ + + if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { + setbits_le32(&power_regs->hw_power_5vctrl, + 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + } else { + tmp = (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> + POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; + while (tmp < 0x3f) { + if (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DCDC_4P2_BO)) { + tmp = readl(&power_regs->hw_power_5vctrl); + tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; + early_delay(100); + writel(tmp, &power_regs->hw_power_5vctrl); + break; + } else { + tmp++; + tmp2 = readl(&power_regs->hw_power_5vctrl); + tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; + tmp2 |= tmp << + POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; + writel(tmp2, &power_regs->hw_power_5vctrl); + early_delay(100); + } + } + } + + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); + writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +} + +void mx28_power_init_dcdc_4p2_source(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + if (!(readl(&power_regs->hw_power_dcdc4p2) & + POWER_DCDC4P2_ENABLE_DCDC)) { + hang(); + } + + mx28_enable_4p2_dcdc_input(1); + + if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + writel(POWER_5VCTRL_ENABLE_DCDC, + &power_regs->hw_power_5vctrl_clr); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_set); + } +} + +void mx28_power_enable_4p2(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t vdddctrl, vddactrl, vddioctrl; + uint32_t tmp; + + vdddctrl = readl(&power_regs->hw_power_vdddctrl); + vddactrl = readl(&power_regs->hw_power_vddactrl); + vddioctrl = readl(&power_regs->hw_power_vddioctrl); + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | + POWER_VDDACTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); + + mx28_power_init_4p2_params(); + mx28_power_init_4p2_regulator(); + + /* Shutdown battery (none present) */ + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); + writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); + + mx28_power_init_dcdc_4p2_source(); + + writel(vdddctrl, &power_regs->hw_power_vdddctrl); + early_delay(20); + writel(vddactrl, &power_regs->hw_power_vddactrl); + early_delay(20); + writel(vddioctrl, &power_regs->hw_power_vddioctrl); + + /* + * Check if FET is enabled on either powerout and if so, + * disable load. + */ + tmp = 0; + tmp |= !(readl(&power_regs->hw_power_vdddctrl) & + POWER_VDDDCTRL_DISABLE_FET); + tmp |= !(readl(&power_regs->hw_power_vddactrl) & + POWER_VDDACTRL_DISABLE_FET); + tmp |= !(readl(&power_regs->hw_power_vddioctrl) & + POWER_VDDIOCTRL_DISABLE_FET); + if (tmp) + writel(POWER_CHARGE_ENABLE_LOAD, + &power_regs->hw_power_charge_clr); +} + +void mx28_boot_valid_5v(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* + * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V + * disconnect event. FIXME + */ + writel(POWER_5VCTRL_VBUSVALID_5VDETECT, + &power_regs->hw_power_5vctrl_set); + + /* Configure polarity to check for 5V disconnection. */ + writel(POWER_CTRL_POLARITY_VBUSVALID | + POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, + &power_regs->hw_power_ctrl_clr); + + writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, + &power_regs->hw_power_ctrl_clr); + + mx28_power_enable_4p2(); +} + +void mx28_powerdown(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); +} + +void mx28_handle_5v_conflict(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_BO_OFFSET_MASK); + + for (;;) { + tmp = readl(&power_regs->hw_power_sts); + + if (tmp & POWER_STS_VDDIO_BO) { + mx28_powerdown(); + break; + } + + if (tmp & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + break; + } else { + mx28_powerdown(); + break; + } + } +} + +int mx28_get_batt_volt(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + return volt; +} + +int mx28_is_batt_ready(void) +{ + return (mx28_get_batt_volt() >= 3600); +} + +void mx28_5v_boot(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* + * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, + * but their implementation always returns 1 so we omit it here. + */ + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + return; + } + + early_delay(1000); + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + return; + } + + mx28_handle_5v_conflict(); +} + +void mx28_init_batt_bo(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Brownout at 3V */ + clrsetbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_BRWNOUT_LVL_MASK, + 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); + + writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); + writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); +} + +void mx28_switch_vddd_to_dcdc_source(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_LINREG_OFFSET_MASK, + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_DISABLE_STEPPING); +} + +int mx28_is_batt_good(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt; + + volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + + if ((volt >= 2400) && (volt <= 4300)) + return 1; + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + clrsetbits_le32(&power_regs->hw_power_charge, + POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); + + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + early_delay(500000); + + volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + + if (volt >= 3500) + return 0; + + if (volt >= 2400) + return 1; + + writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + &power_regs->hw_power_charge_clr); + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + + return 0; +} + +void mx28_power_configure_power_source(void) +{ + mx28_src_power_init(); + + mx28_5v_boot(); + mx28_power_clock2pll(); + + mx28_init_batt_bo(); + mx28_switch_vddd_to_dcdc_source(); +} + +void mx28_enable_output_rail_protection(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | + POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_PWDN_BRNOUT); +} + +int mx28_get_vddio_power_source_off(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + tmp = readl(&power_regs->hw_power_vddioctrl); + if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { + if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + + if (!(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + } + + return 0; + +} + +int mx28_get_vddd_power_source_off(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + tmp = readl(&power_regs->hw_power_vdddctrl); + if (tmp & POWER_VDDDCTRL_DISABLE_FET) { + if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (!(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return 1; + } + } + + if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) { + if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) { + return 1; + } + } + + return 0; +} + +void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t cur_target, diff, bo_int = 0; + uint32_t powered_by_linreg = 0; + + new_brownout = new_target - new_brownout; + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + + powered_by_linreg = mx28_get_vddio_power_source_off(); + if (new_target > cur_target) { + + if (powered_by_linreg) { + bo_int = readl(&power_regs->hw_power_vddioctrl); + clrbits_le32(&power_regs->hw_power_vddioctrl, + POWER_CTRL_ENIRQ_VDDIO_BO); + } + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_BO_OFFSET_MASK); + do { + if (new_target - cur_target > 100) + diff = cur_target + 100; + else + diff = new_target; + + diff -= 2800; + diff /= 50; + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + } while (new_target > cur_target); + + if (powered_by_linreg) { + writel(POWER_CTRL_VDDIO_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO) + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_CTRL_ENIRQ_VDDIO_BO); + } + } else { + do { + if (cur_target - new_target > 100) + diff = cur_target - 100; + else + diff = new_target; + + diff -= 2800; + diff /= 50; + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + } while (new_target < cur_target); + } + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); +} + +void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t cur_target, diff, bo_int = 0; + uint32_t powered_by_linreg = 0; + + new_brownout = new_target - new_brownout; + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + + powered_by_linreg = mx28_get_vddd_power_source_off(); + if (new_target > cur_target) { + if (powered_by_linreg) { + bo_int = readl(&power_regs->hw_power_vdddctrl); + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_CTRL_ENIRQ_VDDD_BO); + } + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK); + + do { + if (new_target - cur_target > 100) + diff = cur_target + 100; + else + diff = new_target; + + diff -= 800; + diff /= 25; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + } while (new_target > cur_target); + + if (powered_by_linreg) { + writel(POWER_CTRL_VDDD_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO) + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_CTRL_ENIRQ_VDDD_BO); + } + } else { + do { + if (cur_target - new_target > 100) + diff = cur_target - 100; + else + diff = new_target; + + diff -= 800; + diff /= 25; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + } while (new_target < cur_target); + } + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); +} + +void mx28_power_init(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + mx28_power_clock2xtal(); + mx28_power_clear_auto_restart(); + mx28_power_set_linreg(); + mx28_power_setup_5v_detect(); + mx28_power_configure_power_source(); + mx28_enable_output_rail_protection(); + + mx28_power_set_vddio(3300, 3150); + + mx28_power_set_vddd(1350, 1200); + + writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | + POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | + POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | + POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); + + writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); + + early_delay(1000); +} + +#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +void mx28_power_wait_pswitch(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) + ; +} +#endif diff --git a/board/denx/m28evk/start.S b/board/denx/m28evk/start.S new file mode 100644 index 000000000..94696d6cd --- /dev/null +++ b/board/denx/m28evk/start.S @@ -0,0 +1,234 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Groger <mag@sysgo.de> + * Copyright (c) 2002 Alex Zupke <azu@sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> + * Copyright (c) 2003 Kshitij <kshitij@ti.com> + * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> + * + * Change to support call back into iMX28 bootrom + * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-offsets.h> +#include <config.h> +#include <common.h> +#include <version.h> + +#if defined(CONFIG_OMAP1610) +#include <./configs/omap1510.h> +#elif defined(CONFIG_OMAP730) +#include <./configs/omap730.h> +#endif + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: + b reset + b undefined_instruction + b software_interrupt + b prefetch_abort + b data_abort + b not_used + b irq + b fiq + +/* + * Vector table, located at address 0x20. + * This table allows the code running AFTER SPL, the U-Boot, to install it's + * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, + * including it's interrupt vectoring table and the table at 0x0 is still the + * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table + * is still used. + */ +_vt_reset: + .word _reset +_vt_undefined_instruction: + .word _hang +_vt_software_interrupt: + .word _hang +_vt_prefetch_abort: + .word _hang +_vt_data_abort: + .word _hang +_vt_not_used: + .word _reset +_vt_irq: + .word _hang +_vt_fiq: + .word _hang + +reset: + ldr pc, _vt_reset +undefined_instruction: + ldr pc, _vt_undefined_instruction +software_interrupt: + ldr pc, _vt_software_interrupt +prefetch_abort: + ldr pc, _vt_prefetch_abort +data_abort: + ldr pc, _vt_data_abort +not_used: + ldr pc, _vt_not_used +irq: + ldr pc, _vt_irq +fiq: + ldr pc, _vt_fiq + + .balignl 16,0xdeadbeef + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +.globl _TEXT_BASE +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +/* + * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word __bss_end__ - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +_reset: + /* + * Store all registers on old stack pointer, this will allow us later to + * return to the BootROM and let the BootROM load U-Boot into RAM. + */ + push {r0-r12,r14} + + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + bl board_init_ll + + pop {r0-r12,r14} + bx lr + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr /* back to my caller */ + + .align 5 +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ diff --git a/board/denx/m28evk/u-boot-spl.lds b/board/denx/m28evk/u-boot-spl.lds new file mode 100644 index 000000000..e296a92ed --- /dev/null +++ b/board/denx/m28evk/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + board/denx/m28evk/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/denx/m28evk/u-boot.bd b/board/denx/m28evk/u-boot.bd new file mode 100644 index 000000000..3ce7f92d7 --- /dev/null +++ b/board/denx/m28evk/u-boot.bd @@ -0,0 +1,14 @@ +sources { + u_boot_spl="spl/u-boot-spl.bin"; + u_boot="u-boot.bin"; +} + +section (0) { + load u_boot_spl > 0x0000; + load ivt (entry = 0x0014) > 0x8000; + hab call 0x8000; + + load u_boot > 0x40000100; + load ivt (entry = 0x40000100) > 0x8000; + hab call 0x8000; +} diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 2a5636c07..c4ed82029 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -23,7 +23,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/ic/sc520.h> +#include <asm/arch/sc520.h> #include <net.h> #include <netdev.h> diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c index d97387ecd..29d13d251 100644 --- a/board/eNET/eNET_pci.c +++ b/board/eNET/eNET_pci.c @@ -27,7 +27,7 @@ #include <common.h> #include <pci.h> #include <asm/pci.h> -#include <asm/ic/pci.h> +#include <asm/arch/pci.h> static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 77e551964..4241f6e10 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -27,11 +27,9 @@ * that is used by U-boot to its final destination. */ -/* #include <asm/ic/sc520_defs.h> */ - #include "config.h" #include "hardware.h" -#include <asm/ic/sc520.h> +#include <asm/arch/sc520.h> .text .section .start16, "ax" diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c index 2fbdb2771..88313287f 100644 --- a/board/eltec/mhpc/flash.c +++ b/board/eltec/mhpc/flash.c @@ -311,7 +311,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp; FPW data; - int count, i, l, rc, port_width; + int i, l, rc, port_width; if (info->flash_id == FLASH_UNKNOWN) { return 4; @@ -330,9 +330,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ if ((l = addr - wp) != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i=0, cp=wp; i<l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } + for (; i<port_width && cnt>0; ++i) { data = (data << 8) | *src++; --cnt; @@ -351,7 +351,6 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle word aligned part */ - count = 0; while (cnt >= port_width) { data = 0; for (i=0; i<port_width; ++i) { diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c index c1d6e9100..182cabca1 100644 --- a/board/ep82xxm/ep82xxm.c +++ b/board/ep82xxm/ep82xxm.c @@ -31,6 +31,7 @@ #include <pci.h> #endif #include <miiphy.h> +#include <linux/compiler.h> /* * I/O Port configuration table @@ -230,8 +231,8 @@ phys_size_t initdram(int board_type) uint psdmr = CONFIG_SYS_PSDMR; int i; - unsigned char ramtmp; unsigned char *ramptr1 = (unsigned char *)0x00000110; + __maybe_unused unsigned char ramtmp; memctl->memc_mptpr = CONFIG_SYS_MPTPR; diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 4dfea7196..fc60545d0 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -91,7 +91,6 @@ int au_check_cksum_valid(int i, long nbytes) int au_check_header_valid(int i, long nbytes) { image_header_t *hdr; - unsigned long checksum; hdr = (image_header_t *)LOAD_ADDR; #if defined(CONFIG_FIT) @@ -127,9 +126,6 @@ int au_check_header_valid(int i, long nbytes) return -1; } - /* recycle checksum */ - checksum = image_get_data_size (hdr); - return 0; } @@ -397,7 +393,7 @@ int do_auto_update(void) { block_dev_desc_t *stor_dev = NULL; long sz; - int i, res, cnt, old_ctrlc, got_ctrlc; + int i, res, cnt, old_ctrlc; char buffer[32]; char str[80]; int n; @@ -473,8 +469,6 @@ int do_auto_update(void) /* let the user break out of the loop */ if (ctrlc() || had_ctrlc ()) { clear_ctrlc (); - if (res < 0) - got_ctrlc = 1; break; } cnt++; diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c index 9b578b5f5..9de51f3ea 100644 --- a/board/esd/cpci5200/strataflash.c +++ b/board/esd/cpci5200/strataflash.c @@ -678,12 +678,10 @@ static ulong flash_get_size(ulong base, int banknum) static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) { - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *) dest; + cptr.cp = (uchar *)dest; /* Check if Flash is (sufficiently) erased */ switch (info->portwidth) { diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index f27d65ed1..08311c963 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -566,7 +566,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) volatile unsigned int *ptr; int count = 0; int count2 = 0; - int status; + int status = 0; char addr[16]; char str[] = "\\|/-"; char *local_args[2]; @@ -622,7 +622,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; } - return 0; + return status; } U_BOOT_CMD( diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 615e32af9..9767cf2ca 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -47,18 +47,6 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG -/* #define DEBUG */ -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit(void); /* setup delay line of Mv64360 */ /* ------------------------------------------------------------------------- */ @@ -250,8 +238,6 @@ NSto10PS(unsigned char spd_byte) /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) { - unsigned long spd_checksum; - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; unsigned int i, j, density = 1, devicesForErrCheck = 0; @@ -264,7 +250,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; @@ -275,11 +261,11 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) ret = 0; - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 2, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm') @@ -345,7 +331,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -402,8 +388,9 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /*------------------------------------------------------------------------------------------------------------------------------*/ /* calculate SPD checksum */ /*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; #if 0 /* test-only */ + spd_checksum = 0; + for (i = 0; i <= 62; i++) { spd_checksum += data[i]; } @@ -424,46 +411,40 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; #ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + debug("Dram_type in slot %d is: SDRAM\n", + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); + debug("Dram_type in slot %d is: DDRAM\n", + dimmInfo->slot); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + debug("Module Number of row addresses: %d\n", + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + debug("Module Number of col addresses: %d\n", + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + debug("Number of Banks on Mod. : %d\n", + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf - ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + debug("Module Data Width: %d\n", + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -471,33 +452,27 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -516,9 +491,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -531,9 +505,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out: %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Clock To Data Out: %d.%2d [ns]\n", + leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -541,42 +514,37 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) #ifdef CONFIG_MV64360_ECC case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + debug("Error Check Type (0=NONE): %d\n", + dimmInfo->errorCheckType); break; #endif /* of ifdef CONFIG_MV64360_ECC */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf - ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + debug("Sdram Width: %d\n", + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + debug("Error Check Data Width: %d\n", + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + debug("Minimum Clock Delay: %d\n", + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -592,26 +560,24 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + debug("Number Of Banks On Each Chip: %d\n", + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -631,34 +597,32 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf - ("%d, ", - k + 1)); + debug("%d, ", + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -670,8 +634,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -679,8 +642,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -688,36 +650,31 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -736,32 +693,29 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf - ("Max. Cas Latencies (SD): %d\n", + debug("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -771,7 +725,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -784,62 +738,47 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (data[i] & BIT5) >> 5; dimmInfo->redundantRowAddressing = (data[i] & BIT6) >> 6; -#ifdef DEBUG + if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug(" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug(" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug(" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug(" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug(" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug(" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug(" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug(" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug(" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug(" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug(" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug(" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug(" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug(" - redundant Row Addressing: No \n"); -#endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -851,50 +790,37 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (data[i] & BIT4) >> 4; dimmInfo->suported5PercentUpperVCC = (data[i] & BIT5) >> 5; -#ifdef DEBUG + if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug(" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug(" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug(" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug(" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug(" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug(" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug(" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug(" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug(" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug(" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug(" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug(" - upper VCC tolerance: 10 Percent \n"); -#endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -911,9 +837,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf - ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -927,9 +852,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -946,9 +870,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf - ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -962,9 +885,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -981,12 +903,10 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", + tmemclk, tmemclk / 100, tmemclk % 100); + debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1000,12 +920,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1019,12 +935,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1033,41 +945,38 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + debug("Module Bank Density: %d\n", + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1093,9 +1002,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + debug("Address And Command Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1120,9 +1028,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + debug("Address And Command Hold Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1147,9 +1054,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + debug("Data Input Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1174,9 +1080,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + debug("Data Input Hold Time [ns]: %d.%d\n\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1213,7 +1118,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1141,11 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) cal_val = 4; } - DP (printf ("cal_val = %d\n", cal_val * 5)); + debug("cal_val = %d\n", cal_val * 5); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1267,81 +1172,74 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Program the GT with the discovered data */ if (info->registeredAddrAndControlInputs == true) - DP (printf - ("Module is registered, but we do not support registered Modules !!!\n")); + debug("Module is registered, but we do not support registered Modules !!!\n"); /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } #ifdef CONFIG_MV64360_ECC if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) { /* DRAM has ECC, so turn it on */ sdram_config_reg |= BIT18; - DP(printf("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* of ifdef CONFIG_MV64360_ECC */ /* SDRAM configuration */ GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg); - DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); + debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages controll keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + debug("sdram_open_pages_controll 0x1414: %08x\n", + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Lentency according to SPD information */ switch (info->memoryType) { case SDRAM: - DP (printf ("### SD-RAM not supported yet !!!\n")); + debug("### SD-RAM not supported yet !!!\n"); hang (); /* ToDo fill SD-RAM if needed !!!!! */ break; case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); switch (info->maxClSupported_DDR) { case DDR_CL_3: tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */ tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - DP (printf - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); break; case DDR_CL_2_5: if (tmp == 1) { /* clocks sync */ tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */ tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1349,16 +1247,14 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (tmp == 1) { /* Sync */ tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - DP (printf - ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } else { /* Not sync. */ tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - DP (printf - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1366,16 +1262,14 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (tmp == 1) { /* Sync */ tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */ tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } else { /* not sync */ tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1393,8 +1287,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } @@ -1415,8 +1308,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1428,41 +1320,39 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp = 0x02; - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); switch (info->drb_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: printf ("Error in dram size calculation\n"); - DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); return 1; } /* SDRAM bank parameters */ /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - DP (printf - ("setting up slot %d config with: %08lx \n", info->slot, tmp)); + debug("setting up slot %d config with: %08lx \n", info->slot, tmp); GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); /* ------------------------------------------------------------------------------ */ - DP (printf - ("setting up sdram_timing_control_low with: %08x \n", - 0x11511220)); + debug("setting up sdram_timing_control_low with: %08x \n", + 0x11511220); GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); @@ -1474,38 +1364,33 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", + debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU * Page 426 MV64360 */ tmp |= (1 << 26); - DP (printf - ("Before Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf - ("After Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG))); + debug("Before Buffer assignment - sdram_conf: %08x\n", + GTREGREAD (SDRAM_CONFIG)); + debug("After Buffer assignment - sdram_conf: %08x\n", + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH); - DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp)); + debug("# sdram_timing_control_high is : %08lx \n", tmp); /* SDRAM address decode register */ /* program this with the default value */ tmp = GTREGREAD (SDRAM_ADDR_CONTROL); - DP (printf - ("SDRAM address control (before: decode): %08x ", - GTREGREAD (SDRAM_ADDR_CONTROL))); + debug("SDRAM address control (before: decode): %08x ", + GTREGREAD (SDRAM_ADDR_CONTROL)); GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2)); - DP (printf - ("SDRAM address control (after: decode): %08x\n", - GTREGREAD (SDRAM_ADDR_CONTROL))); + debug("SDRAM address control (after: decode): %08x\n", + GTREGREAD (SDRAM_ADDR_CONTROL)); /* set the SDRAM configuration for each bank */ @@ -1514,8 +1399,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) int l, l1; i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1525,15 +1409,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0); GT_REG_WRITE (SDRAM_OPERATION, 0x4); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } GT_REG_WRITE (SDRAM_MODE, tmp | 0x80); GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } l1 = 0; for (l=0;l<200;l++) @@ -1542,15 +1424,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) GT_REG_WRITE (SDRAM_MODE, tmp); GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } #endif /* test only */ @@ -1597,7 +1477,7 @@ dram_size(long int *base, long int maxsize) *b=save2; if (val != cnt) { - DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr)); + debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if(cnt==STARTVAL/sizeof(long)) cnt=0; return (cnt * sizeof(long)); @@ -1690,7 +1570,6 @@ int mv_dma_transfer(int engine, ulong source_addr, phys_size_t initdram(int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = { [0 ... 3] = 0 }; ulong realsize, total, check; AUX_MEM_DIMM_INFO dimmInfo1; @@ -1709,10 +1588,10 @@ initdram(int board_type) printf("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm(0, &dimmInfo1); + (void)check_dimm(0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm(1, &dimmInfo2); + (void)check_dimm(1, &dimmInfo2); memory_map_bank(0, 0, 0); memory_map_bank(1, 0, 0); diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index 4946538f4..001480876 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -132,8 +132,6 @@ static void showPci9054 (void) static void updatePci9054 (void) { - int val; - /* * Set EEPROM write-protect register to 0 */ @@ -141,44 +139,44 @@ static void updatePci9054 (void) in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); /* Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x00, 0x905410b5); - val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ - val = PciEepromWriteLongVPD (0x08, 0x28140100); + PciEepromWriteLongVPD (0x00, 0x905410b5); + PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ + PciEepromWriteLongVPD (0x08, 0x28140100); - val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ - val = PciEepromWriteLongVPD (0x10, 0x00000000); + PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ + PciEepromWriteLongVPD (0x10, 0x00000000); /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ - val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ - val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ + PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ + PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ - val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ - val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ + PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ + PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ - val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ - val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ + PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ + PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ - val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ + PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ - val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ - val = PciEepromWriteLongVPD (0x34, 0x00000000); - val = PciEepromWriteLongVPD (0x38, 0x00000000); + PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ + PciEepromWriteLongVPD (0x34, 0x00000000); + PciEepromWriteLongVPD (0x38, 0x00000000); - val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ - val = PciEepromWriteLongVPD (0x40, 0x00000000); + PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ + PciEepromWriteLongVPD (0x40, 0x00000000); /* Extra Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ + PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ /* Offset to LAS1: Group 1: 0x00040000 */ /* Group 2: 0x00080000 */ /* Group 3: 0x000c0000 */ - val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ - val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ - val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ + PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ + PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ + PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ - val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ + PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); } @@ -186,8 +184,6 @@ static void updatePci9054 (void) static void clearPci9054 (void) { - int val; - /* * Set EEPROM write-protect register to 0 */ @@ -195,8 +191,8 @@ static void clearPci9054 (void) in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); /* Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x00, 0xffffffff); - val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ + PciEepromWriteLongVPD (0x00, 0xffffffff); + PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ printf ("Finished clearing PLX PCI9054 EEPROM!\n"); } diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 13f901942..f570ef340 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -42,7 +42,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned int *ptr = 0; int count = 0; int count2 = 0; - int status; int i; char addr[16]; char str[] = "\\|/-"; @@ -99,7 +98,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) local_args[0] = argv[0]; local_args[1] = NULL; - status = do_bootm (cmdtp, 0, 1, local_args); + do_bootm (cmdtp, 0, 1, local_args); } return 0; diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index 83dbfcbbd..2e07ac120 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -327,13 +327,11 @@ int phypower(int flag) int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - int status; + if (argv[1][0] == '0') + (void)phypower(0); + else + (void)phypower(1); - if (argv[1][0] == '0') { - status = phypower(0); - } else { - status = phypower(1); - } return (0); } diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c index eb895817d..93ad57a26 100644 --- a/board/etin/kvme080/multiverse.c +++ b/board/etin/kvme080/multiverse.c @@ -17,6 +17,7 @@ #include <common.h> #include <asm/io.h> #include <pci.h> +#include <linux/compiler.h> #include "multiverse.h" @@ -103,7 +104,7 @@ int multiv_reset(unsigned long base) void multiv_auto_slot_id(unsigned long base) { - unsigned int vector; + __maybe_unused unsigned int vector; int slot_id = 1; if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) { *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe; diff --git a/board/etx094/flash.c b/board/etx094/flash.c index fa51c9037..0958e73d6 100644 --- a/board/etx094/flash.c +++ b/board/etx094/flash.c @@ -24,68 +24,53 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); +static ulong flash_get_size(vu_long *addr, flash_info_t *info); +static int write_word(flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets(ulong base, flash_info_t *info); /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; - } /* Static FLASH Bank configuration here - FIXME XXX */ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0<<20); } - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - /* Remap FLASH according to real size */ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); #ifdef CONFIG_FLASH_16BIT - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | + BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ #else - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | + BR_MS_GPCM | BR_V; #endif /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, + &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ @@ -95,56 +80,26 @@ unsigned long flash_init (void) &flash_info[0]); #endif - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); -#ifdef CONFIG_FLASH_16BIT - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V | BR_PS_16; -#else - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; -#endif - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } + memctl->memc_br1 = 0; /* invalidate bank 1 */ flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } /*----------------------------------------------------------------------- */ -static void flash_get_offsets (ulong base, flash_info_t *info) +static void flash_get_offsets(ulong base, flash_info_t *info) { int i; - if (info->flash_id == FLASH_UNKNOWN) { + if (info->flash_id == FLASH_UNKNOWN) return; - } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) { + for (i = 0; i < info->sector_count; i++) info->start[i] = base + (i * 0x00002000); - } + return; } @@ -156,106 +111,119 @@ static void flash_get_offsets (ulong base, flash_info_t *info) info->start[1] = base + 0x00004000; info->start[2] = base + 0x00006000; info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { + for (i = 4; i < info->sector_count; i++) info->start[i] = base + (i * 0x00010000) - 0x00030000; #else info->start[0] = base + 0x00000000; info->start[1] = base + 0x00008000; info->start[2] = base + 0x0000C000; info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { + for (i = 4; i < info->sector_count; i++) info->start[i] = base + (i * 0x00020000) - 0x00060000; #endif - } } else { /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00008000; info->start[i--] = base + info->size - 0x0000C000; info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { + for (; i >= 0; i--) info->start[i] = base + i * 0x00020000; - } } - } /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void flash_print_info(flash_info_t *info) { int i; if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); + printf("missing or unknown FLASH type\n"); return; } switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - default: printf ("Unknown Vendor "); break; + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + default: + printf("Unknown Vendor "); + break; } switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST200A: printf ("39xF200A (2M = 128K x 16)\n"); - break; - case FLASH_SST400A: printf ("39xF400A (4M = 256K x 16)\n"); - break; - case FLASH_SST800A: printf ("39xF800A (8M = 512K x 16)\n"); - break; - case FLASH_STM800AB: printf ("M29W800AB (8M = 512K x 16)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST200A: + printf("39xF200A (2M = 128K x 16)\n"); + break; + case FLASH_SST400A: + printf("39xF400A (4M = 256K x 16)\n"); + break; + case FLASH_SST800A: + printf("39xF800A (8M = 512K x 16)\n"); + break; + case FLASH_STM800AB: + printf("M29W800AB (8M = 512K x 16)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } - printf (" Size: %ld MB in %d Sectors\n", + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", + printf("\n "); + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " " ); } - printf ("\n"); + printf("\n"); return; } -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - /* * The following code cannot be run from FLASH! */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) +static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; ulong value; @@ -263,7 +231,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ #ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; + vu_short *s_addr = (vu_short *)addr; s_addr[0x5555] = 0x00AA; s_addr[0x2AAA] = 0x0055; s_addr[0x5555] = 0x0090; @@ -293,7 +261,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; info->size = 0; - return (0); /* no or unknown flash */ + return 0; /* no or unknown flash */ } #ifdef CONFIG_FLASH_16BIT value = s_addr[1]; @@ -349,32 +317,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) #endif break; -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif case SST_ID_xF200A: info->flash_id += FLASH_SST200A; - info->sector_count = 64; /* 39xF200A ID ( 2M = 128K x 16 ) */ + info->sector_count = 64; /* 39xF200A (2M = 128K x 16) */ info->size = 0x00080000; break; case SST_ID_xF400A: info->flash_id += FLASH_SST400A; - info->sector_count = 128; /* 39xF400A ID ( 4M = 256K x 16 ) */ + info->sector_count = 128; /* 39xF400A (4M = 256K x 16) */ info->size = 0x00100000; break; case SST_ID_xF800A: info->flash_id += FLASH_SST800A; - info->sector_count = 256; /* 39xF800A ID ( 8M = 512K x 16 ) */ + info->sector_count = 256; /* 39xF800A (8M = 512K x 16) */ info->size = 0x00200000; break; /* => 2 MB */ case STM_ID_x800AB: @@ -384,55 +339,55 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) break; /* => 2 MB */ default: info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + return 0; /* => no or unknown flash */ } if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", + printf("** ERROR: sector count %d > max (%d) **\n", info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - for (i = 0; i < info->sector_count; i++) { + for (i = 0; i < info->sector_count; i++) info->start[i] = base + (i * 0x00002000); - } } else { /* AMD and Fujitsu types */ /* set up sector start address table */ if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ + /* set sector offsets for bottom boot block type */ #ifdef CONFIG_FLASH_16BIT info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; info->start[2] = base + 0x00006000; info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; + for (i = 4; i < info->sector_count; i++) + info->start[i] = base + + (i * 0x00010000) - 0x00030000; #else info->start[0] = base + 0x00000000; info->start[1] = base + 0x00008000; info->start[2] = base + 0x0000C000; info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; + for (i = 4; i < info->sector_count; i++) + info->start[i] = base + + (i * 0x00020000) - 0x00060000; #endif - } } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00008000; info->start[i--] = base + info->size - 0x0000C000; info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { + for (; i >= 0; i--) info->start[i] = base + i * 0x00020000; - } } /* check for protected sectors */ for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address: + /* + * read sector protection at sector address: * (A7 .. A0) = 0x02 * D0 = 1 if protected */ @@ -459,28 +414,23 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) #endif } - return (info->size); + return info->size; } - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - vu_long *addr = (vu_long*)(info->start[0]); + vu_long *addr = (vu_long *)(info->start[0]); int flag, prot, sect; ulong start, now, last; #ifdef CONFIG_FLASH_16BIT - vu_short *s_addr = (vu_short*)addr; + vu_short *s_addr = (vu_short *)addr; #endif if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); return 1; } /*#ifndef CONFIG_FLASH_16BIT @@ -493,30 +443,29 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } #endif*/ prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } - start = get_timer (0); + start = get_timer(0); last = start; /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ #ifdef CONFIG_FLASH_16BIT - vu_short *s_sect_addr = (vu_short*)(info->start[sect]); + vu_short *s_sect_addr = (vu_short *)(info->start[sect]); #else - vu_long *sect_addr = (vu_long*)(info->start[sect]); + vu_long *sect_addr = (vu_long *)(info->start[sect]); #endif - /* Disable interrupts which might cause a timeout here */ + /* Disable interrupts which might cause a timeout */ flag = disable_interrupts(); #ifdef CONFIG_FLASH_16BIT @@ -541,20 +490,21 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); #ifdef CONFIG_FLASH_16BIT while ((s_sect_addr[0] & 0x0080) != 0x0080) { #else while ((sect_addr[0] & 0x00800080) != 0x00800080) { #endif - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + now = get_timer(start); + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); + /* show every second that we're waiting */ + if ((now - last) > 1000) { + putc('.'); last = now; } } @@ -569,7 +519,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[0] = 0x00F000F0; /* reset bank */ #endif - printf (" done\n"); + printf(" done\n"); return 0; } @@ -581,37 +531,39 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) * 4 - Flash not identified */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; - if (info->flash_id == FLASH_UNKNOWN) { + if (info->flash_id == FLASH_UNKNOWN) return 4; - } wp = (addr & ~3); /* get lower word aligned address */ /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i = 0, cp = wp; i < l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { + for (; cnt == 0 && i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; } @@ -620,33 +572,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + + rc = write_word(info, wp, data); + if (rc != 0) + return rc; + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { + for (; i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); + return write_word(info, wp, data); } /*----------------------------------------------------------------------- @@ -655,22 +606,21 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - vu_long *addr = (vu_long*)(info->start[0]); + vu_long *addr = (vu_long *)(info->start[0]); #ifdef CONFIG_FLASH_16BIT vu_short high_data; vu_short low_data; - vu_short *s_addr = (vu_short*)addr; + vu_short *s_addr = (vu_short *)addr; #endif ulong start; int flag; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } + if ((*((vu_long *)dest) & data) != data) + return 2; #ifdef CONFIG_FLASH_16BIT /* Write the 16 higher-bits */ @@ -685,20 +635,17 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) *((vu_short *)dest) = high_data; - /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); /* data polling for D7 */ - start = get_timer (0); + start = get_timer(0); while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - /* Write the 16 lower-bits */ #endif @@ -725,7 +672,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) enable_interrupts(); /* data polling for D7 */ - start = get_timer (0); + start = get_timer(0); #ifdef CONFIG_FLASH_16BIT while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) { @@ -733,12 +680,8 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { #endif - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - return (0); + return 0; } - -/*----------------------------------------------------------------------- - */ diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index 1492ffce9..c02a9cdfd 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -127,31 +127,32 @@ static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) #endif if(icr&0x10000000) { +#ifdef DEBUG unsigned int psr; + psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); -#ifdef DEBUG printf("PHY state change:\n" " GT:%s:%s:%s:%s\n", - psr&1?"100":" 10", - psr&8?" Link":"nLink", - psr&2?"FD":"HD", - psr&4?" FC":"nFC"); + psr & 1 ? "100" : " 10", + psr & 8 ? " Link" : "nLink", + psr & 2 ? "FD" : "HD", + psr & 4 ? " FC" : "nFC"); #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ { - unsigned short mii_11; - mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11); - - printf(" mii:%s:%s:%s:%s %s:%s %s\n", - mii_11&(1<<14)?"100":" 10", - mii_11&(1<<10)?" Link":"nLink", - mii_11&(1<<9)?"FD":"HD", - mii_11&(1<<4)?" FC":"nFC", - - mii_11&(1<<7)?"ANc":"ANnc", - mii_11&(1<<8)?"AN":"Manual", - "" - ); + unsigned short mii_11; + mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11); + + printf(" mii:%s:%s:%s:%s %s:%s %s\n", + mii_11 & (1 << 14) ? "100" : " 10", + mii_11 & (1 << 10) ? " Link" : "nLink", + mii_11 & (1 << 9) ? "FD" : "HD", + mii_11 & (1 << 4) ? " FC" : "nFC", + + mii_11 & (1 << 7) ? "ANc" : "ANnc", + mii_11 & (1 << 8) ? "AN" : "Manual", + "" + ); } #endif /* CONFIG_INTEL_LXT97X */ #endif /* DEBUG */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c index 80756a5cd..393320ac1 100644 --- a/board/evb64260/evb64260.c +++ b/board/evb64260/evb64260.c @@ -32,6 +32,7 @@ #include <galileo/gt64260R.h> #include <net.h> #include <netdev.h> +#include <linux/compiler.h> #include <asm/io.h> #include "eth.h" @@ -360,7 +361,7 @@ debug_led(int led, int mode) { #if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4) volatile int *addr = NULL; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c index 88d0dac46..3eae3d903 100644 --- a/board/evb64260/i2c.c +++ b/board/evb64260/i2c.c @@ -20,27 +20,23 @@ static void i2c_init(int speed, int slaveaddr) { unsigned int n, m, freq, margin, power; - unsigned int actualFreq, actualN=0, actualM=0; + unsigned int actualN = 0, actualM = 0; unsigned int control, status; unsigned int minMargin = 0xffffffff; unsigned int tclk = 125000000; DP(puts("i2c_init\n")); - for(n = 0 ; n < 8 ; n++) - { - for(m = 0 ; m < 16 ; m++) - { + for (n = 0 ; n < 8 ; n++) { + for (m = 0 ; m < 16 ; m++) { power = 2<<n; /* power = 2^(n+1) */ freq = tclk/(10*(m+1)*power); if (speed > freq) margin = speed - freq; else margin = freq - speed; - if(margin < minMargin) - { + if (margin < minMargin) { minMargin = margin; - actualFreq = freq; actualN = n; actualM = m; } @@ -91,13 +87,13 @@ i2c_start(void) udelay(I2C_DELAY); if (count > 20) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; } - return (0); + return 0; } static uchar @@ -110,9 +106,8 @@ i2c_select_device(uchar dev_addr, uchar read, int ten_bit) /* Output slave address */ - if (ten_bit) { + if (ten_bit) bits = 10; - } data = (dev_addr << 1); /* set the read bit */ @@ -129,7 +124,7 @@ i2c_select_device(uchar dev_addr, uchar read, int ten_bit) udelay(I2C_DELAY); if (count > 20) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return(status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; @@ -137,14 +132,14 @@ i2c_select_device(uchar dev_addr, uchar read, int ten_bit) if (bits == 10) { printf("10 bit I2C addressing not yet implemented\n"); - return (0xff); + return 0xff; } - return (0); + return 0; } static uchar -i2c_get_data(uchar* return_data, int len) { +i2c_get_data(uchar *return_data, int len) { unsigned int data, status = 0; int count = 0; @@ -163,7 +158,7 @@ i2c_get_data(uchar* return_data, int len) { count++; while ((status & 0xff) != 0x50) { udelay(I2C_DELAY); - if(count > 2) { + if (count > 2) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ return 0; } @@ -178,16 +173,16 @@ i2c_get_data(uchar* return_data, int len) { RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3); while ((status & 0xff) != 0x58) { udelay(I2C_DELAY); - if(count > 200) { + if (count > 200) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; } GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */ - return (0); + return 0; } static uchar @@ -213,9 +208,9 @@ i2c_write_data(unsigned int data, int len) count++; while ((status & 0xff) != 0x28) { udelay(I2C_DELAY); - if(count > 20) { + if (count > 20) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; @@ -227,7 +222,7 @@ i2c_write_data(unsigned int data, int len) udelay(I2C_DELAY * 10); - return (0); + return 0; } static uchar @@ -254,11 +249,11 @@ i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit) return status; } - return (0); + return 0; } uchar -i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, +i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data, int ten_bit) { uchar status = 0; @@ -266,7 +261,7 @@ i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, DP(puts("i2c_read\n")); - i2c_init(i2cFreq,0); + i2c_init(i2cFreq, 0); status = i2c_start(); @@ -285,7 +280,7 @@ i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, return status; } - i2c_init(i2cFreq,0); + i2c_init(i2cFreq, 0); status = i2c_start(); if (status) { diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c index e2f07699c..6f725f67f 100644 --- a/board/evb64260/sdram_init.c +++ b/board/evb64260/sdram_init.c @@ -29,6 +29,7 @@ #include <galileo/pci.h> #include <galileo/gt64260R.h> #include <net.h> +#include <linux/compiler.h> #include "eth.h" #include "mpsc.h" @@ -330,7 +331,8 @@ static int check_dimm (uchar slot, sdram_info_t * info) static int setup_sdram_common (sdram_info_t info[2]) { ulong tmp; - int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2; + int tpar = 2, tras_clocks = 5, registered = 1; + __maybe_unused int ecc = 2; if (!info[0].banks && !info[1].banks) return 0; @@ -407,8 +409,9 @@ static int setup_sdram_common (sdram_info_t info[2]) /* sets up the GT properly with information passed in */ static int setup_sdram (sdram_info_t * info) { - ulong tmp, check; + ulong tmp; ulong *addr = 0; + __maybe_unused ulong check; int i; /* sanity checking */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c index 8e381024b..621c64cd8 100644 --- a/board/evb64260/zuma_pbb_mbox.c +++ b/board/evb64260/zuma_pbb_mbox.c @@ -12,57 +12,62 @@ struct _zuma_mbox_dev zuma_mbox_dev; static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data) { - unsigned int status, count = 0, i; - - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - - while((status & OUT_PENDING) && count < 1000) { - count++; - for(i=0;i<1000;i++); - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - } - if(count < 1000) { - /* if SET it means msg pending */ - /* printf("mbox real write %08x\n",data); */ - dev->sip->mbox_out = cpu_to_le32(data); - return 4; - } - - printf("mbox tx timeout\n"); - return 0; + unsigned int status, count = 0, i; + + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + + while ((status & OUT_PENDING) && count < 1000) { + count++; + for (i = 0; i < 1000; i++) + ; + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + } + if (count < 1000) { + /* if SET it means msg pending */ + /* printf("mbox real write %08x\n",data); */ + dev->sip->mbox_out = cpu_to_le32(data); + return 4; + } + + printf("mbox tx timeout\n"); + return 0; } static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data) { - unsigned int status, count = 0, i; - - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - - while(!(status & IN_VALID) && count < 1000) { - count++; - for(i=0;i<1000;i++); - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - } - if(count < 1000) { - /* if SET it means msg pending */ - *data=le32_to_cpu(dev->sip->mbox_in); - /*printf("mbox real read %08x\n", *data); */ - return 4; - } - printf("mbox rx timeout\n"); - return 0; + unsigned int status, count = 0, i; + + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + + while (!(status & IN_VALID) && count < 1000) { + count++; + for (i = 0; i < 1000; i++) + ; + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + } + if (count < 1000) { + /* if SET it means msg pending */ + *data = le32_to_cpu(dev->sip->mbox_in); + /*printf("mbox real read %08x\n", *data); */ + return 4; + } + printf("mbox rx timeout\n"); + return 0; } static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) { - int ret; - ret=zuma_mbox_write(&zuma_mbox_dev,out); - /*printf("write 0x%08x (%d bytes)\n", out, ret); */ - if(ret!=4) return -1; - ret=zuma_mbox_read(&zuma_mbox_dev,in); - /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ - if(ret!=4) return -1; - return 0; + int ret; + + ret = zuma_mbox_write(&zuma_mbox_dev, out); + /*printf("write 0x%08x (%d bytes)\n", out, ret); */ + if (ret != 4) + return -1; + ret = zuma_mbox_read(&zuma_mbox_dev, in); + /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ + if (ret != 4) + return -1; + return 0; } @@ -70,81 +75,93 @@ static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) static int zuma_mbox_do_all_mailbox(void) { - unsigned int data_in; - unsigned short sdata_in; + unsigned int data_in; + unsigned short sdata_in; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); - memcpy(zuma_acc_mac+2,&data_in,4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); - sdata_in=data_in&0xffff; - memcpy(zuma_acc_mac,&sdata_in,2); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); + memcpy(zuma_acc_mac + 2, &data_in, 4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); + sdata_in = data_in & 0xffff; + memcpy(zuma_acc_mac, &sdata_in, 2); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); - zuma_ip=data_in; + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); + zuma_ip = data_in; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); - zuma_slot_bac=data_in>>3; + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); + zuma_slot_bac = data_in >> 3; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); - zuma_console_baud = data_in & 0xffff; - zuma_debug_baud = data_in >> 16; + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); + zuma_console_baud = data_in & 0xffff; + zuma_debug_baud = data_in >> 16; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); - memcpy(zuma_prv_mac+2,&data_in,4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); - sdata_in=data_in&0xffff; - memcpy(zuma_prv_mac,&sdata_in,2); + RET_IF_FAILED(zuma_mbox_do_one_mailbox + (ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); + memcpy(zuma_prv_mac + 2, &data_in, 4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox + (ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); + sdata_in = data_in & 0xffff; + memcpy(zuma_prv_mac, &sdata_in, 2); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); - return 0; + return 0; } -static void -zuma_mbox_dump(void) +static void zuma_mbox_dump(void) { - printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2)); - printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2)); - printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3); - printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud); + unsigned short s; + unsigned int i; + + memcpy(&s, &zuma_acc_mac, sizeof(s)); + memcpy(&i, &zuma_acc_mac[2], sizeof(i)); + printf("ACC MAC=%04x%08x\n", s, i); + + memcpy(&s, &zuma_prv_mac, sizeof(s)); + memcpy(&s, &zuma_prv_mac[2], sizeof(i)); + printf("PRV MAC=%04x%08x\n", s, i); + + printf("slot:bac=%d:%d\n", + (zuma_slot_bac >> 2) & 0xf, + zuma_slot_bac & 0x3); + + printf("BAUD1=%d BAUD2=%d\n", + zuma_console_baud, + zuma_debug_baud); } -static void -zuma_mbox_setenv(void) +static void zuma_mbox_setenv(void) { - char *data, buf[32]; - unsigned char save = 0; - - data = getenv("baudrate"); - - if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { - sprintf(buf, "%6d", zuma_console_baud); - setenv("baudrate", buf); - save=1; - printf("baudrate doesn't match from mbox\n"); - } - - ip_to_string(zuma_ip, buf); - setenv("ipaddr", buf); - - sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x", - zuma_prv_mac[0], - zuma_prv_mac[1], - zuma_prv_mac[2], - zuma_prv_mac[3], - zuma_prv_mac[4], - zuma_prv_mac[5]); - setenv("ethaddr", buf); - - sprintf(buf,"%02x",zuma_slot_bac); - setenv("bacslot", buf); - - if(save) - saveenv(); + char *data, buf[32]; + unsigned char save = 0; + + data = getenv("baudrate"); + + if (!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { + sprintf(buf, "%6d", zuma_console_baud); + setenv("baudrate", buf); + save = 1; + printf("baudrate doesn't match from mbox\n"); + } + + ip_to_string(zuma_ip, buf); + setenv("ipaddr", buf); + + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", + zuma_prv_mac[0], + zuma_prv_mac[1], + zuma_prv_mac[2], + zuma_prv_mac[3], zuma_prv_mac[4], zuma_prv_mac[5]); + setenv("ethaddr", buf); + + sprintf(buf, "%02x", zuma_slot_bac); + setenv("bacslot", buf); + + if (save) + saveenv(); } /** @@ -153,37 +170,39 @@ zuma_mbox_setenv(void) int zuma_mbox_init(void) { - unsigned int iobase; - memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); + unsigned int iobase; + + memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); - zuma_mbox_dev.dev = pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); + zuma_mbox_dev.dev = + pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - if(zuma_mbox_dev.dev == -1) { - printf("no zuma pbb\n"); - return -1; - } + if (zuma_mbox_dev.dev == -1) { + printf("no zuma pbb\n"); + return -1; + } - pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); + pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); - iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase &= PCI_BASE_ADDRESS_MEM_MASK; - zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *)iobase; + zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) iobase; - zuma_mbox_dev.sip->int_mask.word=0; + zuma_mbox_dev.sip->int_mask.word = 0; - printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, - zuma_mbox_dev.sip->version.pci_bits.rev_major, - zuma_mbox_dev.sip->version.pci_bits.rev_minor, - zuma_mbox_dev.sip->timestamp); + printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, + zuma_mbox_dev.sip->version.pci_bits.rev_major, + zuma_mbox_dev.sip->version.pci_bits.rev_minor, + zuma_mbox_dev.sip->timestamp); - if (zuma_mbox_do_all_mailbox() == -1) { - printf("mailbox failed.. no ACC?\n"); - return -1; - } + if (zuma_mbox_do_all_mailbox() == -1) { + printf("mailbox failed.. no ACC?\n"); + return -1; + } - zuma_mbox_dump(); + zuma_mbox_dump(); - zuma_mbox_setenv(); + zuma_mbox_setenv(); - return 0; + return 0; } diff --git a/board/fads/fads.c b/board/fads/fads.c index 9f7faaf47..317d27960 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -603,15 +603,17 @@ static int initsdram(uint base, uint *noMbytes) phys_size_t initdram (int board_type) { uint sdramsz = 0; /* size of sdram in Mbytes */ - uint base = 0; /* base of dram in bytes */ uint m = 0; /* size of dram in Mbytes */ #ifndef CONFIG_MPC885ADS + uint base = 0; /* base of dram in bytes */ uint k, s; #endif #ifdef CONFIG_FADS if (!initsdram (0x00000000, &sdramsz)) { +#ifndef CONFIG_MPC885ADS base = sdramsz << 20; +#endif printf ("(%u MB SDRAM) ", sdramsz); } #endif diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 6f221aff2..8a09f99cc 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -28,13 +28,12 @@ #if defined(CONFIG_OF_BOARD_SETUP) static void cds_pci_fixup(void *blob) { - int node, tmp[2]; + int node; const char *path; int len, slot, i; u32 *map = NULL; node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { path = fdt_getprop(blob, node, "pci0", NULL); if (path) { diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 89d8810f7..6acbc361a 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -31,12 +31,81 @@ #include "pixis.h" #endif +/* define for SYS CLK or CLK1Frequency */ +#define TTL 1 +#define CLK2 0 +#define CRYSTAL 0 +#define MAX_VDW (511 + 8) +#define MAX_RDW (127 + 2) +#define MIN_VDW (4 + 8) +#define MIN_RDW (1 + 2) +#define NUM_OD_SETTING 8 +/* + * These defines cover the industrial temperature range part, + * for commercial, change below to 400000 and 55000, respectively + */ +#define MAX_VCO 360000 +#define MIN_VCO 60000 + /* decode S[0-2] to Output Divider (OD) */ static u8 ics307_s_to_od[] = { 10, 2, 8, 4, 5, 7, 3, 6 }; /* + * Find one solution to generate required frequency for SYSCLK + * out_freq: KHz, required frequency to the SYSCLK + * the result will be retuned with component RDW, VDW, OD, TTL, + * CLK2 and crystal + */ +unsigned long ics307_sysclk_calculator(unsigned long out_freq) +{ + const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; + unsigned long tmp_out, diff, result = 0; + int found = 0; + + for (odp = 0; odp < NUM_OD_SETTING; odp++) { + od = ics307_s_to_od[odp]; + if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) + continue; + for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { + /* Calculate the VDW */ + vdw = out_freq * 1000 * od * rdw / (input_freq * 2); + if (vdw > MAX_VDW) + vdw = MAX_VDW; + if (vdw < MIN_VDW) + continue; + /* Calculate the temp out frequency */ + tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); + diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out); + /* + * calculate the percent, the precision is 1/1000 + * If greater than 1/1000, continue + * otherwise, we think the solution is we required + */ + if (diff * 1000 / out_freq > 1) + continue; + else { + s_vdw = vdw; + s_rdw = rdw; + s_odp = odp; + found = 1; + break; + } + } + } + + if (found) + result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | + CLK2 << 19 | TTL << 21 | CRYSTAL << 22; + + debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, + ics307_s_to_od[s_odp]); + return result; +} + +/* * Calculate frequency being generated by ICS307-02 clock chip based upon * the control bytes being programmed into it. */ diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h index db3dbc41f..37579124b 100644 --- a/board/freescale/common/ics307_clk.h +++ b/board/freescale/common/ics307_clk.h @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,8 +23,10 @@ #define __ICS_CLK_H_ 1 #ifndef __ASSEMBLY__ + extern unsigned long get_board_sys_clk(void); extern unsigned long get_board_ddr_clk(void); +extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); #endif #endif /* __ICS_CLK_H_ */ diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 765f0359b..276ae3c5c 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -156,9 +156,29 @@ static void pixis_dump_regs(void) } #endif +void pixis_sysclk_set(unsigned long sysclk) +{ + unsigned long freq_word; + u8 sclk0, sclk1, sclk2; + + freq_word = ics307_sysclk_calculator(sysclk); + sclk2 = freq_word & 0xff; + sclk1 = (freq_word >> 8) & 0xff; + sclk0 = (freq_word >> 16) & 0xff; + + /* set SYSCLK enable bit */ + PIXIS_WRITE(vcfgen0, 0x01); + + /* SYSCLK to required frequency */ + PIXIS_WRITE(sclk[0], sclk0); + PIXIS_WRITE(sclk[1], sclk1); + PIXIS_WRITE(sclk[2], sclk2); +} + int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int i; + unsigned long sysclk; char *p_altbank = NULL; #ifdef DEBUG char *p_dump = NULL; @@ -182,6 +202,12 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) continue; } #endif + if (strcmp(argv[i], "sysclk") == 0) { + sysclk = simple_strtoul(argv[i + 1], NULL, 0); + i += 1; + pixis_sysclk_set(sysclk); + continue; + } unknown_param = argv[i]; } @@ -219,4 +245,5 @@ U_BOOT_CMD( #ifdef DEBUG "pixis_reset dump - display the PIXIS registers\n" #endif + "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n" ); diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index a35b5cfe3..8d07061c3 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -380,7 +380,7 @@ static unsigned long strfractoint(char *strptr) { int i, j; int mulconst; - int intarr_len, no_dec = 0; + int no_dec = 0; unsigned long intval = 0, decval = 0; char intarr[3], decarr[3]; @@ -399,8 +399,6 @@ static unsigned long strfractoint(char *strptr) i++; } - /* Assign length of integer part to intarr_len. */ - intarr_len = i; intarr[i] = '\0'; if (no_dec) { diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a7a5e13af..962f38038 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 7ff00d146..1f00c1453 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -301,7 +301,6 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; int i; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; @@ -327,13 +326,6 @@ int board_eth_init(bd_t *bis) SLOT5, /* 17 - Bank 3:D */ }; - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index e7b22e3fc..3e9f4c346 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -32,9 +32,6 @@ SECTIONS arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*) arch/m68k/lib/libm68k.o (.text*) - . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text*) - *(.text*) } _etext = .; diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c index 2caf4aa99..5d4896818 100644 --- a/board/freescale/mpc8266ads/mpc8266ads.c +++ b/board/freescale/mpc8266ads/mpc8266ads.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001 + * (C) Copyright 2001-2011 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * Modified during 2001 by @@ -61,8 +61,8 @@ const iop_conf_t iop_conf_tab[4][32] = { - /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ @@ -95,10 +95,10 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, + }, - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ @@ -131,10 +131,10 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, + }, - /* Port C */ - { /* conf ppar psor pdir podr pdat */ + /* Port C */ + { /* conf ppar psor pdir podr pdat */ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ @@ -167,10 +167,10 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, + }, - /* Port D */ - { /* conf ppar psor pdir podr pdat */ + /* Port D */ + { /* conf ppar psor pdir podr pdat */ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ @@ -203,7 +203,7 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } + } }; typedef struct bscr_ { @@ -224,317 +224,329 @@ typedef struct pci_ic_s { void reset_phy(void) { - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; + volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - /* reset the FEC port */ - bcsr->bcsr1 &= ~FETH_RST; - bcsr->bcsr1 |= FETH_RST; + /* reset the FEC port */ + bcsr->bcsr1 &= ~FETH_RST; + bcsr->bcsr1 |= FETH_RST; } -int board_early_init_f (void) +int board_early_init_f(void) { - volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; - volatile pci_ic_t *pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT; + volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; + volatile pci_ic_t *pci_ic = (pci_ic_t *)CONFIG_SYS_PCI_INT; - bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; + bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; - /* mask all PCI interrupts */ - pci_ic->pci_int_mask |= 0xfff00000; + /* mask all PCI interrupts */ + pci_ic->pci_int_mask |= 0xfff00000; - return 0; + return 0; } int checkboard(void) { - puts ("Board: Motorola MPC8266ADS\n"); - return 0; + puts("Board: Motorola MPC8266ADS\n"); + return 0; } phys_size_t initdram(int board_type) { /* Autoinit part stolen from board/sacsng/sacsng.c */ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0xff; - volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - - uint psrt = 0x21; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char spd_size; - u_char data; - u_char cksum; - int j; - - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = rows = banks = cols = caslatency = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - spd_size = data; - cksum = data; - for(j = 1; j < 64; j++) - { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0xff; + volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); + uint psdmr = CONFIG_SYS_PSDMR; + int i; + + uint psrt = 0x21; /* for no SPD */ + uint chipselects = 1; /* for no SPD */ + uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ + uint data_width; + uint rows; + uint banks; + uint cols; + uint caslatency; + uint width; + uint rowst; + uint sdam; + uint bsma; + uint sda10; + u_char data; + u_char cksum; + int j; + + /* + * Keep the compiler from complaining about + * potentially uninitialized vars + */ + data_width = rows = banks = cols = caslatency = 0; + + /* + * Read the SDRAM SPD EEPROM via I2C. + */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); + cksum = data; + for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ + /* note: the I2C address autoincrements when alen == 0 */ i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - /*printf("addr %d = 0x%02x\n", j, data);*/ - if(j == 5) chipselects = data & 0x0F; - else if(j == 6) data_width = data; - else if(j == 7) data_width |= data << 8; - else if(j == 3) rows = data & 0x0F; - else if(j == 4) cols = data & 0x0F; - else if(j == 12) - { + /*printf("addr %d = 0x%02x\n", j, data); */ + if (j == 5) + chipselects = data & 0x0F; + else if (j == 6) + data_width = data; + else if (j == 7) + data_width |= data << 8; + else if (j == 3) + rows = data & 0x0F; + else if (j == 4) + cols = data & 0x0F; + else if (j == 12) { /* - * Refresh rate: this assumes the prescaler is set to - * approximately 0.39uSec per tick and the target refresh period - * is about 85% of maximum. + * Refresh rate: this assumes the prescaler is set to + * approximately 0.39uSec per tick and the target + * refresh period is about 85% of maximum. */ - switch(data & 0x7F) - { - default: - case 0: psrt = 0x21; /* 15.625uS */ break; - case 1: psrt = 0x07; /* 3.9uS */ break; - case 2: psrt = 0x0F; /* 7.8uS */ break; - case 3: psrt = 0x43; /* 31.3uS */ break; - case 4: psrt = 0x87; /* 62.5uS */ break; - case 5: psrt = 0xFF; /* 125uS */ break; + switch (data & 0x7F) { + default: + case 0: + psrt = 0x21; /* 15.625uS */ + break; + case 1: + psrt = 0x07; /* 3.9uS */ + break; + case 2: + psrt = 0x0F; /* 7.8uS */ + break; + case 3: + psrt = 0x43; /* 31.3uS */ + break; + case 4: + psrt = 0x87; /* 62.5uS */ + break; + case 5: + psrt = 0xFF; /* 125uS */ + break; } - } - else if(j == 17) banks = data; - else if(j == 18) - { - caslatency = 3; /* default CL */ -# if(PESSIMISTIC_SDRAM) - if((data & 0x04) != 0) caslatency = 3; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x01) != 0) caslatency = 1; -# else - if((data & 0x01) != 0) caslatency = 1; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x04) != 0) caslatency = 3; -# endif - else - { - printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", + } else if (j == 17) + banks = data; + else if (j == 18) { + caslatency = 3; /* default CL */ +#if (PESSIMISTIC_SDRAM) + if ((data & 0x04) != 0) + caslatency = 3; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x01) != 0) + caslatency = 1; +#else + if ((data & 0x01) != 0) + caslatency = 1; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x04) != 0) + caslatency = 3; +#endif + else { + printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data); } - } - else if(j == 63) - { - if(data != cksum) - { - printf ("WARNING: Configuration data checksum failure:" + } else if (j == 63) { + if (data != cksum) { + printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", - data, cksum); + data, cksum); } } cksum += data; - } + } - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if(caslatency < 2) { + /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ + if (caslatency < 2) { printf("CL was %d, forcing to 2\n", caslatency); caslatency = 2; - } - if(rows > 14) { - printf("This doesn't look good, rows = %d, should be <= 14\n", rows); + } + if (rows > 14) { + printf("This doesn't look good, rows = %d, should be <= 14\n", + rows); rows = 14; - } - if(cols > 11) { - printf("This doesn't look good, columns = %d, should be <= 11\n", cols); + } + if (cols > 11) { + printf("This doesn't look good, columns = %d, should be <= 11\n", + cols); cols = 11; - } + } - if((data_width != 64) && (data_width != 72)) - { + if ((data_width != 64) && (data_width != 72)) { printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) banks = 1; - else if(banks == 4) banks = 2; - else if(banks == 8) banks = 3; - - - sdram_size = 1 << (rows + cols + banks + width); - /* hack for high density memory (512MB per CS) */ - /* !!!!! Will ONLY work with Page Based Interleave !!!!! - ( PSDMR[PBI] = 1 ) - */ - /* mamory actually has 11 column addresses, but the memory controller - doesn't really care. - the calculations that follow will however move the rows so that - they are muxed one bit off if you use 11 bit columns. - The solution is to tell the memory controller the correct size of the memory - but change the number of columns to 10 afterwards. - The 11th column addre will still be mucxed correctly onto the bus. - - Also be aware that the MPC8266ADS board Rev B has not connected - Row address 13 to anything. - - The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) - */ - if (cols > 10) - cols = 10; - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; + } + width = 3; /* 2^3 = 8 bytes = 64 bits wide */ + /* + * Convert banks into log2(banks) + */ + if (banks == 2) + banks = 1; + else if (banks == 4) + banks = 2; + else if (banks == 8) + banks = 3; + + + sdram_size = 1 << (rows + cols + banks + width); + /* hack for high density memory (512MB per CS) */ + /* !!!!! Will ONLY work with Page Based Interleave !!!!! + ( PSDMR[PBI] = 1 ) + */ + /* + * memory actually has 11 column addresses, but the memory + * controller doesn't really care. + * + * the calculations that follow will however move the rows so + * that they are muxed one bit off if you use 11 bit columns. + * + * The solution is to tell the memory controller the correct + * size of the memory but change the number of columns to 10 + * afterwards. + * + * The 11th column addre will still be mucxed correctly onto + * the bus. + * + * Also be aware that the MPC8266ADS board Rev B has not + * connected Row address 13 to anything. + * + * The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) + */ + if (cols > 10) + cols = 10; + +#if (CONFIG_PBI == 0) /* bank-based interleaving */ + rowst = ((32 - 6) - (rows + cols + width)) * 2; #else - rowst = 32 - (rows + banks + cols + width); + rowst = 32 - (rows + banks + cols + width); #endif - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks-1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - - /*printf("memctl->memc_or2 = 0x%08x\n", or);*/ - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; + or = ~(sdram_size - 1) | /* SDAM address mask */ + ((banks - 1) << 13) | /* banks per device */ + (rowst << 9) | /* rowst */ + ((rows - 9) << 6); /* numr */ + + + /*printf("memctl->memc_or2 = 0x%08x\n", or); */ + + /* + * SDAM specifies the number of columns that are multiplexed + * (reference AN2165/D), defined to be (columns - 6) for page + * interleave, (columns - 8) for bank interleave. + * + * BSMA is 14 - max(rows, cols). The bank select lines come + * into play above the highest "address" line going into the + * the SDRAM. + */ +#if (CONFIG_PBI == 0) /* bank-based interleaving */ + sdam = cols - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam + 2; #else - sdam = cols + banks - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; + sdam = cols + banks - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam; #endif -#if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_16_CLK |\ - PSDMR_PRETOACT_8W |\ - PSDMR_ACTTORW_8W |\ - PSDMR_WRC_4C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); +#if (PESSIMISTIC_SDRAM) + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | + PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | + PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #else - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX |\ - BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | + PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_WRC_1C | /* 1 clock + 7nSec */ + EAMUX | BUFCMD) | caslatency | + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #endif - /*printf("psdmr = 0x%08x\n", psdmr);*/ - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_or2 = or; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) + /*printf("psdmr = 0x%08x\n", psdmr); */ + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * Quote from Micron MT48LC8M16A2 data sheet: + * + * "...the SDRAM requires a 100uS delay prior to issuing any + * command other than a COMMAND INHIBIT or NOP. Starting at some + * point during this 100uS period and continuing at least through + * the end of this period, COMMAND INHIBIT or NOP commands should + * be applied." + * + * "Once the 100uS delay has been satisfied with at least one COMMAND + * INHIBIT or NOP command having been applied, a /PRECHARGE command/ + * should be applied. All banks must then be precharged, thereby + * placing the device in the all banks idle state." + * + * "Once in the idle state, /two/ AUTO REFRESH cycles must be + * performed. After the AUTO REFRESH cycles are complete, the + * SDRAM is ready for mode register programming." + * + * (/emphasis/ mine, gvb) + * + * The way I interpret this, Micron start up sequence is: + * 1. Issue a PRECHARGE-BANK command (initial precharge) + * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") + * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands + * 4. Issue a MODE-SET command to initialize the mode register + * + * -------- + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set + * when we get here. The SDRAM can be accessed at the address + * CONFIG_SYS_SDRAM_BASE. + */ + + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = psrt; + + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; + memctl->memc_or2 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if(chipselects > 1) - { - ramaddr += sdram_size; + /* + * Do it a second time for the second set of chips if the DIMM has + * two chip selects (double sided). + */ + if (chipselects > 1) { + ramaddr += sdram_size; memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; memctl->memc_or3 = or; @@ -551,28 +563,28 @@ phys_size_t initdram(int board_type) memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; - } + } /* print info */ printf("SDRAM configuration read from SPD\n"); printf("\tSize per side = %dMB\n", sdram_size >> 20); - printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width); + printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", + chipselects, 1 << (banks), cols, rows, data_width); printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency); -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - printf(", Using Bank Based Interleave\n"); +#if (CONFIG_PBI == 0) /* bank-based interleaving */ + printf(", Using Bank Based Interleave\n"); #else - printf(", Using Page Based Interleave\n"); + printf(", Using Page Based Interleave\n"); #endif printf("\tTotal size: "); - /* this delay only needed for original 16MB DIMM... - * Not needed for any other memory configuration */ - if ((sdram_size * chipselects) == (16 *1024 *1024)) - udelay (250000); - return (sdram_size * chipselects); - /*return (16 * 1024 * 1024);*/ -} + /* this delay only needed for original 16MB DIMM... + * Not needed for any other memory configuration */ + if ((sdram_size * chipselects) == (16 * 1024 * 1024)) + udelay(250000); + return sdram_size * chipselects; +} #ifdef CONFIG_PCI struct pci_controller hose; diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 7aede136d..a9a2ba470 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -74,8 +74,14 @@ static long fixed_sdram(void) */ __udelay(50000); - im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + CSBNDS_EA); + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; /* Currently we use only one CS, so disable the other bank. */ im->ddr.cs_config[1] = 0; diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 620540f83..ebd5274a5 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -101,18 +101,10 @@ phys_size_t initdram (int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; /* DDR size in bytes */ + u32 ddr_size_log2 = __ilog2(ddr_size); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); @@ -133,8 +125,15 @@ int fixed_sdram(void) im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; + +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[2].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 56475795b..9cc808ed7 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -43,23 +43,27 @@ int fixed_sdram(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 ddr_size; /* The size of RAM, in bytes */ - u32 ddr_size_log2 = 0; - - for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { - if (ddr_size & 1) { - return -1; - } - ddr_size_log2++; - } + /* The size of RAM, in bytes */ + u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20; + u32 ddr_size_log2 = __ilog2(ddr_size); im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - /* Only one CS0 for DDR */ - im->ddr.csbnds[0].csbnds = 0x0000000f; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + + /* Only one CS for DDR */ + im->ddr.cs_config[1] = 0; + im->ddr.cs_config[2] = 0; + im->ddr.cs_config[3] = 0; debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 51d803520..bdd129334 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006,2010 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. * Dave Liu <daveliu@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -24,6 +24,7 @@ #include <asm/mmu.h> #include <asm/io.h> #include <asm/fsl_enet.h> +#include <asm/mmu.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -139,9 +140,20 @@ int board_early_init_f(void) int board_early_init_r(void) { + gd_t *gd; #ifdef CONFIG_PQ_MDS_PIB pib_init(); #endif + /* + * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB + * So re-setup PCI MEM space used BAT5 after relocated to DDR + */ + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + } + return 0; } @@ -160,10 +172,11 @@ int board_eth_init(bd_t *bd) if (board_handle_erratum2()) { int i; - for (i = 0; i < ARRAY_SIZE(uec_info); i++) + for (i = 0; i < ARRAY_SIZE(uec_info); i++) { uec_info[i].enet_interface_type = PHY_INTERFACE_MODE_RGMII_RXID; uec_info[i].speed = SPEED_1000; + } } return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); } @@ -216,19 +229,15 @@ phys_size_t initdram(int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; + u32 ddr_size_log2 = __ilog2(ddr_size); + u32 half_ddr_size = ddr_size >> 1; + + im->sysconf.ddrlaw[0].bar = + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = - LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif @@ -246,11 +255,25 @@ int fixed_sdram(void) im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else - im->ddr.csbnds[0].csbnds = 0x00000007; - im->ddr.csbnds[1].csbnds = 0x0008000f; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; - im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG; +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[0].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.csbnds[1].csbnds = + (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >> + CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG; + + im->ddr.cs_config[2] = 0; + im->ddr.cs_config[3] = 0; im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; @@ -292,6 +315,19 @@ static int sdram_init(unsigned int base) if (rem) base = base - rem + sdram_size; + /* + * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB + * After relocated to DDR, reuse BAT5 for PCI MEM space + */ + if (base > CONFIG_MAX_MEM_MAPPED) { + unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; + unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; + + /* Setup the BAT6 for SDRAM */ + write_bat(DBAT6, batu, batl); + write_bat(IBAT6, batu, batl); + } + sdram_addr = (uint *)base; /* * Setup SDRAM Base and Option Registers diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index a8d57cddd..e5563f7c7 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -33,6 +33,9 @@ #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> +#include <tsec.h> +#include <fsl_mdio.h> +#include <netdev.h> #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -81,12 +84,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -115,7 +116,6 @@ void lbc_sdram_init(void) uint idx; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint cpu_board_rev; uint lsdmr_common; puts("LBC SDRAM: "); @@ -137,7 +137,6 @@ void lbc_sdram_init(void) /* * MPC8548 uses "new" 15-16 style addressing. */ - cpu_board_rev = get_cpu_board_revision(); lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= LSDMR_BSMA1516; @@ -287,7 +286,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); } -int last_stage_init(void) +void configure_rgmii(void) { unsigned short temp; @@ -295,29 +294,77 @@ int last_stage_init(void) /* This is needed to get the RGMII working for the 1.3+ * CDS cards */ if (get_board_version() == 0x13) { - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 18); - miiphy_read(CONFIG_TSEC1_NAME, + miiphy_read(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, &temp); temp = (temp & 0xf03f); temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, temp); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 3); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, 0x8000); } - return 0; + return; } +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif +#ifdef CONFIG_TSEC4 + /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 4); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + configure_rgmii(); + + return pci_eth_init(bis); +} +#endif #if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 225c5d8d0..6e3945edd 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -147,12 +147,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -302,6 +300,7 @@ pib_init(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio"); + i2c_set_bus_num(orig_i2c_bus); } #ifdef CONFIG_PCI diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 89557d221..d119c6517 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -303,12 +303,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 575bdb55a..6d605139f 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_NAND_SPL /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -76,6 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 0e7e0ce34..1d7b4f6d9 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -30,6 +30,8 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <watchdog.h> +#include <pmic.h> +#include <fsl_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -69,16 +71,34 @@ int board_early_init_f(void) return 0; } +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + enable_caches(); + return 0; } int board_late_init(void) { + u32 val; + struct pmic *p; + + pmic_init(); + p = get_pmic(); + + /* Enable RTC battery */ + pmic_reg_read(p, REG_POWER_CTL0, &val); + pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); + pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI); #ifdef CONFIG_HW_WATCHDOG mxc_hw_watchdog_enable(); #endif diff --git a/board/freescale/mx35pdk/mx35pdk.h b/board/freescale/mx35pdk/mx35pdk.h index 409aeb228..6aeb21835 100644 --- a/board/freescale/mx35pdk/mx35pdk.h +++ b/board/freescale/mx35pdk/mx35pdk.h @@ -59,24 +59,6 @@ #define CCM_CCMR_CONFIG 0x003F4208 #define CCM_PDR0_CONFIG 0x00801000 -#define PLL_BRM_OFFSET 31 -#define PLL_PD_OFFSET 26 -#define PLL_MFD_OFFSET 16 -#define PLL_MFI_OFFSET 10 - -#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) -#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) -#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) -#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) -#define _PLL_MFN(x) (x) -#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ - (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ - _PLL_MFN(mfn)) - -#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) -#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) -#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) - /* MEMORY SETTING */ #define ESDCTL_0x92220000 0x92220000 #define ESDCTL_0xA2220000 0xA2220000 diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 2a0dad021..37e6e4dbe 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -38,8 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -static u32 system_rev; - #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, @@ -47,11 +45,6 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = { }; #endif -u32 get_board_rev(void) -{ - return system_rev; -} - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -254,16 +247,14 @@ static void power_init(void) pmic_reg_write(p, REG_MODE_1, val); udelay(200); - gpio_direction_output(46, 0); - - /* Reset the ethernet controller over GPIO */ - writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | VVIDEOEN | VAUDIOEN | VSDEN; pmic_reg_write(p, REG_MODE_1, val); + mxc_request_iomux(MX51_PIN_EIM_A20, IOMUX_CONFIG_ALT1); + gpio_direction_output(46, 0); + udelay(500); gpio_set_value(46, 1); @@ -406,8 +397,6 @@ int board_early_init_f(void) int board_init(void) { - system_rev = get_cpu_rev(); - /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index c89da1332..be32aee14 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -37,11 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { u32 size1, size2; diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index eab9c5f7d..335661fd4 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -39,11 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 156f8b5a3..b4c7f33f9 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -38,11 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { u32 size1, size2; diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 776784f5e..87fa7fa72 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -35,11 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 get_board_rev(void) -{ - return get_cpu_rev(); -} - int dram_init(void) { u32 size1, size2; diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 03e9da194..b9e66f7fa 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif /* P1014 and it's derivatives don't support CAN and eTSEC3 */ if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 864b3ce8f..cfbae6911 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) /* Delete eLBC node as it is muxed with USB2 controller */ diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5ff6ea6aa..79689199c 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -25,15 +25,17 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifndef CONFIG_NAND_SPL SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#endif + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 4671128af..a60c5a20a 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_board_fixup_qe_pins(blob); #endif #endif + +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif } #endif diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 0a1dfa7cc..4b0d577e2 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -139,7 +139,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -149,13 +148,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c index a4bfbc978..57bd21fc2 100644 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -25,6 +25,7 @@ #include <mpc8260.h> #include <asm/m8260_pci.h> #include <miiphy.h> +#include <linux/compiler.h> #include "m88e6060.h" @@ -263,7 +264,7 @@ int board_early_init_f (void) int misc_init_r (void) { volatile ioport_t *iop; - unsigned char temp; + __maybe_unused unsigned char temp; #if 0 /* DUMP UPMA RAM */ volatile immap_t *immap; diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c index effe65a36..fd72f4731 100644 --- a/board/g2000/strataflash.c +++ b/board/g2000/strataflash.c @@ -666,14 +666,11 @@ static ulong flash_get_size (ulong base, int banknum) static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) { - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr(info, 0, 0); cptr.cp = (uchar *)dest; - /* Check if Flash is (sufficiently) erased */ switch(info->portwidth) { case FLASH_CFI_8BIT: diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index ecba66ec7..f55afbd12 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -87,7 +87,6 @@ static void print_fpga_info(unsigned dev) u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; - unsigned feature_compression; unsigned feature_rs232; unsigned feature_audio; unsigned feature_sysclock; @@ -111,7 +110,6 @@ static void print_fpga_info(unsigned dev) unit_type = (versions >> 4) & 0x000f; hardware_version = versions & 0x000f; - feature_compression = (fpga_features >> 13) & 0x0003; feature_rs232 = fpga_features & (1<<11); feature_audio = (fpga_features >> 9) & 0x0003; feature_sysclock = (fpga_features >> 7) & 0x0003; diff --git a/board/genietv/flash.c b/board/genietv/flash.c index 5313ad8b0..19a428abb 100644 --- a/board/genietv/flash.c +++ b/board/genietv/flash.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2011 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -24,32 +24,33 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); +static ulong flash_get_size(vu_long *addr, flash_info_t *info); +static int write_word(flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets(ulong base, flash_info_t *info); /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, + &flash_info[0]); /* Setup offsets */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* Monitor protection ON by default */ @@ -59,21 +60,15 @@ unsigned long flash_init (void) &flash_info[0]); #endif - size_b1 = 0 ; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } /*----------------------------------------------------------------------- * Fix this to support variable sector sizes */ -static void flash_get_offsets (ulong base, flash_info_t *info) +static void flash_get_offsets(ulong base, flash_info_t *info) { int i; @@ -87,73 +82,85 @@ static void flash_get_offsets (ulong base, flash_info_t *info) /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void flash_print_info(flash_info_t *info) { int i; - if (info->flash_id == FLASH_UNKNOWN) - { - puts ("missing or unknown FLASH type\n"); + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); return; } - switch (info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_BM: + printf("BRIGHT MICRO "); + break; + default: + printf("Unknown Vendor "); + break; } - switch (info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } if (info->size >> 20) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); } else { - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, + info->sector_count); } - puts (" Sector Start Addresses:"); + puts(" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) - { + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - { - puts ("\n "); - } + puts("\n "); - printf (" %08lX%s", + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); } - putc ('\n'); + putc('\n'); return; } /*----------------------------------------------------------------------- @@ -163,7 +170,7 @@ void flash_print_info (flash_info_t *info) * The following code cannot be run from FLASH! */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) +static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; volatile unsigned char *caddr; @@ -173,9 +180,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ -#if 0 - printf("Base address is: %08x\n", caddr); -#endif + debug("Base address is: %8p\n", caddr); caddr[0x0555] = 0xAA; caddr[0x02AA] = 0x55; @@ -183,51 +188,47 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = caddr[0]; -#if 0 - printf("Manufact ID: %02x\n", value); -#endif - switch (value) - { - case 0x1: /* AMD_MANUFACT */ - info->flash_id = FLASH_MAN_AMD; - break; + debug("Manufact ID: %02x\n", value); - case 0x4: /* FUJ_MANUFACT */ - info->flash_id = FLASH_MAN_FUJ; + switch (value) { + case 0x1: /* AMD_MANUFACT */ + info->flash_id = FLASH_MAN_AMD; + break; + case 0x4: /* FUJ_MANUFACT */ + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; } value = caddr[1]; /* device ID */ -#if 0 - printf("Device ID: %02x\n", value); -#endif - switch (value) - { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + debug("Device ID: %02x\n", value); + + switch (value) { + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ } - flash_get_offsets ((ulong)addr, &flash_info[0]); + flash_get_offsets((ulong)addr, &flash_info[0]); /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ + for (i = 0; i < info->sector_count; i++) { + /* + * read sector protection at sector address, + * (A7 .. A0) = 0x02 + * D0 = 1 if protected + */ caddr = (volatile unsigned char *)(info->start[i]); info->protect[i] = caddr[2] & 1; } @@ -235,52 +236,47 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* * Prevent writes to uninitialized FLASH. */ - if (info->flash_id != FLASH_UNKNOWN) - { + if (info->flash_id != FLASH_UNKNOWN) { caddr = (volatile unsigned char *)info->start[0]; *caddr = 0xF0; /* reset bank */ } - return (info->size); + return info->size; } - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); int flag, prot, sect, l_sect; ulong start, now, last; if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; } if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); + printf("Can't erase unknown flash type - aborted\n"); return 1; } prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } l_sect = -1; @@ -295,7 +291,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[0x02AA] = 0x55; /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr = (volatile unsigned char *)(info->start[sect]); addr[0] = 0x30; @@ -308,7 +304,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); /* * We wait for the last triggered sector @@ -316,19 +312,21 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - start = get_timer (0); + start = get_timer(0); last = start; addr = (volatile unsigned char *)(info->start[l_sect]); - while ((addr[0] & 0xFF) != 0xFF) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + while ((addr[0] & 0xFF) != 0xFF) { + + now = get_timer(start); + + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ - putc ('.'); + putc('.'); last = now; } } @@ -339,7 +337,7 @@ DONE: addr[0] = 0xF0; /* reset bank */ - printf (" done\n"); + printf(" done\n"); return 0; } @@ -350,7 +348,7 @@ DONE: * 2 - Flash not erased */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; @@ -360,23 +358,26 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i = 0, cp = wp; i < l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { + for (; cnt == 0 && i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; } @@ -385,33 +386,33 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { + for (; i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); + return write_word(info, wp, data); } /*----------------------------------------------------------------------- @@ -420,10 +421,11 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), - *cdest,*cdata; + volatile unsigned char *cdest, *cdata; + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); ulong start; int flag, count = 4 ; @@ -431,39 +433,33 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) cdata = (volatile unsigned char *)&data ; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } + if ((*((vu_long *)dest) & data) != data) + return 2; - while(count--) - { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); + while (count--) { - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); - *cdest = *cdata; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); + *cdest = *cdata; - /* data polling for D7 */ - start = get_timer (0); - while ((*cdest ^ *cdata) & 0x80) - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((*cdest ^ *cdata) & 0x80) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - } - cdata++ ; - cdest++ ; + cdata++ ; + cdest++ ; } - return (0); + return 0; } - -/*----------------------------------------------------------------------- - */ diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c index 6035f6976..fb29659e2 100644 --- a/board/gw8260/flash.c +++ b/board/gw8260/flash.c @@ -63,54 +63,50 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); /* functions */ /*********************************************************************/ -/*********************************************************************/ -/* NAME: flash_init() - initializes flash banks */ -/* */ -/* DESCRIPTION: */ -/* This function initializes the flash bank(s). */ -/* */ -/* RETURNS: */ -/* The size in bytes of the flash */ -/* */ -/* RESTRICTIONS/LIMITATIONS: */ -/* */ -/* */ -/*********************************************************************/ -unsigned long flash_init (void) +/* + * NAME: flash_init() - initializes flash banks + * + * DESCRIPTION: + * This function initializes the flash bank(s). + * + * RETURNS: + * The size in bytes of the flash + * + * RESTRICTIONS/LIMITATIONS: + * + * + */ +unsigned long flash_init(void) { - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); - - /* - * protect monitor and environment sectors - */ - + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; + + /* for now, only support the 4 MB Flash SIMM */ + (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, + &flash_info[0]); + /* + * protect monitor and environment sectors + */ #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); +#ifndef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif - return (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); /*size*/ + return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; /*size */ } /*********************************************************************/ diff --git a/board/hale/tt01/Makefile b/board/hale/tt01/Makefile new file mode 100644 index 000000000..f6b28541e --- /dev/null +++ b/board/hale/tt01/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2009 HALE electronic <helmut.raiger@hale.at> +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o +COBJS := tt01.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/hale/tt01/lowlevel_init.S b/board/hale/tt01/lowlevel_init.S new file mode 100644 index 000000000..6e9dc80ef --- /dev/null +++ b/board/hale/tt01/lowlevel_init.S @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (C) Copyright 2011 Helmut Raiger <helmut.raiger@hale.at> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <asm/arch/imx-regs.h> +#include <asm/macro.h> + +.globl lowlevel_init +lowlevel_init: + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + mov pc, lr diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c new file mode 100644 index 000000000..2995c8f10 --- /dev/null +++ b/board/hale/tt01/tt01.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at> + * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <command.h> +#include <pmic.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define BOARD_STRING "Board: HALE TT-01" + +/* Clock configuration */ +#define CCM_CCMR_SETUP 0x074B0BF5 + +static void board_setup_clocks(void) +{ + struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE; + volatile int wait = 0x10000; + + writel(CCM_CCMR_SETUP, &ccm->ccmr); + while (wait--) + ; + + writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr); + writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr); + + /* Set up clock to 532MHz */ + writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | + PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | + PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | + PDR0_MCU_PODF(0), &ccm->pdr0); + writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12), + &ccm->mpctl); + writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1), + &ccm->spctl); +} + +/* DRAM configuration */ + +#define ESDMISC_MDDR_SETUP 0x00000004 +#define ESDMISC_MDDR_RESET_DL 0x0000000c +/* + * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below: + * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10 + * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + * note: all but tWTR (1), tRC (111) are reset defaults, + * the same values work in the jtag configuration + * + * Bluetechnix setup has 0x75e73a (for 128MB) = + * 0b 0111 0101 1110 0111 0011 1010 + * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01 + * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11 + * tRCD = 011, tRC = 010 + */ +#define ESDCFG0_MDDR_SETUP 0x006ac73a +#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) +#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ(2) | ESDCTL_BL(1)) +#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) +#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) +#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) +#define ESDCTL_RW ESDCTL_SETTINGS + +static void board_setup_sdram(void) +{ + u32 *pad; + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; + + /* + * setup pad control for the controller pins + * no loopback, no pull, no keeper, no open drain, + * standard input, standard drive, slow slew rate + */ + for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B; + pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++) + *pad = 0; + + /* set up MX31 DDR Memory Controller */ + writel(ESDMISC_MDDR_SETUP, &esdc->misc); + writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0); + + /* perform DDR init sequence for CSD0 */ + writel(ESDCTL_PRECHARGE, &esdc->ctl0); + writel(0x12344321, CSD0_BASE+0x0f00); + writel(ESDCTL_AUTOREFRESH, &esdc->ctl0); + writel(0x12344321, CSD0_BASE); + writel(0x12344321, CSD0_BASE); + writel(ESDCTL_LOADMODEREG, &esdc->ctl0); + writeb(0xda, CSD0_BASE+0x33); + writeb(0xff, CSD0_BASE+0x1000000); + writel(ESDCTL_RW, &esdc->ctl0); + writel(0xDEADBEEF, CSD0_BASE); + writel(ESDMISC_MDDR_RESET_DL, &esdc->misc); +} + +static void tt01_spi3_hw_init(void) +{ + /* CSPI3 */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC)); + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC)); + /* CSPI3, SS0 = Atlas */ + mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1)); + + /* start CSPI3 clock (3 = always on except if PLL off) */ + setbits_le32(CCM_CGR0, 3 << 16); +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +int board_early_init_f(void) +{ + /* CS4: FPGA incl. network controller */ + struct mxc_weimcs cs4 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) + }; + + /* this seems essential, won't start without, but why? */ + writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF); + + board_setup_clocks(); + board_setup_sdram(); + mxc_setup_weimcs(4, &cs4); + + /* Setup UART2 and SPI3 pins */ + mx31_uart2_hw_init(); + tt01_spi3_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + return 0; +} + +int board_late_init(void) +{ + pmic_init(); + +#ifdef CONFIG_HW_WATCHDOG + mxc_hw_watchdog_enable(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts(BOARD_STRING "\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/hymod/input.c b/board/hymod/input.c index 998132d65..1a2b8d23a 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -76,7 +76,6 @@ hymod_get_ethaddr (void) if (n == 17) { int i; char *p, *q; - uchar ea[6]; /* see if it looks like an ethernet address */ @@ -85,7 +84,7 @@ hymod_get_ethaddr (void) for (i = 0; i < 6; i++) { char term = (i == 5 ? '\0' : ':'); - ea[i] = simple_strtol (p, &q, 16); + (void)simple_strtol (p, &q, 16); if ((q - p) != 2 || *q++ != term) break; diff --git a/board/icu862/flash.c b/board/icu862/flash.c index 2afeff4b5..7f72258f1 100644 --- a/board/icu862/flash.c +++ b/board/icu862/flash.c @@ -52,13 +52,12 @@ unsigned long flash_init (void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; - } /* Static FLASH Bank configuration here - FIXME XXX */ @@ -70,27 +69,6 @@ unsigned long flash_init (void) size_b0 >> 20); } - if (FLASH_BASE1_PRELIM != 0x0) { - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: Bank 1 (0x%08lx = %ld MB)" - " > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 >> 20, - size_b0, size_b0 >> 20); - - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - } else { - size_b1 = 0; - } - /* Remap FLASH according to real size */ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; @@ -117,13 +95,9 @@ unsigned long flash_init (void) #endif /* ICU862 Board has only one Flash Bank */ - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c index a4c0b54bc..dbe3c3cf7 100644 --- a/board/icu862/pcmcia.c +++ b/board/icu862/pcmcia.c @@ -18,18 +18,16 @@ static void cfg_port_B (void) { - volatile immap_t *immap; volatile cpm8xx_t *cp; uint reg; - immap = (immap_t *)CONFIG_SYS_IMMR; cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* - * Configure Port B for TPS2205 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ + * Configure Port B for TPS2205 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ reg = cp->cp_pbdat; reg |= (TPS2205_VPP_PGM | TPS2205_VPP_VCC | /* VAVPP => Hi-Z */ TPS2205_VCC3 | TPS2205_VCC5 | /* VAVCC => Hi-Z */ @@ -47,7 +45,6 @@ static void cfg_port_B (void) int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; @@ -58,7 +55,6 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); @@ -188,7 +184,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; @@ -198,7 +193,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index d621833cc..02db07f1d 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -281,10 +281,9 @@ phys_size_t initdram (int board_type) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - long psize, lsize; + long psize; psize = 16 * 1024 * 1024; - lsize = 0; memctl->memc_psrt = CONFIG_SYS_PSRT; memctl->memc_mptpr = CONFIG_SYS_MPTPR; diff --git a/board/innokom/flash.c b/board/innokom/flash.c deleted file mode 100644 index ed4b9872a..000000000 --- a/board/innokom/flash.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> - * - * (C) Copyright 2002 - * Auerswald GmbH & Co KG, Germany - * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/pxa-regs.h> - -/* Debugging macros ------------------------------------------------------ */ - -#undef FLASH_DEBUG - -/* Some debug macros */ -#if (FLASH_DEBUG > 2 ) -#define PRINTK3(args...) printf(args) -#else -#define PRINTK3(args...) -#endif - -#if FLASH_DEBUG > 1 -#define PRINTK2(args...) printf(args) -#else -#define PRINTK2(args...) -#endif - -#ifdef FLASH_DEBUG -#define PRINTK(args...) printf(args) -#else -#define PRINTK(args...) -#endif - -/* ------------------------------------------------------------------------ */ - -/* Development system: we have only 16 MB Flash */ -#ifdef CONFIG_MTD_INNOKOM_16MB -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB (during development) */ -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ -#endif - -/* Production system: we have 64 MB Flash */ -#ifdef CONFIG_MTD_INNOKOM_64MB -#define FLASH_BANK_SIZE 0x04000000 /* 64 MB */ -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/** - * flash_init: - initialize data structures for flash chips - * - * @return: size of the flash - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect u-boot sectors */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + (256*1024) - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_IS_IN_FLASH - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - - -/** - * flash_print_info: - print information about the flash situation - * - * @param info: - */ - -void flash_print_info (flash_info_t *info) -{ - int i, j; - - for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) { - - switch (info->flash_id & FLASH_VENDMASK) { - - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf("Intel: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf("28F128J3 (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } -} - - -/** - * flash_erase: - erase flash sectors - * - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - ulong start; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) prot++; - } - - if (prot) return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - - PRINTK("\n"); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - u16 * volatile addr = (u16 * volatile)(info->start[sect]); - - PRINTK("unlocking sector\n"); - *addr = 0x0060; - *addr = 0x00d0; - *addr = 0x00ff; - - PRINTK("erasing sector\n"); - *addr = 0x0020; - PRINTK("confirming erase\n"); - *addr = 0x00D0; - - while ((*addr & 0x0080) != 0x0080) { - PRINTK("."); - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0x00B0; /* suspend erase*/ - *addr = 0x00FF; /* read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - PRINTK("clearing status register\n"); - *addr = 0x0050; - PRINTK("resetting to read mode"); - *addr = 0x00FF; - } - - printf("ok.\n"); - } - - if (ctrlc()) printf("User Interrupt!\n"); - - outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_word: - copy memory to flash - * - * @param info: - * @param dest: - * @param data: - * @return: - */ - -static int write_word (flash_info_t *info, ulong dest, ushort data) -{ - volatile u16 *addr = (u16 *)dest, val; - int rc = ERR_OK; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts(); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while(((val = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - *addr = 0xB0; /* suspend program command */ - goto outahere; - } - } - - if(val & 0x1A) { /* check for error */ - printf("\nFlash write error %02x at address %08lx\n", - (int)val, (unsigned long)dest); - if(val & (1<<3)) { - printf("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if(val & (1<<1)) { - printf("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if(val & (1<<4)) { - printf("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - - outahere: - - *addr = 0xFF; /* read array command */ - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - for (; i<2 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt==0 && i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((ushort*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - return write_word(info, wp, data); -} diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c deleted file mode 100644 index 22de7e340..000000000 --- a/board/innokom/innokom.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de - * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/pxa-regs.h> -#include <asm/mach-types.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -/** - * i2c_init_board - reset i2c bus. When the board is powercycled during a - * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. - * The Innokom board has GPIO70 connected to SCLK which can be toggled - * until all chips think that their current cycles are finished. - */ -int i2c_init_board(void) -{ - int i; - - /* set gpio pin low _before_ we change direction to output */ - writel(GPIO_bit(70), GPCR(70)); - - /* now toggle between output=low and high-impedance */ - for (i = 0; i < 20; i++) { - writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */ - udelay(10); - writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */ - udelay(10); - } - - return 0; -} - - -/** - * misc_init_r: - misc initialisation routines - */ - -int misc_init_r(void) -{ - char *str; - - /* determine if the software update key is pressed during startup */ - if (readl(GPLR0) & 0x00000800) { - printf("using bootcmd_normal (sw-update button not pressed)\n"); - str = getenv("bootcmd_normal"); - } else { - printf("using bootcmd_update (sw-update button pressed)\n"); - str = getenv("bootcmd_update"); - } - - setenv("bootcmd",str); - - return 0; -} - - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; - gd->bd->bi_boot_params = 0xa0000100; - gd->bd->bi_baudrate = CONFIG_BAUDRATE; - - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -/** - * innokom_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1,2) - * @param state: switch on (1) or off (0) - */ - -void innokom_set_led(int led, int state) -{ - switch(led) { -/* - case 0: if (state==1) { - GPCR0 |= CSB226_USER_LED0; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED0; - } - break; - - case 1: if (state==1) { - GPCR0 |= CSB226_USER_LED1; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED1; - } - break; - - case 2: if (state==1) { - GPCR0 |= CSB226_USER_LED2; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED2; - } - break; -*/ - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - switch(status) { -/* - case 1: csb226_set_led(0,1); break; - case 5: csb226_set_led(1,1); break; - case 15: csb226_set_led(2,1); break; -*/ - } - - return; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/jse/flash.c b/board/jse/flash.c index 5735f19b8..27cd4698e 100644 --- a/board/jse/flash.c +++ b/board/jse/flash.c @@ -301,7 +301,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -331,8 +331,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -360,7 +358,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -379,16 +376,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* wait at least 80us - let's wait 1 ms */ udelay (1000); -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - -DONE: -#endif /* reset to read mode */ addr = (FLASH_WORD_SIZE *) info->start[0]; addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index d3d8ea51f..2a2994373 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -140,7 +140,6 @@ int board_init() mx25_uart1_init_pins(); #endif /* board id for linux */ - gd->bd->bi_arch_number = MACH_TYPE_TX25; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; } diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 612dd2a05..f26230648 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -39,7 +39,10 @@ #include <i2c.h> #endif +#if !defined(CONFIG_MPC83xx) static void i2c_write_start_seq(void); +#endif + DECLARE_GLOBAL_DATA_PTR; /* @@ -89,9 +92,7 @@ int set_km_env(void) return 0; } -#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ -#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) - +#if defined(CONFIG_SYS_I2C_INIT_BOARD) #if !defined(CONFIG_MPC83xx) static void i2c_write_start_seq(void) { @@ -171,68 +172,6 @@ int i2c_make_abort(void) #endif return ret; } -#endif /* !MPC83xx */ - -#if defined(CONFIG_MPC83xx) -static void i2c_write_start_seq(void) -{ - struct fsl_i2c *dev; - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN)); -} - -int i2c_make_abort(void) -{ - struct fsl_i2c *dev; - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); - uchar dummy; - uchar last; - int nbr_read = 0; - int i = 0; - int ret = 0; - - /* wait after each operation to finsh with a delay */ - out_8(&dev->cr, (I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - dummy = in_8(&dev->dr); - udelay(DELAY_ABORT_SEQ); - last = in_8(&dev->dr); - nbr_read++; - - /* - * do read until the last bit is 1, but stop if the full eeprom is - * read. - */ - while (((last & 0x01) != 0x01) && - (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) { - udelay(DELAY_ABORT_SEQ); - last = in_8(&dev->dr); - nbr_read++; - } - if ((last & 0x01) != 0x01) - ret = -2; - if ((last != 0xff) || (nbr_read > 1)) - printf("[INFO] i2c abort after %d bytes (0x%02x)\n", - nbr_read, last); - udelay(DELAY_ABORT_SEQ); - out_8(&dev->cr, (I2C_CR_MEN)); - udelay(DELAY_ABORT_SEQ); - /* clear status reg */ - out_8(&dev->sr, 0); - - for (i = 0; i < 5; i++) - i2c_write_start_seq(); - if (ret != 0) - printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n", - nbr_read, last); - - return ret; -} #endif /** @@ -244,6 +183,8 @@ void i2c_init_board(void) /* Now run the AbortSequence() */ i2c_make_abort(); } +#endif + #if !defined(MACH_TYPE_KM_KIRKWOOD) int ethernet_present(void) diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index 0fb19cf33..6c1f6400c 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -136,6 +136,9 @@ int fdt_get_node_and_value(void *blob, char *propname, void **var); +#define DELAY_ABORT_SEQ 62 /* @200kHz 9 clocks = 44us, 62us is ok */ +#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) + int i2c_soft_read_pin(void); int i2c_make_abort(void); #endif /* __KEYMILE_COMMON_H */ diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile index 72945e283..472768a66 100644 --- a/board/keymile/km83xx/Makefile +++ b/board/keymile/km83xx/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS += $(BOARD).o ../common/common.o ../common/ivm.o +COBJS += $(BOARD).o ../common/common.o ../common/ivm.o $(BOARD)_i2c.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c new file mode 100644 index 000000000..8df92d887 --- /dev/null +++ b/board/keymile/km83xx/km83xx_i2c.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2011 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <linux/ctype.h> +#include "../common/common.h" + +static void i2c_write_start_seq(void) +{ + struct fsl_i2c *dev; + dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN)); +} + +int i2c_make_abort(void) +{ + struct fsl_i2c *dev; + dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); + uchar last; + int nbr_read = 0; + int i = 0; + int ret = 0; + + /* wait after each operation to finsh with a delay */ + out_8(&dev->cr, (I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); + udelay(DELAY_ABORT_SEQ); + in_8(&dev->dr); + udelay(DELAY_ABORT_SEQ); + last = in_8(&dev->dr); + nbr_read++; + + /* + * do read until the last bit is 1, but stop if the full eeprom is + * read. + */ + while (((last & 0x01) != 0x01) && + (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) { + udelay(DELAY_ABORT_SEQ); + last = in_8(&dev->dr); + nbr_read++; + } + if ((last & 0x01) != 0x01) + ret = -2; + if ((last != 0xff) || (nbr_read > 1)) + printf("[INFO] i2c abort after %d bytes (0x%02x)\n", + nbr_read, last); + udelay(DELAY_ABORT_SEQ); + out_8(&dev->cr, (I2C_CR_MEN)); + udelay(DELAY_ABORT_SEQ); + /* clear status reg */ + out_8(&dev->sr, 0); + + for (i = 0; i < 5; i++) + i2c_write_start_seq(); + if (ret != 0) + printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n", + nbr_read, last); + + return ret; +} diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 6ef5e5da1..ca33aaec5 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -207,8 +207,14 @@ int misc_init_r(void) if (wait_for_ne != NULL) { if (strcmp(wait_for_ne, "true") == 0) { int cnt = 0; + int abort = 0; puts("NE go: "); while (startup_allowed() == 0) { + if (tstc()) { + (void) getc(); /* consume input */ + abort = 1; + break; + } udelay(200000); cnt++; if (cnt == 5) @@ -218,7 +224,10 @@ int misc_init_r(void) puts(" \b\b\b\b"); } } - puts("OK\n"); + if (abort == 1) + printf("\nAbort waiting for ne\n"); + else + puts("OK\n"); } } #endif @@ -258,17 +267,17 @@ int board_early_init_f(void) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif - +#if defined(CONFIG_KM_RECONFIG_XLX) + /* trigger the reconfiguration of the xilinx fpga */ + kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); + kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); + kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); +#endif return 0; } int board_init(void) { - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; - /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; @@ -396,6 +405,15 @@ int hush_init_var(void) #endif #if defined(CONFIG_BOOTCOUNT_LIMIT) +const ulong patterns[] = { 0x00000000, + 0xFFFFFFFF, + 0xFF00FF00, + 0x0F0F0F0F, + 0xF0F0F0F0}; +const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns); +const ulong OFFS_PATTERN = 3; +const ulong REPEAT_PATTERN = 1000; + void bootcount_store(ulong a) { volatile ulong *save_addr; @@ -407,21 +425,34 @@ void bootcount_store(ulong a) save_addr = (ulong*)(size - BOOTCOUNT_ADDR); writel(a, save_addr); writel(BOOTCOUNT_MAGIC, &save_addr[1]); + + for (i = 0; i < REPEAT_PATTERN; i++) + writel(patterns[i % NBR_OF_PATTERNS], + &save_addr[i+OFFS_PATTERN]); + } ulong bootcount_load(void) { volatile ulong *save_addr; volatile ulong size = 0; - int i; + ulong counter = 0; + int i, tmp; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { size += gd->bd->bi_dram[i].size; } save_addr = (ulong*)(size - BOOTCOUNT_ADDR); - if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC) - return 0; - else - return readl(save_addr); + + counter = readl(&save_addr[0]); + + /* Is the counter reliable, check in the big pattern for bit errors */ + for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) { + tmp = readl(&save_addr[i+OFFS_PATTERN]); + if (tmp != patterns[i % NBR_OF_PATTERNS]) + counter = 0; + } + return counter; } #endif diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c index ce6b1861d..61ba586e1 100644 --- a/board/kup/common/pcmcia.c +++ b/board/kup/common/pcmcia.c @@ -20,7 +20,6 @@ int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; @@ -30,15 +29,14 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ /* clear interrupt state, and disable interrupts */ @@ -46,9 +44,9 @@ int pcmcia_hardware_enable(int slot) pcmp->pcmc_per &= ~PCMCIA_MASK(slot); /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -57,9 +55,9 @@ int pcmcia_hardware_enable(int slot) udelay(2500); /* - * Configure Port B pins for - * 3 Volts enable - */ + * Configure Port B pins for + * 3 Volts enable + */ if (slot) { /* Slot A is built-in */ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; @@ -67,8 +65,8 @@ int pcmcia_hardware_enable(int slot) cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ } /* - * Make sure there is a card in the slot, then configure the interface. - */ + * Make sure there is a card in the slot, then configure the interface. + */ udelay(10000); debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, @@ -79,8 +77,8 @@ int pcmcia_hardware_enable(int slot) } /* - * Power On. - */ + * Power On. + */ printf("%s Slot %c:", slot ? "" : "\n", 'A' + slot); mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); reg = pcmp->pcmc_pipr; @@ -149,7 +147,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; @@ -162,14 +159,13 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) if (!slot) /* Slot A is not configurable */ return 0; - immap = (immap_t *)CONFIG_SYS_IMMR; pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(slot); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -179,9 +175,9 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) debug ("PCMCIA power OFF\n"); /* - * Configure Port B pins for - * 3 Volts enable - */ + * Configure Port B pins for + * 3 Volts enable + */ cp->cp_pbdir |= KUP4K_PCMCIA_B_3V3; cp->cp_pbpar &= ~KUP4K_PCMCIA_B_3V3; /* remove all power */ diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 267821c48..e1dc8f7cf 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -152,7 +152,7 @@ phys_size_t initdram(int board_type) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size = 0; - uchar *latch,rev,mod,tmp; + uchar *latch, rev, tmp; /* * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision @@ -164,7 +164,6 @@ phys_size_t initdram(int board_type) latch = (uchar *)0x90000200; tmp = swapbyte(*latch); rev = (tmp & 0xF8) >> 3; - mod = (tmp & 0x07); upmconfig(UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c index 568fdf5f2..f3e3fce82 100644 --- a/board/linkstation/ide.c +++ b/board/linkstation/ide.c @@ -62,14 +62,16 @@ int ide_preinit (void) &ide_bus_offset32); ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe; ide_bus_offset[0] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[0] & 0xfffffffe, - PCI_REGION_IO); - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, - (u32 *) &ide_bus_offset[1]); - ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, - ide_bus_offset[1] & 0xfffffffe, - PCI_REGION_IO); + ide_bus_offset[0] & 0xfffffffe, + PCI_REGION_IO); + if (CONFIG_SYS_IDE_MAXBUS > 1) { + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, + (u32 *) &ide_bus_offset[1]); + ide_bus_offset[1] &= 0xfffffffe; + ide_bus_offset[1] = pci_hose_bus_to_phys(&hose, + ide_bus_offset[1] & 0xfffffffe, + PCI_REGION_IO); + } } if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) { diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c index ad2e60d59..acbb9d54d 100644 --- a/board/lwmon/pcmcia.c +++ b/board/lwmon/pcmcia.c @@ -29,8 +29,6 @@ int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; uint reg, mask; @@ -51,10 +49,8 @@ int pcmcia_hardware_enable(int slot) #endif udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure SIUMCR to enable PCMCIA port B @@ -171,7 +167,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; volatile pcmconf8xx_t *pcmp; u_long reg; uchar val; @@ -181,7 +176,6 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) diff --git a/board/manroland/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c index ad256783c..db3821a5e 100644 --- a/board/manroland/uc100/pcmcia.c +++ b/board/manroland/uc100/pcmcia.c @@ -27,8 +27,8 @@ static void cfg_ports (void) immap = (immap_t *)CONFIG_SYS_IMMR; /* - * Configure Port A for MAX1602 PC-Card Power-Interface Switch - */ + * Configure Port A for MAX1602 PC-Card Power-Interface Switch + */ immap->im_ioport.iop_padat &= ~0x8000; /* set port x output to low */ immap->im_ioport.iop_padir |= 0x8000; /* enable port x as output */ @@ -40,7 +40,6 @@ static void cfg_ports (void) int pcmcia_hardware_enable(int slot) { volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; uint reg, mask; @@ -52,15 +51,14 @@ int pcmcia_hardware_enable(int slot) immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ cfg_ports (); /* - * Configure SIUMCR to enable PCMCIA port B - * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) - */ + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ /* clear interrupt state, and disable interrupts */ @@ -68,9 +66,9 @@ int pcmcia_hardware_enable(int slot) pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -78,8 +76,8 @@ int pcmcia_hardware_enable(int slot) udelay(500); /* - * Make sure there is a card in the slot, then configure the interface. - */ + * Make sure there is a card in the slot, then configure the interface. + */ udelay(10000); debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, @@ -90,19 +88,19 @@ int pcmcia_hardware_enable(int slot) } /* - * Power On. - */ + * Power On. + */ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); reg = pcmp->pcmc_pipr; debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg, (reg&PCMCIA_VS1(slot))?"n":"ff", (reg&PCMCIA_VS2(slot))?"n":"ff"); - if ((reg & mask) == mask) { + + if ((reg & mask) == mask) puts (" 5.0V card found: "); - } else { + else puts (" 3.3V card found: "); - } /* switch VCC on */ immap->im_ioport.iop_padat |= 0x8000; /* power enable 3.3V */ @@ -154,8 +152,6 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; u_long reg; debug ("voltage_set: " @@ -163,12 +159,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(_slot_); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -176,10 +170,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) udelay(500); /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ debug ("PCMCIA power OFF\n"); cfg_ports (); /* Enables switch, but all in Hi-Z */ diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile new file mode 100644 index 000000000..01cb51715 --- /dev/null +++ b/board/matrix_vision/mvblx/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += mvblx.o fpga.o +COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o +COBJS := $(COBJS-y) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +CFLAGS += -Werror + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk new file mode 100644 index 000000000..cf055db62 --- /dev/null +++ b/board/matrix_vision/mvblx/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006 +# Texas Instruments, <www.ti.com> +# +# Beagle Board uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c new file mode 100644 index 000000000..dacc13845 --- /dev/null +++ b/board/matrix_vision/mvblx/fpga.c @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2011 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * Michael Jones, Matrix Vision GmbH, michael.jones@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ACEX1K.h> +#include <command.h> +#include <asm/gpio.h> +#include "fpga.h" + +#ifdef FPGA_DEBUG +#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) +#else +#define fpga_debug(fmt, args...) +#endif + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, /* Altera_pre_fn */ + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + fast_passive_parallel, + Altera_EP3C5_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +#define GPIO_RESET 43 +#define GPIO_DCLK 65 +#define GPIO_nSTATUS 157 +#define GPIO_CONF_DONE 158 +#define GPIO_nCONFIG 159 +#define GPIO_DATA0 54 +#define GPIO_DATA1 55 +#define GPIO_DATA2 56 +#define GPIO_DATA3 57 +#define GPIO_DATA4 58 +#define GPIO_DATA5 60 +#define GPIO_DATA6 61 +#define GPIO_DATA7 62 + +DECLARE_GLOBAL_DATA_PTR; + +/* return FPGA_SUCCESS on success, else FPGA_FAIL + */ +int mvblx_init_fpga(void) +{ + fpga_debug("Initializing FPGA interface\n"); + fpga_init(); + fpga_add(fpga_altera, &cyclone2); + + if (gpio_request(GPIO_DCLK, "dclk") || + gpio_request(GPIO_nSTATUS, "nStatus") || +#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE + gpio_request(GPIO_CONF_DONE, "conf_done") || +#endif + gpio_request(GPIO_nCONFIG, "nConfig") || + gpio_request(GPIO_DATA0, "data0") || + gpio_request(GPIO_DATA1, "data1") || + gpio_request(GPIO_DATA2, "data2") || + gpio_request(GPIO_DATA3, "data3") || + gpio_request(GPIO_DATA4, "data4") || + gpio_request(GPIO_DATA5, "data5") || + gpio_request(GPIO_DATA6, "data6") || + gpio_request(GPIO_DATA7, "data7")) { + printf("%s: error requesting GPIOs.", __func__); + return FPGA_FAIL; + } + + /* set up outputs */ + gpio_direction_output(GPIO_DCLK, 0); + gpio_direction_output(GPIO_nCONFIG, 0); + gpio_direction_output(GPIO_DATA0, 0); + gpio_direction_output(GPIO_DATA1, 0); + gpio_direction_output(GPIO_DATA2, 0); + gpio_direction_output(GPIO_DATA3, 0); + gpio_direction_output(GPIO_DATA4, 0); + gpio_direction_output(GPIO_DATA5, 0); + gpio_direction_output(GPIO_DATA6, 0); + gpio_direction_output(GPIO_DATA7, 0); + + /* NB omap_free_gpio() resets to an input, so we can't + * free ie. nCONFIG, or else the FPGA would reset + * Q: presumably gpio_free() has the same effect? + */ + + /* set up inputs */ + gpio_direction_input(GPIO_nSTATUS); +#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE + gpio_direction_input(GPIO_CONF_DONE); +#endif + + fpga_config_fn(0, 1, 0); + udelay(60); + + return FPGA_SUCCESS; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert); + if (flush) { + gpio_set_value(GPIO_nCONFIG, !assert); + udelay(1); + gpio_set_value(GPIO_nCONFIG, assert); + } + + return assert; +} + +int fpga_done_fn(int cookie) +{ + int result = 0; + + /* since revA of BLX, we will not get this signal. */ + udelay(10); +#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE + fpga_debug("not waiting for CONF_DONE."); + result = 1; +#else + fpga_debug("CONF_DONE check ... "); + if (gpio_get_value(GPIO_CONF_DONE)) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + gpio_free(GPIO_CONF_DONE); +#endif + + return result; +} + +int fpga_status_fn(int cookie) +{ + int result = 0; + fpga_debug("STATUS check ... "); + + result = gpio_get_value(GPIO_nSTATUS); + + if (result < 0) + fpga_debug("error\n"); + else if (result > 0) + fpga_debug("high\n"); + else + fpga_debug("low\n"); + + return result; +} + +static inline int _write_fpga(u8 byte) +{ + gpio_set_value(GPIO_DATA0, byte & 0x01); + gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01); + gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01); + gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01); + gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01); + gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01); + gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01); + gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01); + + /* clock */ + gpio_set_value(GPIO_DCLK, 1); + udelay(1); + gpio_set_value(GPIO_DCLK, 0); + udelay(1); + + return 0; +} + +int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i]); + fpga_debug("-%s\n", __func__); + + return FPGA_SUCCESS; +} diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h new file mode 100644 index 000000000..3d427bf57 --- /dev/null +++ b/board/matrix_vision/mvblx/fpga.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mvblx_init_fpga(void); + +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c new file mode 100644 index 000000000..74b5b19be --- /dev/null +++ b/board/matrix_vision/mvblx/mvblx.c @@ -0,0 +1,169 @@ +/* + * MATRIX VISION GmbH mvBlueLYNX-X + * + * Derived from Beagle and Overo + * + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar <sunilsaini05@gmail.com> + * Shashi Ranjan <shashiranjanmca05@gmail.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include "mvblx.h" +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) +static void setup_net_chip(void); +#endif /* CONFIG_CMD_NET */ + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + printf("mvBlueLYNX-X\n"); + if (get_cpu_family() == CPU_OMAP36XX) + setenv("mpurate", "1000"); + else + setenv("mpurate", "600"); + + twl4030_power_init(); + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif /* CONFIG_CMD_NET */ + + mvblx_init_fpga(); + + mac_read_from_eeprom(); + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MVBLX(); +} + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + omap_mmc_init(1); + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + /* Configure GPMC registers */ + writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1); + writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2); + writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3); + writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4); + writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5); + writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6); + writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 139 as output pin */ + writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe); + + /* Now send a pulse on the GPIO pin */ + writel(GPIO11, &gpio5_base->setdataout); + udelay(1); + writel(GPIO11, &gpio5_base->cleardataout); + udelay(1); + writel(GPIO11, &gpio5_base->setdataout); +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} + +int overwrite_console(void) +{ + /* return TRUE if console should be overwritten */ + return 0; +} + +#endif /* CONFIG_CMD_NET */ diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h new file mode 100644 index 000000000..cda5b0bd0 --- /dev/null +++ b/board/matrix_vision/mvblx/mvblx.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2008 + * Dirk Behme <dirk.behme@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MVBLX_H_ +#define _MVBLX_H_ + +#include <asm/arch/sys_proto.h> + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 mvBlueLYNX-X camera", + "no NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MVBLX() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card 1*/\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\ + /*Expansion card 2 */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ + MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\ + MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\ + MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\ + MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\ + MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\ + /* USB EHCI (port 2) not used */\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ + MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ + MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ + MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\ + /* USB EHCI (port 1) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\ + /*Die to Die */\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ + +#endif diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c new file mode 100644 index 000000000..945a36dfe --- /dev/null +++ b/board/matrix_vision/mvblx/sys_eeprom.c @@ -0,0 +1,395 @@ +/* + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor + * York Sun (yorksun@freescale.com) + * Haiying Wang (haiying.wang@freescale.com) + * Timur Tabi (timur@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> + +/* #define DEBUG */ + +/* + * static eeprom: EEPROM layout + */ +static struct __attribute__ ((__packed__)) eeprom { + u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */ + u8 sn[10]; /* 0x10 - 0x19 Serial Number */ + u8 date[6]; /* 0x1A - 0x1F Build Date */ + u8 mac[6]; /* 0x20 - 0x25 MAC address */ + u8 reserved[10];/* 0x26 - 0x2f reserved */ + u32 crc; /* x+1 CRC32 checksum */ +} e; + +/* Set to 1 if we've read EEPROM into memory */ +static int has_been_read; + +/** + * show_eeprom - display the contents of the EEPROM + */ +static void show_eeprom(void) +{ + unsigned int crc; + char safe_string[16]; + +#ifdef DEBUG + int i; +#endif + u8 *p; + + /* ID */ + strncpy(safe_string, (char *)e.id, sizeof(e.id)); + safe_string[sizeof(e.id)-1] = 0; + printf("ID: mvBlueLYNX-X%s\n", safe_string); + + /* Serial number */ + strncpy(safe_string, (char *)e.sn, sizeof(e.sn)); + safe_string[sizeof(e.sn)-1] = 0; + printf("SN: %s\n", safe_string); + + /* Build date, BCD date values, as YYMMDDhhmmss */ + printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n", + e.date[0], e.date[1], e.date[2], + e.date[3] & 0x7F, e.date[4], e.date[5], + e.date[3] & 0x80 ? "PM" : ""); + + /* Show MAC address */ + p = e.mac; + printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n", + p[0], p[1], p[2], p[3], p[4], p[5]); + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + + if (crc == be32_to_cpu(e.crc)) + printf("CRC: %08x\n", be32_to_cpu(e.crc)); + else + printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc); + +#ifdef DEBUG + printf("EEPROM dump: (0x%x bytes)\n", sizeof(e)); + for (i = 0; i < sizeof(e); i++) { + if ((i % 16) == 0) + printf("%02X: ", i); + printf("%02X ", ((u8 *)&e)[i]); + if (((i % 16) == 15) || (i == sizeof(e) - 1)) + printf("\n"); + } +#endif +} + +/** + * read_eeprom - read the EEPROM into memory + */ +static int read_eeprom(void) +{ + int ret; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus; +#endif + + if (has_been_read) + return 0; + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + (uchar *)&e, sizeof(e)); + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + +#ifdef DEBUG + show_eeprom(); +#endif + + has_been_read = (ret == 0) ? 1 : 0; + + return ret; +} + +/** + * update_crc - update the CRC + * + * This function should be called after each update to the EEPROM structure, + * to make sure the CRC is always correct. + */ +static void update_crc(void) +{ + u32 crc; + + crc = crc32(0, (void *)&e, sizeof(e) - 4); + e.crc = cpu_to_be32(crc); +} + +/** + * prog_eeprom - write the EEPROM from memory + */ +static int prog_eeprom(void) +{ + int ret = 0; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus; +#endif + + update_crc(); + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + (uchar *)&e, sizeof(e)); + + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct eeprom e2; +#ifdef DEBUG + printf("%s verifying...\n", __func__); +#endif + ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + (uchar *)&e2, sizeof(e2)); + + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + + if (ret) { + printf("Programming failed.\n"); + has_been_read = 0; + return -1; + } + + printf("Programming passed.\n"); + return 0; +} + +/** + * h2i - converts hex character into a number + * + * This function takes a hexadecimal character (e.g. '7' or 'C') and returns + * the integer equivalent. + */ +static inline u8 h2i(char p) +{ + if ((p >= '0') && (p <= '9')) + return p - '0'; + + if ((p >= 'A') && (p <= 'F')) + return (p - 'A') + 10; + + if ((p >= 'a') && (p <= 'f')) + return (p - 'a') + 10; + + return 0; +} + +/** + * set_date - stores the build date into the EEPROM + * + * This function takes a pointer to a string in the format "YYMMDDhhmmss" + * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string, + * and stores it in the build date field of the EEPROM local copy. + */ +static void set_date(const char *string) +{ + unsigned int i; + + if (strlen(string) != 12) { + printf("Usage: mac date YYMMDDhhmmss\n"); + return; + } + + for (i = 0; i < 6; i++) + e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]); + + update_crc(); +} + +/** + * set_mac_address - stores a MAC address into the EEPROM + * + * This function takes a pointer to MAC address string + * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and + * stores it in the MAC address field in the EEPROM local copy. + */ +static void set_mac_address(const char *string) +{ + char *p = (char *) string; + unsigned int i; + + for (i = 0; *p && (i < 6); i++) { + e.mac[i] = simple_strtoul(p, &p, 16); + if (*p == ':') + p++; + } + + update_crc(); +} + +int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char cmd; + + if (argc == 1) { + show_eeprom(); + return 0; + } + + cmd = argv[1][0]; + + if (cmd == 'r') { +#ifdef DEBUG + printf("%s read\n", __func__); +#endif + read_eeprom(); + return 0; + } + + if (argc == 2) { + switch (cmd) { + case 's': /* save */ +#ifdef DEBUG + printf("%s save\n", __func__); +#endif + prog_eeprom(); + break; + default: + return cmd_usage(cmdtp); + } + + return 0; + } + + /* We know we have at least one parameter */ + + switch (cmd) { + case 'n': /* serial number */ +#ifdef DEBUG + printf("%s serial number\n", __func__); +#endif + memset(e.sn, 0, sizeof(e.sn)); + strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); + update_crc(); + break; + case 'd': /* date BCD format YYMMDDhhmmss */ + set_date(argv[2]); + break; + case 'e': /* errata */ + printf("mac errata not implemented\n"); + break; + case 'i': /* id */ + memset(e.id, 0, sizeof(e.id)); + strncpy((char *)e.id, argv[2], sizeof(e.id) - 1); + update_crc(); + break; + case 'p': /* ports */ + printf("mac ports not implemented (always 1 port)\n"); + break; + case '0' ... '9': + /* we only have "mac 0" but any digit can be used here */ + set_mac_address(argv[2]); + break; + case 'h': /* help */ + default: + return cmd_usage(cmdtp); + } + + return 0; +} + +int mac_read_from_eeprom(void) +{ + u32 crc, crc_offset = offsetof(struct eeprom, crc); + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */ + + if (read_eeprom()) { + printf("EEPROM Read failed.\n"); + return -1; + } + + crc = crc32(0, (void *)&e, crc_offset); + crcp = (void *)&e + crc_offset; + if (crc != be32_to_cpu(*crcp)) { + printf("EEPROM CRC mismatch (%08x != %08x)\n", crc, + be32_to_cpu(e.crc)); + return -1; + } + + if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) && + memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { + char ethaddr[9]; + + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + e.mac[0], + e.mac[1], + e.mac[2], + e.mac[3], + e.mac[4], + e.mac[5]); + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!getenv("ethaddr")) + setenv("ethaddr", ethaddr); + } + + if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) && + memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) { + char serial_num[12]; + + strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1); + /* Only initialize environment variables that are blank + * (i.e. have not yet been set) + */ + if (!getenv("serial#")) + setenv("serial#", serial_num); + } + + /* TODO should I calculate CRC here? */ + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + char *serial = getenv("serial#"); + + if (serial && (strlen(serial) > 3)) { + /* use the numerical part of the serial number LXnnnnnn */ + serialnr->high = 0; + serialnr->low = simple_strtoul(serial + 2, NULL, 10); + } else { + serialnr->high = 0; + serialnr->low = 0; + } +} +#endif diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c index 255796bd1..0f014e1ad 100644 --- a/board/mbx8xx/mbx8xx.c +++ b/board/mbx8xx/mbx8xx.c @@ -117,14 +117,16 @@ static const uint sdram_table_50[] = { /* ------------------------------------------------------------------------- */ +#ifdef CONFIG_SYS_USE_OSCCLK static unsigned int get_reffreq(void); +#endif static unsigned int board_get_cpufreq(void); void mbx_init (void) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; - ulong speed, refclock, plprcr, sccr; + ulong speed, plprcr, sccr; ulong br0_32 = memctl->memc_br0 & 0x400; /* real-time clock status and control register */ @@ -152,7 +154,6 @@ void mbx_init (void) immr->im_clkrst.car_sccr = sccr; speed = board_get_cpufreq (); - refclock = get_reffreq (); #if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) plprcr = CONFIG_SYS_PLPRCR; @@ -163,7 +164,7 @@ void mbx_init (void) #endif #ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */ - plprcr |= ((speed + refclock / 2) / refclock - 1) << 20; + plprcr |= ((speed + get_reffreq() / 2) / refclock - 1) << 20; #endif immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; @@ -226,21 +227,27 @@ static unsigned int board_get_cpufreq (void) { #ifndef CONFIG_8xx_GCLK_FREQ vpd_packet_t *packet; + ulong *p; packet = vpd_find_packet (VPD_PID_ICS); - return *((ulong *) packet->data); + p = (ulong *)packet->data; + return *p; #else return((unsigned int)CONFIG_8xx_GCLK_FREQ ); #endif /* CONFIG_8xx_GCLK_FREQ */ } +#ifdef CONFIG_SYS_USE_OSCCLK static unsigned int get_reffreq (void) { vpd_packet_t *packet; + ulong *p; packet = vpd_find_packet (VPD_PID_RCS); - return *((ulong *) packet->data); + p = (ulong *)packet->data; + return *p; } +#endif static void board_get_enetaddr(uchar *addr) { diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c index e672d8c78..497e260a0 100644 --- a/board/mbx8xx/pcmcia.c +++ b/board/mbx8xx/pcmcia.c @@ -77,10 +77,7 @@ int pcmcia_voltage_set (int slot, int vcc, int vpp) int pcmcia_hardware_enable (int slot) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; uint reg, mask; debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", @@ -88,10 +85,7 @@ int pcmcia_hardware_enable (int slot) udelay (10000); - immap = (immap_t *) CONFIG_SYS_IMMR; - sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm)); /* clear interrupt state, and disable interrupts */ pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 49213d0b3..415287384 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -341,7 +341,7 @@ int do_auto_update(void) { block_dev_desc_t *stor_dev; long sz; - int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; + int i, res = 0, cnt, old_ctrlc; char *env; long start, end; @@ -450,8 +450,6 @@ int do_auto_update(void) /* make sure that we see CTRL-C and save the old state */ old_ctrlc = disable_ctrlc(0); - bitmap_first = 0; - /* validate the images first */ for (i = 0; i < AU_MAXFILES; i++) { ulong imsize; @@ -506,14 +504,11 @@ int do_auto_update(void) /* this is really not a good idea, but it's what the */ /* customer wants. */ cnt = 0; - got_ctrlc = 0; do { res = au_do_update(i, sz); /* let the user break out of the loop */ if (ctrlc() || had_ctrlc()) { clear_ctrlc(); - if (res < 0) - got_ctrlc = 1; break; } cnt++; diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c index 726366ddf..d8f754c4a 100644 --- a/board/mcc200/lcd.c +++ b/board/mcc200/lcd.c @@ -55,6 +55,9 @@ #define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ #define PSOC_WAIT_TIME 10 /* usec */ +#include <video_font.h> +#define FONT_WIDTH VIDEO_FONT_WIDTH + DECLARE_GLOBAL_DATA_PTR; /* @@ -185,7 +188,6 @@ void lcd_enable (void) } #ifdef CONFIG_PROGRESSBAR -#define FONT_WIDTH 8 /* the same as VIDEO_FONT_WIDTH in video_font.h */ void show_progress (int size, int tot) { int cnt; diff --git a/board/mousse/flash.c b/board/mousse/flash.c index d729f33f9..cc405356d 100644 --- a/board/mousse/flash.c +++ b/board/mousse/flash.c @@ -776,8 +776,7 @@ void flash_print_info (flash_info_t * info) */ int flash_erase (flash_info_t * info, int s_first, int s_last) { - vu_long *addr = (vu_long *) (info->start[0]); - int prot, sect, l_sect; + int prot, sect; flash_dev_t *dev = NULL; if ((s_first < 0) || (s_first > s_last)) { @@ -803,17 +802,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Start erase on unprotected sectors */ dev = getFlashDevFromInfo (info); if (dev) { printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors); for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *) (dev->base); - /* printf("erase_sector: sector=%d, addr=0x%x\n", - sect, addr); */ printf ("."); if (ERROR == flashEraseSector (dev, sect)) { printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name); diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 61f031aab..81d7271a1 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -600,7 +600,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i, rcode = 0; @@ -632,8 +632,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -672,7 +670,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) rcode |= wait_for_DQ7(info, sect); } } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -691,16 +688,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) /* wait at least 80us - let's wait 1 ms */ udelay (1000); -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7(info, l_sect); - -DONE: -#endif /* reset to read mode */ addr = (FLASH_WORD_SIZE *)info->start[0]; addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index e93d99407..9d0db6446 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -246,8 +246,7 @@ int init_sdram (void) unsigned char trp_clocks, trcd_clocks, tras_clocks, - trc_clocks, - tctp_clocks; + trc_clocks; unsigned char cal_val; unsigned char bc; unsigned long sdram_tim, sdram_bank; @@ -345,7 +344,6 @@ int init_sdram (void) trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ @@ -626,10 +624,9 @@ phys_size_t initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; - int i, ds; + int i; unsigned long TotalSize; - ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); @@ -646,8 +643,7 @@ phys_size_t initdram (int board_type) tmp = (bank_reg[i] >> 17) & 0x7; bank_size = 4 << tmp; TotalSize += bank_size; - } else - ds = 1; + } } mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 7b48c0617..a1f0b656d 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -179,7 +179,6 @@ void write_4hex (unsigned long val) int board_early_init_f (void) { - unsigned char dataout[1]; unsigned char datain[128]; unsigned long sdram_size = 0; SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; @@ -189,9 +188,13 @@ int board_early_init_f (void) unsigned short i; unsigned char rows, cols, banks, sdram_banks, density; unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, - trc_clocks, tctp_clocks; + trc_clocks; unsigned char cal_index, cal_val, spd_version, spd_chksum; unsigned char buf[8]; +#ifdef SDRAM_DEBUG + unsigned char tctp_clocks; +#endif + /* set up the config port */ mtdcr (EBC0_CFGADDR, PB7AP); mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); @@ -210,7 +213,6 @@ int board_early_init_f (void) /* Read Serial Presence Detect Information */ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - dataout[0] = 0; for (i = 0; i < 128; i++) datain[i] = 127; i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); @@ -307,12 +309,13 @@ int board_early_init_f (void) /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; + +#ifdef SDRAM_DEBUG /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ tctp_clocks = ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + (tmemclk - 1)) / tmemclk; -#ifdef SDRAM_DEBUG serial_puts ("c_RP: "); write_hex (trp_clocks); serial_puts ("\nc_RCD: "); diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index e63625bf9..9f259c220 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -72,9 +72,6 @@ int board_early_init_f(void) int board_init(void) { - /* arch number of VCMA9-Board */ - gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; diff --git a/board/netta/codec.c b/board/netta/codec.c index c8d31d72e..e303aa478 100644 --- a/board/netta/codec.c +++ b/board/netta/codec.c @@ -1386,34 +1386,31 @@ static inline unsigned int s_transfer_internal(int s_id, unsigned int address, u static void s_write_BR(int s_id, unsigned int regno, unsigned int val) { unsigned int address; - unsigned int v; address = 0x70 | (regno & 15); val &= 0xff; - v = s_transfer_internal(s_id, address, val); + (void)s_transfer_internal(s_id, address, val); } static void s_write_OR(int s_id, unsigned int regno, unsigned int val) { unsigned int address; - unsigned int v; address = 0x70 | (regno & 15); val &= 0xff; - v = s_transfer_internal(s_id, address, val); + (void)s_transfer_internal(s_id, address, val); } static void s_write_NR(int s_id, unsigned int regno, unsigned int val) { unsigned int address; - unsigned int v; address = (regno & 7) << 4; val &= 0xf; - v = s_transfer_internal(s_id, address | val, 0x00); + (void)s_transfer_internal(s_id, address | val, 0x00); } #define BR7_IFR 0x08 /* IDL2 free run */ diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c index ed58f2c85..3fa1925f4 100644 --- a/board/netta/pcmcia.c +++ b/board/netta/pcmcia.c @@ -147,23 +147,16 @@ static void set_shdn(int what) static void cfg_ports (void) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; - - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); - - cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ cfg_vccd(0); cfg_vccd(1); /* 3V and 5V off */ cfg_shdn(); cfg_oc(); /* - * Configure Port A for TPS2211 PC-Card Power-Interface Switch - * - * Switch off all voltages, assert shutdown - */ + * Configure Port A for TPS2211 PC-Card Power-Interface Switch + * + * Switch off all voltages, assert shutdown + */ set_vppd(0, 1); set_vppd(1, 1); set_vccd(0, 0); set_vccd(1, 0); set_shdn(1); @@ -173,10 +166,7 @@ static void cfg_ports (void) int pcmcia_hardware_enable(int slot) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; - volatile sysconf8xx_t *sysp; uint reg, pipr, mask; int i; @@ -184,10 +174,7 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CONFIG_SYS_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ cfg_ports (); @@ -197,9 +184,9 @@ int pcmcia_hardware_enable(int slot) pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_); /* - * Disable interrupts, DMA, and PCMCIA buffers - * (isolate the interface) and assert RESET signal - */ + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -221,8 +208,8 @@ int pcmcia_hardware_enable(int slot) } /* - * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z - */ + * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z + */ mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); pipr = pcmp->pcmc_pipr; debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", @@ -267,15 +254,10 @@ int pcmcia_hardware_enable(int slot) #if defined(CONFIG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { - volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; u_long reg; debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - /* Configure PCMCIA General Control Register */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = 0; @@ -296,24 +278,19 @@ int pcmcia_hardware_disable(int slot) int pcmcia_voltage_set(int slot, int vcc, int vpp) { - volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; u_long reg; - ushort sreg; debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CONFIG_SYS_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* - * Disable PCMCIA buffers (isolate the interface) - * and assert RESET signal - */ + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ debug ("Disable PCMCIA buffers and assert RESET\n"); reg = PCMCIA_PGCRX(_slot_); reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ @@ -322,30 +299,29 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) udelay(500); /* - * Configure Port C pins for - * 5 Volts Enable and 3 Volts enable, - * Turn all power pins to Hi-Z - */ + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable, + * Turn all power pins to Hi-Z + */ debug ("PCMCIA power OFF\n"); cfg_ports (); /* Enables switch, but all in Hi-Z */ - sreg = immap->im_ioport.iop_pcdat; set_vppd(0, 1); set_vppd(1, 1); switch(vcc) { - case 0: - break; /* Switch off */ + case 0: + break; /* Switch off */ - case 33: - set_vccd(0, 1); set_vccd(1, 0); - break; + case 33: + set_vccd(0, 1); set_vccd(1, 0); + break; - case 50: - set_vccd(0, 0); set_vccd(1, 1); - break; + case 50: + set_vccd(0, 0); set_vccd(1, 1); + break; - default: - goto done; + default: + goto done; } /* Checking supported voltages */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index d13537d16..370a25906 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -102,16 +102,6 @@ static void pin_mux_uart(void) #ifdef CONFIG_TEGRA2_MMC /* - * Routine: clock_init_mmc - * Description: init the PLL and clocks for the SDMMC controllers - */ -static void clock_init_mmc(void) -{ - clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000); - clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000); -} - -/* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) */ @@ -157,8 +147,7 @@ int board_init(void) int board_mmc_init(bd_t *bd) { debug("board_mmc_init called\n"); - /* Enable clocks, muxes, etc. for SDMMC controllers */ - clock_init_mmc(); + /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); gpio_config_mmc(); diff --git a/board/pm520/flash.c b/board/pm520/flash.c index 64c862415..01dcd560c 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -370,7 +370,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) int flash_erase (flash_info_t *info, int s_first, int s_last) { int flag, prot, sect; - ulong type, start, last; + ulong type, start; int rcode = 0; if ((s_first < 0) || (s_first > s_last)) { @@ -404,7 +404,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } start = get_timer (0); - last = start; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -440,6 +439,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf (" done\n"); } } + + if (flag) + enable_interrupts(); + return rcode; } @@ -543,6 +546,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) ulong status; ulong start; int flag; + int rcode = 0; /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { @@ -561,14 +565,17 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); + rcode = 1; + break; } } *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); + if (flag) + enable_interrupts(); + + return rcode; } void inline spin_wheel (void) diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c index fac7633b7..15b3bfc08 100644 --- a/board/prodrive/p3mx/mv_eth.c +++ b/board/prodrive/p3mx/mv_eth.c @@ -468,7 +468,6 @@ static int mv64460_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; unsigned int port_num; - u32 port_status; ushort reg_short; int speed; int duplex; @@ -569,7 +568,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) */ MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); #if defined(CONFIG_PHY_RESET) /* @@ -717,15 +716,6 @@ static int mv64460_eth_free_rx_rings (struct eth_device *dev) int mv64460_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -793,7 +783,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -802,7 +791,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; @@ -874,13 +862,11 @@ int mv64460_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == ETH_OK)) { @@ -976,12 +962,10 @@ static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; mv64460_eth_update_stat (dev); @@ -1002,13 +986,10 @@ static void mv64460_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -1031,12 +1012,12 @@ static void mv64460_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + (void)eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + (void)eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1084,12 +1065,10 @@ static void mv64460_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -2138,13 +2117,13 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy; /* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; - i += 4) - dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE + i += 4) { + (void)MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num) + i)); + } return; } diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c index 85da41bd2..a939b31d4 100644 --- a/board/r360mpi/pcmcia.c +++ b/board/r360mpi/pcmcia.c @@ -19,7 +19,6 @@ int pcmcia_hardware_enable(int slot) { volatile immap_t *immap; - volatile cpm8xx_t *cp; volatile pcmconf8xx_t *pcmp; volatile sysconf8xx_t *sysp; uint reg, mask; @@ -31,7 +30,6 @@ int pcmcia_hardware_enable(int slot) immap = (immap_t *)CONFIG_SYS_IMMR; sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure SIUMCR to enable PCMCIA port B @@ -127,13 +125,11 @@ int pcmcia_hardware_enable(int slot) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; - volatile pcmconf8xx_t *pcmp; u_long reg; debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); immap = (immap_t *)CONFIG_SYS_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* remove all power */ immap->im_ioport.iop_pcdat |= 0x0400; diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c index cb1e089f3..6be2bc92f 100644 --- a/board/rbc823/flash.c +++ b/board/rbc823/flash.c @@ -24,32 +24,30 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -/*----------------------------------------------------------------------- +/* * Functions */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ +static ulong flash_get_size(vu_long *addr, flash_info_t *info); +static int write_word(flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets(ulong base, flash_info_t *info); -unsigned long flash_init (void) +unsigned long flash_init(void) { - unsigned long size_b0, size_b1; + unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) - flash_info[i].flash_id = FLASH_UNKNOWN; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; /* Detect size */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, + &flash_info[0]); /* Setup offsets */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* Monitor protection ON by default */ @@ -59,21 +57,15 @@ unsigned long flash_init (void) &flash_info[0]); #endif - size_b1 = 0 ; - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - return (size_b0 + size_b1); + return size_b0; } /*----------------------------------------------------------------------- * Fix this to support variable sector sizes */ -static void flash_get_offsets (ulong base, flash_info_t *info) +static void flash_get_offsets(ulong base, flash_info_t *info) { int i; @@ -87,83 +79,93 @@ static void flash_get_offsets (ulong base, flash_info_t *info) /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t *info) +void flash_print_info(flash_info_t *info) { int i; - if (info->flash_id == FLASH_UNKNOWN) - { - puts ("missing or unknown FLASH type\n"); + if (info->flash_id == FLASH_UNKNOWN) { + puts("missing or unknown FLASH type\n"); return; } - switch (info->flash_id & FLASH_VENDMASK) - { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - default: printf ("Unknown Vendor "); break; + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_BM: + printf("BRIGHT MICRO "); + break; + default: + printf("Unknown Vendor "); + break; } - switch (info->flash_id & FLASH_TYPEMASK) - { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } if (info->size >> 20) { - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); } else { - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, - info->sector_count); + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, + info->sector_count); } - puts (" Sector Start Addresses:"); + puts(" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) - { + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - { - puts ("\n "); - } + puts("\n "); - printf (" %08lX%s", + printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); } - putc ('\n'); + putc('\n'); return; } -/*----------------------------------------------------------------------- - */ /* * The following code cannot be run from FLASH! */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) +static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; volatile unsigned char *caddr; @@ -173,9 +175,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ -#if 0 - printf("Base address is: %08x\n", caddr); -#endif + debug("Base address is: %8p\n", caddr); caddr[0x0555] = 0xAA; caddr[0x02AA] = 0x55; @@ -183,51 +183,49 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = caddr[0]; -#if 0 - printf("Manufact ID: %02x\n", value); -#endif - switch (value) - { - case 0x01: /*AMD_MANUFACT*/ - info->flash_id = FLASH_MAN_AMD; + debug("Manufact ID: %02x\n", value); + + switch (value) { + case 0x01: /*AMD_MANUFACT*/ + info->flash_id = FLASH_MAN_AMD; break; - case 0x04: /*FUJ_MANUFACT*/ - info->flash_id = FLASH_MAN_FUJ; + case 0x04: /*FUJ_MANUFACT*/ + info->flash_id = FLASH_MAN_FUJ; break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; } value = caddr[1]; /* device ID */ -#if 0 - printf("Device ID: %02x\n", value); -#endif - switch (value) - { - case AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512Kb */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + debug("Device ID: %02x\n", value); + + switch (value) { + case AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; + break; /* => 512Kb */ + + default: + info->flash_id = FLASH_UNKNOWN; + return 0; /* => no or unknown flash */ } - flash_get_offsets ((ulong)addr, &flash_info[0]); + flash_get_offsets((ulong)addr, &flash_info[0]); /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) - { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ + for (i = 0; i < info->sector_count; i++) { + /* + * read sector protection at sector address, + * (A7 .. A0) = 0x02 + * D0 = 1 if protected + */ caddr = (volatile unsigned char *)(info->start[i]); info->protect[i] = caddr[2] & 1; } @@ -235,52 +233,48 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) /* * Prevent writes to uninitialized FLASH. */ - if (info->flash_id != FLASH_UNKNOWN) - { + if (info->flash_id != FLASH_UNKNOWN) { caddr = (volatile unsigned char *)info->start[0]; *caddr = 0xF0; /* reset bank */ } - return (info->size); + return info->size; } -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); int flag, prot, sect, l_sect; ulong start, now, last; if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; } if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type - aborted\n"); + printf("Can't erase unknown flash type - aborted\n"); return 1; } prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } l_sect = -1; @@ -295,7 +289,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[0x02AA] = 0x55; /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr = (volatile unsigned char *)(info->start[sect]); addr[0] = 0x30; @@ -308,7 +302,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); /* * We wait for the last triggered sector @@ -316,19 +310,19 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - start = get_timer (0); + start = get_timer(0); last = start; addr = (volatile unsigned char *)(info->start[l_sect]); - while ((addr[0] & 0xFF) != 0xFF) - { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + while ((addr[0] & 0xFF) != 0xFF) { + now = get_timer(start); + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ - putc ('.'); + putc('.'); last = now; } } @@ -339,18 +333,18 @@ DONE: addr[0] = 0xF0; /* reset bank */ - printf (" done\n"); + printf(" done\n"); return 0; } -/*----------------------------------------------------------------------- +/* * Copy memory to flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; @@ -360,23 +354,27 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { + for (i = 0, cp = wp; i < l; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { + + for (; cnt == 0 && i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; } @@ -385,45 +383,46 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { + for (; i < 4; ++i, ++cp) data = (data << 8) | (*(uchar *)cp); - } - return (write_word(info, wp, data)); + return write_word(info, wp, data); } -/*----------------------------------------------------------------------- +/* * Write a word to Flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]), - *cdest,*cdata; + volatile unsigned char *cdest, *cdata; + volatile unsigned char *addr = + (volatile unsigned char *)(info->start[0]); ulong start; int flag, count = 4 ; @@ -431,39 +430,32 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) cdata = (volatile unsigned char *)&data ; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } + if ((*((vu_long *)dest)&data) != data) + return 2; - while(count--) - { - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); + while (count--) { + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); - addr[0x0555] = 0xAA; - addr[0x02AA] = 0x55; - addr[0x0555] = 0xA0; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; - *cdest = *cdata; + *cdest = *cdata; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - while ((*cdest ^ *cdata) & 0x80) - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); + /* data polling for D7 */ + start = get_timer(0); + while ((*cdest ^ *cdata) & 0x80) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } - } - cdata++ ; - cdest++ ; + cdata++ ; + cdest++ ; } - return (0); + return 0; } - -/*----------------------------------------------------------------------- - */ diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 871b94ada..b26e33a65 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -248,9 +248,6 @@ int board_init(void) 1 << ATMEL_ID_PIOC, &pmc->pcer); - /* arch number of PM9261-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PM9261; - /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index cfc9847cc..b0f7ea6dd 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -349,9 +349,6 @@ int board_init(void) (1 << ATMEL_ID_PIOB), &pmc->pcer); - /* arch number of AT91SAM9263EK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PM9263; - /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index f3374a442..961d193fd 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -139,8 +139,6 @@ int board_init(void) (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIODE), &pmc->pcer); - /* arch number of AT91SAM9M10G45EK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PM9G45; /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c index be29b65cf..70ae1d2ff 100644 --- a/board/rpxsuper/flash.c +++ b/board/rpxsuper/flash.c @@ -47,41 +47,39 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { - unsigned long size; - int i; + int i; - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } + /* Init: no FLASHes known */ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) + flash_info[i].flash_id = FLASH_UNKNOWN; - /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); + /* for now, only support the 4 MB Flash SIMM */ + (void)flash_get_size((vu_long *) CONFIG_SYS_FLASH0_BASE, + &flash_info[0]); - /* - * protect monitor and environment sectors - */ + /* + * protect monitor and environment sectors + */ #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); +#ifndef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif - return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); + return CONFIG_SYS_FLASH0_SIZE * 1024 * 1024; } /*----------------------------------------------------------------------- diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c index 61cab8703..536d7de0e 100644 --- a/board/sacsng/sacsng.c +++ b/board/sacsng/sacsng.c @@ -39,7 +39,7 @@ extern void eth_loopback_test(void); #endif /* CONFIG_ETHER_LOOPBACK_TEST */ #include "clkinit.h" -#include "ioconfig.h" /* I/O configuration table */ +#include "ioconfig.h" /* I/O configuration table */ /* * PBI Page Based Interleaving @@ -61,88 +61,86 @@ extern void eth_loopback_test(void); /* * ADC/DAC Defines: */ -#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ -#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ -#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ -#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ -#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ +#define INITIAL_SAMPLE_RATE 10016 /* Initial Daq sample rate */ +#define INITIAL_RIGHT_JUST 0 /* Initial DAC right justification */ +#define INITIAL_MCLK_DIVIDE 0 /* Initial MCLK Divide */ +#define INITIAL_SAMPLE_64X 1 /* Initial 64x clocking mode */ +#define INITIAL_SAMPLE_128X 0 /* Initial 128x clocking mode */ /* * ADC Defines: */ -#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ -#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ +#define I2C_ADC_1_ADDR 0x0E /* I2C Address of the ADC #1 */ +#define I2C_ADC_2_ADDR 0x0F /* I2C Address of the ADC #2 */ -#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ -#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ +#define ADC_SDATA1_MASK 0x00020000 /* PA14 - CH12SDATA_PU */ +#define ADC_SDATA2_MASK 0x00010000 /* PA15 - CH34SDATA_PU */ -#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ -#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ -#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ +#define ADC_VREF_CAP 100 /* VREF capacitor in uF */ +#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */ +#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */ #define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500) - /* Wait at least 4100 LRCLK's */ - -#define ADC_REG1_FRAME_START 0x80 /* Frame start */ -#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ -#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ -#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ - -#define ADC_REG2_128x 0x80 /* Oversample at 128x */ -#define ADC_REG2_CAL 0x40 /* System calibration enable */ -#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ -#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ -#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ -#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ -#define ADC_REG2_DFS 0x02 /* Digital format select */ -#define ADC_REG2_MUTE 0x01 /* Mute */ - -#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ -#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ -#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ -#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ -#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ -#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ -#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ + /* Wait at least 4100 LRCLK's */ + +#define ADC_REG1_FRAME_START 0x80 /* Frame start */ +#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */ +#define ADC_REG1_ANA_MOD_PDOWN 0x20 /* Analog modulator section in power down */ +#define ADC_REG1_DIG_MOD_PDOWN 0x10 /* Digital modulator section in power down */ + +#define ADC_REG2_128x 0x80 /* Oversample at 128x */ +#define ADC_REG2_CAL 0x40 /* System calibration enable */ +#define ADC_REG2_CHANGE_SIGN 0x20 /* Change sign enable */ +#define ADC_REG2_LR_DISABLE 0x10 /* Left/Right output disable */ +#define ADC_REG2_HIGH_PASS_DIS 0x08 /* High pass filter disable */ +#define ADC_REG2_SLAVE_MODE 0x04 /* Slave mode */ +#define ADC_REG2_DFS 0x02 /* Digital format select */ +#define ADC_REG2_MUTE 0x01 /* Mute */ + +#define ADC_REG7_ADDR_ENABLE 0x80 /* Address enable */ +#define ADC_REG7_PEAK_ENABLE 0x40 /* Peak enable */ +#define ADC_REG7_PEAK_UPDATE 0x20 /* Peak update */ +#define ADC_REG7_PEAK_FORMAT 0x10 /* Peak display format */ +#define ADC_REG7_DIG_FILT_PDOWN 0x04 /* Digital filter power down enable */ +#define ADC_REG7_FIR2_IN_EN 0x02 /* External FIR2 input enable */ +#define ADC_REG7_PSYCHO_EN 0x01 /* External pyscho filter input enable */ /* * DAC Defines: */ -#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ +#define I2C_DAC_ADDR 0x11 /* I2C Address of the DAC */ -#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ -#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ -#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ +#define DAC_RST_MASK 0x00008000 /* PA16 - DAC_RST* */ +#define DAC_RESET_DELAY 100 /* DAC reset delay in usec */ +#define DAC_INITIAL_DELAY 5000 /* DAC initialization delay in usec */ -#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ +#define DAC_REG1_AMUTE 0x80 /* Auto-mute */ -#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ -#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ -#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ -#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ -#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ -#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ +#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit */ +#define DAC_REG1_I2S_24_BIT (1 << 4) /* Fmt 1: I2S up to 24 bit */ +#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */ +#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */ +#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */ +#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */ -#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ -#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ -#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ -#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ +#define DAC_REG1_DEM_NO (0 << 2) /* No De-emphasis */ +#define DAC_REG1_DEM_44KHZ (1 << 2) /* 44.1KHz De-emphasis */ +#define DAC_REG1_DEM_48KHZ (2 << 2) /* 48KHz De-emphasis */ +#define DAC_REG1_DEM_32KHZ (3 << 2) /* 32KHz De-emphasis */ -#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ -#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ -#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ -#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ +#define DAC_REG1_SINGLE 0 /* 4- 50KHz sample rate */ +#define DAC_REG1_DOUBLE 1 /* 50-100KHz sample rate */ +#define DAC_REG1_QUAD 2 /* 100-200KHz sample rate */ +#define DAC_REG1_DSD 3 /* Direct Stream Data, DSD */ -#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ -#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ -#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ -#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ -#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ -#define DAC_REG5_FREEZE 0x04 /* Freeze */ -#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ -#define DAC_REG5_RESERVED 0x01 /* Reserved */ - -/* ------------------------------------------------------------------------- */ +#define DAC_REG5_INVERT_A 0x80 /* Invert channel A */ +#define DAC_REG5_INVERT_B 0x40 /* Invert channel B */ +#define DAC_REG5_I2C_MODE 0x20 /* Control port (I2C) mode */ +#define DAC_REG5_POWER_DOWN 0x10 /* Power down mode */ +#define DAC_REG5_MUTEC_A_B 0x08 /* Mutec A=B */ +#define DAC_REG5_FREEZE 0x04 /* Freeze */ +#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */ +#define DAC_REG5_RESERVED 0x01 /* Reserved */ /* * Check Board Identity: @@ -150,290 +148,297 @@ extern void eth_loopback_test(void); int checkboard(void) { - printf ("SACSng\n"); + printf("SACSng\n"); - return 0; + return 0; } -/* ------------------------------------------------------------------------- */ - phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); - uint psdmr = CONFIG_SYS_PSDMR; - int i; - uint psrt = 14; /* for no SPD */ - uint chipselects = 1; /* for no SPD */ - uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0; + volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); + uint psdmr = CONFIG_SYS_PSDMR; + int i; + uint psrt = 14; /* for no SPD */ + uint chipselects = 1; /* for no SPD */ + uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ + #ifdef SDRAM_SPD_ADDR - uint data_width; - uint rows; - uint banks; - uint cols; - uint caslatency; - uint width; - uint rowst; - uint sdam; - uint bsma; - uint sda10; - u_char spd_size; - u_char data; - u_char cksum; - int j; + uint data_width; + uint rows; + uint banks; + uint cols; + uint caslatency; + uint width; + uint rowst; + uint sdam; + uint bsma; + uint sda10; + u_char data; + u_char cksum; + int j; #endif #ifdef SDRAM_SPD_ADDR - /* Keep the compiler from complaining about potentially uninitialized vars */ - data_width = chipselects = rows = banks = cols = caslatency = psrt = 0; - - /* - * Read the SDRAM SPD EEPROM via I2C. - */ - i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); - spd_size = data; - cksum = data; - for(j = 1; j < 64; j++) { /* read only the checksummed bytes */ - /* note: the I2C address autoincrements when alen == 0 */ - i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); - if(j == 5) chipselects = data & 0x0F; - else if(j == 6) data_width = data; - else if(j == 7) data_width |= data << 8; - else if(j == 3) rows = data & 0x0F; - else if(j == 4) cols = data & 0x0F; - else if(j == 12) { - /* - * Refresh rate: this assumes the prescaler is set to - * approximately 1uSec per tick. - */ - switch(data & 0x7F) { - default: - case 0: psrt = 14 ; /* 15.625uS */ break; - case 1: psrt = 2; /* 3.9uS */ break; - case 2: psrt = 6; /* 7.8uS */ break; - case 3: psrt = 29; /* 31.3uS */ break; - case 4: psrt = 60; /* 62.5uS */ break; - case 5: psrt = 120; /* 125uS */ break; - } - } - else if(j == 17) banks = data; - else if(j == 18) { - caslatency = 3; /* default CL */ + /* Keep the compiler from complaining about potentially uninitialized vars */ + data_width = chipselects = rows = banks = cols = caslatency = psrt = + 0; + + /* + * Read the SDRAM SPD EEPROM via I2C. + */ + i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); + cksum = data; + for (j = 1; j < 64; j++) { /* read only the checksummed bytes */ + /* note: the I2C address autoincrements when alen == 0 */ + i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); + if (j == 5) + chipselects = data & 0x0F; + else if (j == 6) + data_width = data; + else if (j == 7) + data_width |= data << 8; + else if (j == 3) + rows = data & 0x0F; + else if (j == 4) + cols = data & 0x0F; + else if (j == 12) { + /* + * Refresh rate: this assumes the prescaler is set to + * approximately 1uSec per tick. + */ + switch (data & 0x7F) { + default: + case 0: + psrt = 14; /* 15.625uS */ + break; + case 1: + psrt = 2; /* 3.9uS */ + break; + case 2: + psrt = 6; /* 7.8uS */ + break; + case 3: + psrt = 29; /* 31.3uS */ + break; + case 4: + psrt = 60; /* 62.5uS */ + break; + case 5: + psrt = 120; /* 125uS */ + break; + } + } else if (j == 17) + banks = data; + else if (j == 18) { + caslatency = 3; /* default CL */ #if(PESSIMISTIC_SDRAM) - if((data & 0x04) != 0) caslatency = 3; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x01) != 0) caslatency = 1; + if ((data & 0x04) != 0) + caslatency = 3; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x01) != 0) + caslatency = 1; #else - if((data & 0x01) != 0) caslatency = 1; - else if((data & 0x02) != 0) caslatency = 2; - else if((data & 0x04) != 0) caslatency = 3; + if ((data & 0x01) != 0) + caslatency = 1; + else if ((data & 0x02) != 0) + caslatency = 2; + else if ((data & 0x04) != 0) + caslatency = 3; #endif - else { - printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", - data); - } + else { + printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data); + } + } else if (j == 63) { + if (data != cksum) { + printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum); + } + } + cksum += data; } - else if(j == 63) { - if(data != cksum) { - printf ("WARNING: Configuration data checksum failure:" - " is 0x%02x, calculated 0x%02x\n", - data, cksum); - } + + /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ + if (caslatency < 2) { + printf("WARNING: CL was %d, forcing to 2\n", caslatency); + caslatency = 2; + } + if (rows > 14) { + printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", + rows); + rows = 14; + } + if (cols > 11) { + printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", + cols); + cols = 11; + } + + if ((data_width != 64) && (data_width != 72)) { + printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", + data_width); } - cksum += data; - } - - /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ - if(caslatency < 2) { - printf("WARNING: CL was %d, forcing to 2\n", caslatency); - caslatency = 2; - } - if(rows > 14) { - printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows); - rows = 14; - } - if(cols > 11) { - printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols); - cols = 11; - } - - if((data_width != 64) && (data_width != 72)) - { - printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", - data_width); - } - width = 3; /* 2^3 = 8 bytes = 64 bits wide */ - /* - * Convert banks into log2(banks) - */ - if (banks == 2) banks = 1; - else if(banks == 4) banks = 2; - else if(banks == 8) banks = 3; - - sdram_size = 1 << (rows + cols + banks + width); - -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - rowst = ((32 - 6) - (rows + cols + width)) * 2; + width = 3; /* 2^3 = 8 bytes = 64 bits wide */ + /* + * Convert banks into log2(banks) + */ + if (banks == 2) + banks = 1; + else if (banks == 4) + banks = 2; + else if (banks == 8) + banks = 3; + + sdram_size = 1 << (rows + cols + banks + width); + +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + rowst = ((32 - 6) - (rows + cols + width)) * 2; #else - rowst = 32 - (rows + banks + cols + width); + rowst = 32 - (rows + banks + cols + width); #endif - or = ~(sdram_size - 1) | /* SDAM address mask */ - ((banks-1) << 13) | /* banks per device */ - (rowst << 9) | /* rowst */ - ((rows - 9) << 6); /* numr */ - - memctl->memc_or2 = or; - - /* - * SDAM specifies the number of columns that are multiplexed - * (reference AN2165/D), defined to be (columns - 6) for page - * interleave, (columns - 8) for bank interleave. - * - * BSMA is 14 - max(rows, cols). The bank select lines come - * into play above the highest "address" line going into the - * the SDRAM. - */ -#if(CONFIG_PBI == 0) /* bank-based interleaving */ - sdam = cols - 8; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam + 2; + or = ~(sdram_size - 1) | /* SDAM address mask */ + ((banks - 1) << 13) | /* banks per device */ + (rowst << 9) | /* rowst */ + ((rows - 9) << 6); /* numr */ + + memctl->memc_or2 = or; + + /* + * SDAM specifies the number of columns that are multiplexed + * (reference AN2165/D), defined to be (columns - 6) for page + * interleave, (columns - 8) for bank interleave. + * + * BSMA is 14 - max(rows, cols). The bank select lines come + * into play above the highest "address" line going into the + * the SDRAM. + */ +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + sdam = cols - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam + 2; #else - sdam = cols - 6; - bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); - sda10 = sdam; + sdam = cols - 6; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam; #endif #if(PESSIMISTIC_SDRAM) - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_16_CLK |\ - PSDMR_PRETOACT_8W |\ - PSDMR_ACTTORW_8W |\ - PSDMR_WRC_4C |\ - PSDMR_EAMUX |\ - PSDMR_BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK | + PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C | + PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency | + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #else - psdmr = (CONFIG_PBI |\ - PSDMR_RFEN |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ - PSDMR_WRC_1C | /* 1 clock + 7nSec */ - EAMUX |\ - BUFCMD) |\ - caslatency |\ - ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ - (sdam << 24) |\ - (bsma << 21) |\ - (sda10 << 18); + psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK | + PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ + PSDMR_WRC_1C | /* 1 clock + 7nSec */ + EAMUX | BUFCMD) | + caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ + (sdam << 24) | (bsma << 21) | (sda10 << 18); #endif #endif - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * Quote from Micron MT48LC8M16A2 data sheet: - * - * "...the SDRAM requires a 100uS delay prior to issuing any - * command other than a COMMAND INHIBIT or NOP. Starting at some - * point during this 100uS period and continuing at least through - * the end of this period, COMMAND INHIBIT or NOP commands should - * be applied." - * - * "Once the 100uS delay has been satisfied with at least one COMMAND - * INHIBIT or NOP command having been applied, a /PRECHARGE command/ - * should be applied. All banks must then be precharged, thereby - * placing the device in the all banks idle state." - * - * "Once in the idle state, /two/ AUTO REFRESH cycles must be - * performed. After the AUTO REFRESH cycles are complete, the - * SDRAM is ready for mode register programming." - * - * (/emphasis/ mine, gvb) - * - * The way I interpret this, Micron start up sequence is: - * 1. Issue a PRECHARGE-BANK command (initial precharge) - * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") - * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands - * 4. Issue a MODE-SET command to initialize the mode register - * - * -------- - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. - */ - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psrt = psrt; - - memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - *ramaddr = c; - - memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *ramaddr = c; - - /* - * Do it a second time for the second set of chips if the DIMM has - * two chip selects (double sided). - */ - if(chipselects > 1) { - ramaddr += sdram_size; + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * Quote from Micron MT48LC8M16A2 data sheet: + * + * "...the SDRAM requires a 100uS delay prior to issuing any + * command other than a COMMAND INHIBIT or NOP. Starting at some + * point during this 100uS period and continuing at least through + * the end of this period, COMMAND INHIBIT or NOP commands should + * be applied." + * + * "Once the 100uS delay has been satisfied with at least one COMMAND + * INHIBIT or NOP command having been applied, a /PRECHARGE command/ + * should be applied. All banks must then be precharged, thereby + * placing the device in the all banks idle state." + * + * "Once in the idle state, /two/ AUTO REFRESH cycles must be + * performed. After the AUTO REFRESH cycles are complete, the + * SDRAM is ready for mode register programming." + * + * (/emphasis/ mine, gvb) + * + * The way I interpret this, Micron start up sequence is: + * 1. Issue a PRECHARGE-BANK command (initial precharge) + * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") + * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands + * 4. Issue a MODE-SET command to initialize the mode register + * + * -------- + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. + */ - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; - memctl->memc_or3 = or; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = psrt; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) - *ramaddr = c; + *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; - } - /* return total ram size */ - return (sdram_size * chipselects); + /* + * Do it a second time for the second set of chips if the DIMM has + * two chip selects (double sided). + */ + if (chipselects > 1) { + ramaddr += sdram_size; + + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; + memctl->memc_or3 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + } + + /* return total ram size */ + return (sdram_size * chipselects); } /*----------------------------------------------------------------------- * Board Control Functions */ -void board_poweroff (void) +void board_poweroff(void) { - while (1); /* hang forever */ + while (1); /* hang forever */ } @@ -441,301 +446,288 @@ void board_poweroff (void) /* ------------------------------------------------------------------------- */ int misc_init_r(void) { - /* - * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. - */ - volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */); - volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); - - int reg; /* I2C register value */ - char *ep; /* Environment pointer */ - char str_buf[12] ; /* sprintf output buffer */ - int sample_rate; /* ADC/DAC sample rate */ - int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ - int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ - int right_just; /* Is the data to the DAC right justified? */ - int mclk_divide; /* MCLK Divide */ - int quiet; /* Quiet or minimal output mode */ - - quiet = 0; - if ((ep = getenv("quiet")) != NULL) { - quiet = simple_strtol(ep, NULL, 10); - } - else { - setenv("quiet", "0"); - } - - /* - * SACSng custom initialization: - * Start the ADC and DAC clocks, since the Crystal parts do not - * work on the I2C bus until the clocks are running. - */ - - sample_rate = INITIAL_SAMPLE_RATE; - if ((ep = getenv("DaqSampleRate")) != NULL) { - sample_rate = simple_strtol(ep, NULL, 10); - } - - sample_64x = INITIAL_SAMPLE_64X; - sample_128x = INITIAL_SAMPLE_128X; - if ((ep = getenv("Daq64xSampling")) != NULL) { - sample_64x = simple_strtol(ep, NULL, 10); + /* + * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. + */ + volatile ioport_t *iopa = + ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ ); + volatile ioport_t *iop = + ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); + + int reg; /* I2C register value */ + char *ep; /* Environment pointer */ + char str_buf[12]; /* sprintf output buffer */ + int sample_rate; /* ADC/DAC sample rate */ + int sample_64x; /* Use 64/4 clocking for the ADC/DAC */ + int sample_128x; /* Use 128/4 clocking for the ADC/DAC */ + int right_just; /* Is the data to the DAC right justified? */ + int mclk_divide; /* MCLK Divide */ + int quiet; /* Quiet or minimal output mode */ + + quiet = 0; + + if ((ep = getenv("quiet")) != NULL) + quiet = simple_strtol(ep, NULL, 10); + else + setenv("quiet", "0"); + + /* + * SACSng custom initialization: + * Start the ADC and DAC clocks, since the Crystal parts do not + * work on the I2C bus until the clocks are running. + */ + + sample_rate = INITIAL_SAMPLE_RATE; + if ((ep = getenv("DaqSampleRate")) != NULL) + sample_rate = simple_strtol(ep, NULL, 10); + + sample_64x = INITIAL_SAMPLE_64X; + sample_128x = INITIAL_SAMPLE_128X; + if ((ep = getenv("Daq64xSampling")) != NULL) { + sample_64x = simple_strtol(ep, NULL, 10); + if (sample_64x) + sample_128x = 0; + else + sample_128x = 1; + } else { + if ((ep = getenv("Daq128xSampling")) != NULL) { + sample_128x = simple_strtol(ep, NULL, 10); + if (sample_128x) + sample_64x = 0; + else + sample_64x = 1; + } + } + + /* + * Stop the clocks and wait for at least 1 LRCLK period + * to make sure the clocking has really stopped. + */ + Daq_Stop_Clocks(); + udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); + + /* + * Initialize the clocks with the new rates + */ + Daq_Init_Clocks(sample_rate, sample_64x); + sample_rate = Daq_Get_SampleRate(); + + /* + * Start the clocks and wait for at least 1 LRCLK period + * to make sure the clocking has become stable. + */ + Daq_Start_Clocks(sample_rate); + udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); + + sprintf(str_buf, "%d", sample_rate); + setenv("DaqSampleRate", str_buf); + if (sample_64x) { - sample_128x = 0; + setenv("Daq64xSampling", "1"); + setenv("Daq128xSampling", NULL); + } else { + setenv("Daq64xSampling", NULL); + setenv("Daq128xSampling", "1"); } - else { - sample_128x = 1; + + /* + * Display the ADC/DAC clocking information + */ + if (!quiet) + Daq_Display_Clocks(); + + /* + * Determine the DAC data justification + */ + + right_just = INITIAL_RIGHT_JUST; + if ((ep = getenv("DaqDACRightJustified")) != NULL) + right_just = simple_strtol(ep, NULL, 10); + + sprintf(str_buf, "%d", right_just); + setenv("DaqDACRightJustified", str_buf); + + /* + * Determine the DAC MCLK Divide + */ + + mclk_divide = INITIAL_MCLK_DIVIDE; + if ((ep = getenv("DaqDACMClockDivide")) != NULL) + mclk_divide = simple_strtol(ep, NULL, 10); + + sprintf(str_buf, "%d", mclk_divide); + setenv("DaqDACMClockDivide", str_buf); + + /* + * Initializing the I2C address in the Crystal A/Ds: + * + * 1) Wait for VREF cap to settle (10uSec per uF) + * 2) Release pullup on SDATA + * 3) Write the I2C address to register 6 + * 4) Enable address matching by setting the MSB in register 7 + */ + + if (!quiet) + printf("Initializing the ADC...\n"); + + udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ + + iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ + udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ + + i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ + i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ + ADC_REG7_ADDR_ENABLE); + + i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); + + reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; + if (reg != I2C_ADC_1_ADDR) { + printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", + reg, I2C_ADC_1_ADDR); } - } - else { - if ((ep = getenv("Daq128xSampling")) != NULL) { - sample_128x = simple_strtol(ep, NULL, 10); - if (sample_128x) { - sample_64x = 0; - } - else { - sample_64x = 1; - } + + iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ + udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ + + /* set address (do not set ADDREN yet) */ + i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); + + i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); + + reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; + if (reg != I2C_ADC_2_ADDR) { + printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", + reg, I2C_ADC_2_ADDR); } - } - - /* - * Stop the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has really stopped. - */ - Daq_Stop_Clocks(); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - /* - * Initialize the clocks with the new rates - */ - Daq_Init_Clocks(sample_rate, sample_64x); - sample_rate = Daq_Get_SampleRate(); - - /* - * Start the clocks and wait for at least 1 LRCLK period - * to make sure the clocking has become stable. - */ - Daq_Start_Clocks(sample_rate); - udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE); - - sprintf(str_buf, "%d", sample_rate); - setenv("DaqSampleRate", str_buf); - - if (sample_64x) { - setenv("Daq64xSampling", "1"); - setenv("Daq128xSampling", NULL); - } - else { - setenv("Daq64xSampling", NULL); - setenv("Daq128xSampling", "1"); - } - - /* - * Display the ADC/DAC clocking information - */ - if (!quiet) { - Daq_Display_Clocks(); - } - - /* - * Determine the DAC data justification - */ - - right_just = INITIAL_RIGHT_JUST; - if ((ep = getenv("DaqDACRightJustified")) != NULL) { - right_just = simple_strtol(ep, NULL, 10); - } - - sprintf(str_buf, "%d", right_just); - setenv("DaqDACRightJustified", str_buf); - - /* - * Determine the DAC MCLK Divide - */ - - mclk_divide = INITIAL_MCLK_DIVIDE; - if ((ep = getenv("DaqDACMClockDivide")) != NULL) { - mclk_divide = simple_strtol(ep, NULL, 10); - } - - sprintf(str_buf, "%d", mclk_divide); - setenv("DaqDACMClockDivide", str_buf); - - /* - * Initializing the I2C address in the Crystal A/Ds: - * - * 1) Wait for VREF cap to settle (10uSec per uF) - * 2) Release pullup on SDATA - * 3) Write the I2C address to register 6 - * 4) Enable address matching by setting the MSB in register 7 - */ - - if (!quiet) { - printf("Initializing the ADC...\n"); - } - udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */ - - iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */ - ADC_REG7_ADDR_ENABLE); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F; - if(reg != I2C_ADC_1_ADDR) - printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_1_ADDR); - - iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */ - udelay(ADC_SDATA_DELAY); /* arbitrary settling time */ - - i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */ - - i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F; - if(reg != I2C_ADC_2_ADDR) - printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n", - reg, I2C_ADC_2_ADDR); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ - ADC_REG1_FRAME_START | - ADC_REG1_GROUND_CAL); - - i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ - (sample_64x ? 0 : ADC_REG2_128x) | - ADC_REG2_CAL | - ADC_REG2_HIGH_PASS_DIS | - ADC_REG2_SLAVE_MODE); - - udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ - i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ - - /* - * Now that we have synchronized the ADC's, enable address - * selection on the second ADC as well as the first. - */ - i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); - - /* - * Initialize the Crystal DAC - * - * Two of the config lines are used for I2C so we have to set them - * to the proper initialization state without inadvertantly - * sending an I2C "start" sequence. When we bring the I2C back to - * the normal state, we send an I2C "stop" sequence. - */ - if (!quiet) { - printf("Initializing the DAC...\n"); - } - - /* - * Bring the I2C clock and data lines low for initialization - */ - I2C_SCL(0); - I2C_DELAY; - I2C_SDA(0); - I2C_ACTIVE; - I2C_DELAY; - - /* Reset the DAC */ - iopa->pdat &= ~DAC_RST_MASK; - udelay(DAC_RESET_DELAY); - - /* Release the DAC reset */ - iopa->pdat |= DAC_RST_MASK; - udelay(DAC_INITIAL_DELAY); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Going into power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - DAC_REG5_POWER_DOWN | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Cause the DAC to: - * Auto-mute disabled - * . Format 0, left justified 24 bits - * . Format 3, right justified 24 bits - * No de-emphasis - * . Single speed mode - * . Double speed mode - */ - i2c_reg_write(I2C_DAC_ADDR, 0x01, - (right_just ? DAC_REG1_RIGHT_JUST_24BIT : - DAC_REG1_LEFT_JUST_24_BIT) | - DAC_REG1_DEM_NO | - (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); - - sprintf(str_buf, "%d", - sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); - setenv("DaqDACFunctionalMode", str_buf); - - /* - * Cause the DAC to: - * Enable control port (I2C mode) - * Remove power down - * . MCLK divide by 1 - * . MCLK divide by 2 - */ - i2c_reg_write(I2C_DAC_ADDR, 0x05, - DAC_REG5_I2C_MODE | - (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); - - /* - * Create a I2C stop condition: - * low->high on data while clock is high. - */ - I2C_SCL(1); - I2C_DELAY; - I2C_SDA(1); - I2C_DELAY; - I2C_TRISTATE; - - if (!quiet) { - printf("\n"); - } + i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */ + ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL); + + i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */ + (sample_64x ? 0 : ADC_REG2_128x) | + ADC_REG2_CAL | + ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE); + + udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */ + i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */ + + /* + * Now that we have synchronized the ADC's, enable address + * selection on the second ADC as well as the first. + */ + i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE); + + /* + * Initialize the Crystal DAC + * + * Two of the config lines are used for I2C so we have to set them + * to the proper initialization state without inadvertantly + * sending an I2C "start" sequence. When we bring the I2C back to + * the normal state, we send an I2C "stop" sequence. + */ + if (!quiet) + printf("Initializing the DAC...\n"); + + /* + * Bring the I2C clock and data lines low for initialization + */ + I2C_SCL(0); + I2C_DELAY; + I2C_SDA(0); + I2C_ACTIVE; + I2C_DELAY; + + /* Reset the DAC */ + iopa->pdat &= ~DAC_RST_MASK; + udelay(DAC_RESET_DELAY); + + /* Release the DAC reset */ + iopa->pdat |= DAC_RST_MASK; + udelay(DAC_INITIAL_DELAY); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Going into power down + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Going into power down + * . MCLK divide by 1 + * . MCLK divide by 2 + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | + DAC_REG5_POWER_DOWN | + (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); + + /* + * Cause the DAC to: + * Auto-mute disabled + * . Format 0, left justified 24 bits + * . Format 3, right justified 24 bits + * No de-emphasis + * . Single speed mode + * . Double speed mode + */ + i2c_reg_write(I2C_DAC_ADDR, 0x01, + (right_just ? DAC_REG1_RIGHT_JUST_24BIT : + DAC_REG1_LEFT_JUST_24_BIT) | + DAC_REG1_DEM_NO | + (sample_rate >= + 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE)); + + sprintf(str_buf, "%d", + sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE); + setenv("DaqDACFunctionalMode", str_buf); + + /* + * Cause the DAC to: + * Enable control port (I2C mode) + * Remove power down + * . MCLK divide by 1 + * . MCLK divide by 2 + */ + i2c_reg_write(I2C_DAC_ADDR, 0x05, + DAC_REG5_I2C_MODE | + (mclk_divide ? DAC_REG5_MCLK_DIV : 0)); + + /* + * Create a I2C stop condition: + * low->high on data while clock is high. + */ + I2C_SCL(1); + I2C_DELAY; + I2C_SDA(1); + I2C_DELAY; + I2C_TRISTATE; + + if (!quiet) + printf("\n"); #ifdef CONFIG_ETHER_LOOPBACK_TEST - /* - * Run the Ethernet loopback test - */ - eth_loopback_test (); + /* + * Run the Ethernet loopback test + */ + eth_loopback_test(); #endif /* CONFIG_ETHER_LOOPBACK_TEST */ #ifdef CONFIG_SHOW_BOOT_PROGRESS - /* - * Turn off the RED fail LED now that we are up and running. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); + /* + * Turn off the RED fail LED now that we are up and running. + */ + status_led_set(STATUS_LED_RED, STATUS_LED_OFF); #endif - return 0; + return 0; } #ifdef CONFIG_SHOW_BOOT_PROGRESS @@ -749,85 +741,86 @@ int misc_init_r(void) */ static void flash_code(uchar number, uchar modulo, uchar digits) { - int j; - - /* - * Recursively do upper digits. - */ - if(digits > 1) { - flash_code(number / modulo, modulo, digits - 1); - } - - number = number % modulo; - - /* - * Zero is indicated by one long flash (dash). - */ - if(number == 0) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(1000000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } else { - /* - * Non-zero is indicated by short flashes, one per count. - */ - for(j = 0; j < number; j++) { - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); - udelay(100000); - status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); - udelay(200000); - } - } - /* - * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total - */ - udelay(700000); -} - -static int last_boot_progress; + int j; -void show_boot_progress (int status) -{ - int i,j; - if(status > 0) { - last_boot_progress = status; - } else { /* - * If a specific failure code is given, flash this code - * else just use the last success code we've seen + * Recursively do upper digits. */ - if(status < -1) - last_boot_progress = -status; + if (digits > 1) + flash_code(number / modulo, modulo, digits - 1); + + number = number % modulo; /* - * Flash this code 5 times + * Zero is indicated by one long flash (dash). */ - for(j=0; j<5; j++) { - /* - * Houston, we have a problem. - * Blink the last OK status which indicates where things failed. - */ - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - flash_code(last_boot_progress, 5, 3); - - /* - * Delay 5 seconds between repetitions, - * with the fault LED blinking - */ - for(i=0; i<5; i++) { - status_led_set(STATUS_LED_RED, STATUS_LED_OFF); - udelay(500000); - status_led_set(STATUS_LED_RED, STATUS_LED_ON); - udelay(500000); - } + if (number == 0) { + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); + udelay(1000000); + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + udelay(200000); + } else { + /* + * Non-zero is indicated by short flashes, one per count. + */ + for (j = 0; j < number; j++) { + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); + udelay(100000); + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + udelay(200000); + } } - /* - * Reset the board to retry initialization. + * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total */ - do_reset (NULL, 0, 0, NULL); - } + udelay(700000); +} + +static int last_boot_progress; + +void show_boot_progress(int status) +{ + int i, j; + + if (status > 0) { + last_boot_progress = status; + } else { + /* + * If a specific failure code is given, flash this code + * else just use the last success code we've seen + */ + if (status < -1) + last_boot_progress = -status; + + /* + * Flash this code 5 times + */ + for (j = 0; j < 5; j++) { + /* + * Houston, we have a problem. + * Blink the last OK status which indicates where things failed. + */ + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + flash_code(last_boot_progress, 5, 3); + + /* + * Delay 5 seconds between repetitions, + * with the fault LED blinking + */ + for (i = 0; i < 5; i++) { + status_led_set(STATUS_LED_RED, + STATUS_LED_OFF); + udelay(500000); + status_led_set(STATUS_LED_RED, STATUS_LED_ON); + udelay(500000); + } + } + + /* + * Reset the board to retry initialization. + */ + do_reset(NULL, 0, 0, NULL); + } } #endif /* CONFIG_SHOW_BOOT_PROGRESS */ @@ -841,27 +834,29 @@ void show_boot_progress (int status) #define SPI_DAC_CS_MASK 0x00001000 static const u32 cs_mask[] = { - SPI_ADC_CS_MASK, - SPI_DAC_CS_MASK, + SPI_ADC_CS_MASK, + SPI_DAC_CS_MASK, }; int spi_cs_is_valid(unsigned int bus, unsigned int cs) { - return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); + return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); } void spi_cs_activate(struct spi_slave *slave) { - volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); + volatile ioport_t *iopd = + ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - iopd->pdat &= ~cs_mask[slave->cs]; + iopd->pdat &= ~cs_mask[slave->cs]; } void spi_cs_deactivate(struct spi_slave *slave) { - volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); + volatile ioport_t *iopd = + ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ ); - iopd->pdat |= cs_mask[slave->cs]; + iopd->pdat |= cs_mask[slave->cs]; } #endif diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index bb6eaf6fa..3a885a5cd 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -41,7 +41,7 @@ OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) ALL +=$(obj).depend $(LIB) ifdef CONFIG_SPL_BUILD -ALL += tools/mk$(BOARD)spl.exe +ALL += $(OBJTREE)/tools/mk$(BOARD)spl endif all: $(ALL) @@ -50,8 +50,8 @@ $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) ifdef CONFIG_SPL_BUILD -tools/mk$(BOARD)spl.exe: tools/mkv310_image.c - $(HOSTCC) tools/mkv310_image.c -o tools/mk$(BOARD)spl.exe +$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl endif ######################################################################### diff --git a/board/samsung/smdkv310/Makefile b/board/samsung/smdkv310/Makefile index d168abd11..56e0c16eb 100644 --- a/board/samsung/smdkv310/Makefile +++ b/board/samsung/smdkv310/Makefile @@ -26,16 +26,33 @@ LIB = $(obj)lib$(BOARD).o SOBJS := mem_setup.o SOBJS += lowlevel_init.o +ifndef CONFIG_SPL_BUILD COBJS += smdkv310.o +endif + +ifdef CONFIG_SPL_BUILD +COBJS += mmc_boot.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -all: $(obj).depend $(LIB) +ALL := $(obj).depend $(LIB) + +ifdef CONFIG_SPL_BUILD +ALL += $(OBJTREE)/tools/mk$(BOARD)spl +endif + +all: $(ALL) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) +ifdef CONFIG_SPL_BUILD +$(OBJTREE)/tools/mk$(BOARD)spl: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl +endif + ######################################################################### # defines $(obj).depend target diff --git a/board/samsung/smdkv310/mmc_boot.c b/board/samsung/smdkv310/mmc_boot.c new file mode 100644 index 000000000..d3fc18d19 --- /dev/null +++ b/board/samsung/smdkv310/mmc_boot.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<config.h> + +/* +* Copy U-boot from mmc to RAM: +* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains +* API (Data transfer from mmc to ram) +*/ +void copy_uboot_to_ram(void) +{ + u32 (*copy_bl2)(u32, u32, u32) = (void *)COPY_BL2_FNPTR_ADDR; + + copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); +} + +void board_init_f(unsigned long bootflag) +{ + __attribute__((noreturn)) void (*uboot)(void); + copy_uboot_to_ram(); + + /* Jump to U-Boot image */ + uboot = (void *)CONFIG_SYS_TEXT_BASE; + (*uboot)(); + /* Never returns Here */ +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /*Function attribute is no-return*/ + /*This Function never executes*/ + while (1) + ; +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) +{ +} diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index e0b89dd55..d9caca7f1 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -57,7 +57,6 @@ int board_init(void) smc9115_pre_init(); - gd->bd->bi_arch_number = MACH_TYPE_SMDKV310; gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } @@ -75,13 +74,17 @@ int dram_init(void) void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ + PHYS_SDRAM_1_SIZE); gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ + PHYS_SDRAM_2_SIZE); gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ + PHYS_SDRAM_3_SIZE); gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ + PHYS_SDRAM_4_SIZE); } int board_eth_init(bd_t *bis) diff --git a/board/samsung/smdkv310/tools/mkv310_image.c b/board/samsung/smdkv310/tools/mkv310_image.c new file mode 100644 index 000000000..1a51913f5 --- /dev/null +++ b/board/samsung/smdkv310/tools/mkv310_image.c @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <fcntl.h> +#include <errno.h> +#include <string.h> +#include <sys/stat.h> + +#define CHECKSUM_OFFSET (14*1024-4) +#define BUFSIZE (16*1024) +#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ + | S_IWGRP | S_IROTH | S_IWOTH) +/* +* Requirement: +* IROM code reads first 14K bytes from boot device. +* It then calculates the checksum of 14K-4 bytes and compare with data at +* 14K-4 offset. +* +* This function takes two filenames: +* IN "u-boot-spl.bin" and +* OUT "u-boot-mmc-spl.bin" as filenames. +* It reads the "u-boot-spl.bin" in 16K buffer. +* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. +* It writes the buffer to "u-boot-mmc-spl.bin" file. +*/ + +int main(int argc, char **argv) +{ + int i, len; + unsigned char buffer[BUFSIZE] = {0}; + int ifd, ofd; + unsigned int checksum = 0, count; + + if (argc != 3) { + printf(" %d Wrong number of arguments\n", argc); + exit(EXIT_FAILURE); + } + + ifd = open(argv[1], O_RDONLY); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[1], strerror(errno)); + exit(EXIT_FAILURE); + } + + ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[2], strerror(errno)); + if (ifd) + close(ifd); + exit(EXIT_FAILURE); + } + + len = lseek(ifd, 0, SEEK_END); + lseek(ifd, 0, SEEK_SET); + + count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET; + + if (read(ifd, buffer, count) != count) { + fprintf(stderr, "%s: Can't read %s: %s\n", + argv[0], argv[1], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++) + checksum += buffer[i]; + + memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum)); + + if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { + fprintf(stderr, "%s: Can't write %s: %s\n", + argv[0], argv[2], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + return EXIT_SUCCESS; +} diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 1b27e8b42..d767eaac4 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -27,6 +27,7 @@ #include <asm/arch/adc.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -57,6 +58,10 @@ int board_init(void) check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); +#if defined(CONFIG_PMIC) + pmic_init(); +#endif + return 0; } diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 50fae7c36..42f4c1ef0 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -89,26 +89,25 @@ phys_size_t initdram (int board_type) int fixed_sdram(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) { - return -1; - } - } + u32 msize = CONFIG_SYS_DDR_SIZE; + u32 ddr_size = msize << 20; /* DDR size in bytes */ + u32 ddr_size_log2 = __ilog2(msize); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); #if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif - im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; + +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + im->ddr.csbnds[2].csbnds = + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >> + CSBNDS_EA_SHIFT) & CSBNDS_EA); + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index e1a3ea36e..26095a545 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -77,12 +77,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index c5fe92e06..98bc7df4c 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -348,7 +348,7 @@ phys_size_t fixed_sdram(void) void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; + int node; #ifdef CONFIG_PCI const char *path; #endif @@ -356,7 +356,6 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { #ifdef CONFIG_PCI path = fdt_getprop(blob, node, "pci0", NULL); diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile index 07cc5a659..07db9d44e 100644 --- a/board/siemens/SCM/Makefile +++ b/board/siemens/SCM/Makefile @@ -24,8 +24,7 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqc/tqm8xx) +$(shell mkdir -p $(obj)../common $(obj)../../tqc/tqm8xx) endif LIB = $(obj)lib$(BOARD).o diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index 926e49127..461b56e3f 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -24,6 +24,7 @@ #include <common.h> #include <ioports.h> #include <mpc8260.h> +#include <linux/compiler.h> #include "scm.h" @@ -397,7 +398,7 @@ static void config_scoh_cs (void) volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE; - volatile uint tmp, i; + __maybe_unused volatile uint tmp, i; /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ memctl->memc_or3 = CONFIG_SYS_CAN0_OR3; diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c index db1f21a58..af329b9f5 100644 --- a/board/svm_sc8xx/flash.c +++ b/board/svm_sc8xx/flash.c @@ -27,155 +27,163 @@ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions */ -static int write_word (flash_info_t *info, ulong dest, ulong data); -#if 0 -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); -#endif -#ifdef CONFIG_BOOT_8B -static int my_in_8( unsigned char *addr); -static void my_out_8( unsigned char *addr, int val); +static int write_word(flash_info_t *info, ulong dest, ulong data); + +#ifdef CONFIG_BOOT_8B +static int my_in_8(unsigned char *addr); +static void my_out_8(unsigned char *addr, int val); #endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16( unsigned short *addr); -static void my_out_be16( unsigned short *addr, int val); +#ifdef CONFIG_BOOT_16B +static int my_in_be16(unsigned short *addr); +static void my_out_be16(unsigned short *addr, int val); #endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32( unsigned *addr); -static void my_out_be32( unsigned *addr, int val); +#ifdef CONFIG_BOOT_32B +static unsigned my_in_be32(unsigned *addr); +static void my_out_be32(unsigned *addr, int val); #endif /*----------------------------------------------------------------------- */ -unsigned long flash_init (void) +unsigned long flash_init(void) { - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; - size_b0=0; - size_b1=0; + size_b0 = 0; + size_b1 = 0; /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; - } + #ifdef CONFIG_SYS_DOC_BASE #ifndef CONFIG_FEL8xx_AT - memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */ + /* 32k bytes */ + memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401; #else - memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */ + /* 32k bytes */ + memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC); memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401; #endif #endif -#if defined( CONFIG_BOOT_8B) -/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ -/* memctl->memc_br0 = 0x40000401; */ - size_b0 = 0x80000; /* 512 K */ +#if defined(CONFIG_BOOT_8B) + size_b0 = 0x80000; /* 512 K */ + flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; flash_info[0].sector_count = 8; flash_info[0].size = 0x00080000; + /* set up sector start address table */ for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + (i * 0x10000); + flash_info[0].start[i] = 0x40000000 + (i * 0x10000); + /* protect all sectors */ for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; -#elif defined (CONFIG_BOOT_16B) -/* memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */ -/* memctl->memc_br0 = 0x40000401; */ - size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ + flash_info[0].protect[i] = 0x1; + +#elif defined(CONFIG_BOOT_16B) + size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ + flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; flash_info[0].sector_count = 67; flash_info[0].size = 0x00400000; + /* set up sector start address table */ - flash_info[0].start[0] = 0x40000000 ; + flash_info[0].start[0] = 0x40000000; flash_info[0].start[1] = 0x40000000 + 0x4000; flash_info[0].start[2] = 0x40000000 + 0x6000; flash_info[0].start[3] = 0x40000000 + 0x8000; - for (i = 4; i < flash_info[0].sector_count; i++) - flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000); + + for (i = 4; i < flash_info[0].sector_count; i++) { + flash_info[0].start[i] = + 0x40000000 + 0x10000 + ((i - 4) * 0x10000); + } + /* protect all sectors */ for (i = 0; i < flash_info[0].sector_count; i++) - flash_info[0].protect[i] = 0x1; + flash_info[0].protect[i] = 0x1; #endif - #ifdef CONFIG_BOOT_32B /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, + &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); } - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); + size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM, + &flash_info[1]); if (size_b1 > size_b0) { - printf ("## ERROR: " + printf("## ERROR: " "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); + size_b1, size_b1 << 20, size_b0, size_b0 << 20); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + + return 0; } /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | + (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | + BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, + &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | + (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + + size_b0), &flash_info[1]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0, + &flash_info[1]); #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]); #endif @@ -183,11 +191,11 @@ unsigned long flash_init (void) /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); #endif } else { - memctl->memc_br1 = 0; /* invalidate bank */ + memctl->memc_br1 = 0; /* invalidate bank */ flash_info[1].flash_id = FLASH_UNKNOWN; flash_info[1].sector_count = -1; @@ -197,350 +205,209 @@ unsigned long flash_init (void) flash_info[1].size = size_b1; -#endif /* CONFIG_BOOT_32B */ +#endif /* CONFIG_BOOT_32B */ - return (size_b0 + size_b1); + return size_b0 + size_b1; } -#if 0 -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } -} -#endif -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) + +void flash_print_info(flash_info_t *info) { int i; if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); + printf("missing or unknown FLASH type\n"); return; } switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + default: + printf("Unknown Vendor "); + break; } switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; } - printf (" Size: %ld MB in %d Sectors\n", + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); + printf("\n "); + printf(" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); } - printf ("\n"); + printf("\n"); return; } -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - /* * The following code cannot be run from FLASH! */ -#if 0 -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) +int flash_erase(flash_info_t *info, int s_first, int s_last) { - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect,in_mid,in_did; + vu_long *addr = (vu_long *) (info->start[0]); + int flag, prot, sect, l_sect, in_mid, in_did; ulong start, now, last; if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } + if (info->flash_id == FLASH_UNKNOWN) + printf("- missing\n"); + else + printf("- no sectors to erase\n"); + return 1; } if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); return 1; } prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) prot++; - } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", + printf("- Warning: %d protected sectors will not be erased!\n", prot); } else { - printf ("\n"); + printf("\n"); } l_sect = -1; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); -#if defined (CONFIG_BOOT_8B ) - my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0xaa ); - my_out_8( (unsigned char * ) ((ulong)addr+0x2aa) , 0x55 ); - my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0x90 ); - in_mid=my_in_8( (unsigned char * ) addr ); - in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_8( (unsigned char *)addr, 0xf0); + +#if defined(CONFIG_BOOT_8B) + my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); + my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); + my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90); + + in_mid = my_in_8((unsigned char *)addr); + in_did = my_in_8((unsigned char *)((ulong)addr + 1)); + + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + + my_out_8((unsigned char *)addr, 0xf0); udelay(1); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); - my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0x80 ); - my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); - my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); + + my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); + my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); + my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80); + my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa); + my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55); + /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); + addr = (vu_long *) (info->start[sect]); /*addr[0] = 0x00300030; */ - my_out_8( (unsigned char *) ((ulong)addr),0x30 ); + my_out_8((unsigned char *)((ulong)addr), 0x30); l_sect = sect; } } -#elif defined(CONFIG_BOOT_16B ) - my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0xaa ); - my_out_be16( (unsigned short * ) ((ulong)addr+ (0x554)) , 0x55 ); - my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0x90 ); - in_mid=my_in_be16( (unsigned short * ) addr ); - in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_be16( (unsigned short *)addr, 0xf0); +#elif defined(CONFIG_BOOT_16B) + my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55); + my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90); + in_mid = my_in_be16((unsigned short *)addr); + in_did = my_in_be16((unsigned short *)((ulong)addr + 2)); + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + my_out_be16((unsigned short *)addr, 0xf0); udelay(1); - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); - my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0x80 ); - my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - my_out_be16( (unsigned short *) ((ulong)addr),0x30 ); + addr = (vu_long *) (info->start[sect]); + my_out_be16((unsigned short *)((ulong)addr), 0x30); l_sect = sect; } } #elif defined(CONFIG_BOOT_32B) - my_out_be32( (unsigned * ) ((ulong)addr+0x1554) , 0xaa ); - my_out_be32( (unsigned * ) ((ulong)addr+0xaa8) , 0x55 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554) , 0x90 ); - in_mid=my_in_be32( (unsigned * ) addr ); - in_did=my_in_be32( (unsigned * ) ((ulong)addr+4) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_be32( (unsigned *)addr, 0xf0); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); + my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90); + + in_mid = my_in_be32((unsigned *)addr); + in_did = my_in_be32((unsigned *)((ulong)addr + 4)); + + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + + my_out_be32((unsigned *) addr, 0xf0); udelay(1); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); - my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0x80 ); - my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); - my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); + + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); + my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80); + my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa); + my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55); + /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { + for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - my_out_be32( (unsigned *) ((ulong)addr),0x00300030 ); + addr = (vu_long *) (info->start[sect]); + my_out_be32((unsigned *)((ulong)addr), 0x00300030); l_sect = sect; } } #else -# error CONFIG_BOOT_(size)B missing. +#error CONFIG_BOOT_(size)B missing. #endif /* re-enable interrupts if necessary */ if (flag) enable_interrupts(); /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + udelay(1000); /* * We wait for the last triggered sector @@ -548,53 +415,55 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) if (l_sect < 0) goto DONE; - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); -#if defined (CONFIG_BOOT_8B) - while ( (my_in_8((unsigned char *)addr) & 0x80) != 0x80 ) -#elif defined(CONFIG_BOOT_16B ) - while ( (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 ) + start = get_timer(0); + last = start; + addr = (vu_long *) (info->start[l_sect]); +#if defined(CONFIG_BOOT_8B) + while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80) +#elif defined(CONFIG_BOOT_16B) + while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080) #elif defined(CONFIG_BOOT_32B) - while ( (my_in_be32((unsigned *)addr) & 0x00800080) != 0x00800080 ) + while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080) #else -# error CONFIG_BOOT_(size)B missing. +#error CONFIG_BOOT_(size)B missing. #endif { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); + now = get_timer(start); + if (now > CONFIG_SYS_FLASH_ERASE_TOUT) { + printf("Timeout\n"); return 1; } /* show that we're waiting */ if ((now - last) > 1000) { /* every second */ - putc ('.'); + putc('.'); last = now; } } DONE: /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; -#if defined (CONFIG_BOOT_8B) - my_out_8( (unsigned char *)addr, 0xf0); -#elif defined(CONFIG_BOOT_16B ) - my_out_be16( (unsigned short * ) addr , 0x00f0 ); + addr = (volatile unsigned long *) info->start[0]; + +#if defined(CONFIG_BOOT_8B) + my_out_8((unsigned char *) addr, 0xf0); +#elif defined(CONFIG_BOOT_16B) + my_out_be16((unsigned short *) addr, 0x00f0); #elif defined(CONFIG_BOOT_32B) - my_out_be32 ( (unsigned *)addr, 0x00F000F0 ); /* reset bank */ + my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */ #else -# error CONFIG_BOOT_(size)B missing. +#error CONFIG_BOOT_(size)B missing. #endif - printf (" done\n"); + printf(" done\n"); return 0; } -/*----------------------------------------------------------------------- +/* * Copy memory to flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; @@ -604,23 +473,26 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle unaligned start bytes */ - if ((l = addr - wp) != 0) { + l = addr - wp; + + if (l != 0) { data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { + for (i = 0, cp = wp; i < l; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + for (; i < 4 && cnt > 0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } + for (; cnt == 0 && i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } wp += 4; } @@ -629,113 +501,123 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i=0; i<4; ++i) { + for (i = 0; i < 4; ++i) data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; + + rc = write_word(info, wp, data); + + if (rc != 0) + return rc; + + wp += 4; cnt -= 4; } - if (cnt == 0) { - return (0); - } + if (cnt == 0) + return 0; /* * handle unaligned tail bytes */ data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } + for (; i < 4; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); - return (write_word(info, wp, data)); + return write_word(info, wp, data); } -/*----------------------------------------------------------------------- +/* * Write a word to Flash, returns: * 0 - OK * 1 - write timeout * 2 - Flash not erased */ -static int write_word (flash_info_t *info, ulong dest, ulong data) +static int write_word(flash_info_t *info, ulong dest, ulong data) { - ulong addr = (ulong)(info->start[0]); - ulong start,last; + ulong addr = (ulong) (info->start[0]); + ulong start; int flag; ulong i; - int data_short[2]; + int data_short[2]; /* Check if Flash is (sufficiently) erased */ - if ( ((ulong) *(ulong *)dest & data) != data ) { - return (2); - } + if (((ulong)*(ulong *)dest & data) != data) + return 2; + /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); #if defined(CONFIG_BOOT_8B) #ifdef DEBUG { - int in_mid,in_did; - my_out_8( (unsigned char * ) (addr+0x555) , 0xaa ); - my_out_8( (unsigned char * ) (addr+0x2aa) , 0x55 ); - my_out_8( (unsigned char * ) (addr+0x555) , 0x90 ); - in_mid=my_in_8( (unsigned char * ) addr ); - in_did=my_in_8( (unsigned char * ) (addr+1) ); - printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); - my_out_8( (unsigned char *)addr, 0xf0); - udelay(1); + int in_mid, in_did; + + my_out_8((unsigned char *) (addr + 0x555), 0xaa); + my_out_8((unsigned char *) (addr + 0x2aa), 0x55); + my_out_8((unsigned char *) (addr + 0x555), 0x90); + + in_mid = my_in_8((unsigned char *) addr); + in_did = my_in_8((unsigned char *) (addr + 1)); + + printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did); + + my_out_8((unsigned char *) addr, 0xf0); + udelay(1); } #endif - { - int data_ch[4]; - data_ch[0]=(int ) ((data>>24) & 0xff); - data_ch[1]=(int ) ((data>>16) &0xff ); - data_ch[2]=(int ) ((data >>8) & 0xff); - data_ch[3]=(int ) (data & 0xff); - for (i=0;i<4;i++ ){ - my_out_8( (unsigned char *) (addr+0x555),0xaa); - my_out_8((unsigned char *) (addr+0x2aa),0x55); - my_out_8( (unsigned char *) (addr+0x555),0xa0); - my_out_8((unsigned char *) (dest+i) ,data_ch[i]); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - last = start; - while( ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i] ) ) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { - return 1; - } - } - }/* for */ - } -#elif defined( CONFIG_BOOT_16B) - data_short[0]=(int) (data>>16) & 0xffff; - data_short[1]=(int ) data & 0xffff ; - for (i=0;i<2;i++ ){ - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); - my_out_be16( (unsigned short *) ((ulong)addr+ 0x554),0x55 ); - my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 ); - my_out_be16( (unsigned short *) (dest+(i*2)) ,data_short[i]); - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - start = get_timer (0); - last = start; - while( ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i] ) ) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { - return 1; - } - } + { + int data_ch[4]; + + data_ch[0] = (int) ((data >> 24) & 0xff); + data_ch[1] = (int) ((data >> 16) & 0xff); + data_ch[2] = (int) ((data >> 8) & 0xff); + data_ch[3] = (int) (data & 0xff); + + for (i = 0; i < 4; i++) { + my_out_8((unsigned char *) (addr + 0x555), 0xaa); + my_out_8((unsigned char *) (addr + 0x2aa), 0x55); + my_out_8((unsigned char *) (addr + 0x555), 0xa0); + my_out_8((unsigned char *) (dest + i), data_ch[i]); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + while ((my_in_8((unsigned char *)(dest + i))) != + (data_ch[i])) { + if (get_timer(start) > + CONFIG_SYS_FLASH_WRITE_TOUT) { + return 1; + } + } + } /* for */ + } +#elif defined(CONFIG_BOOT_16B) + data_short[0] = (int) (data >> 16) & 0xffff; + data_short[1] = (int) data & 0xffff; + for (i = 0; i < 2; i++) { + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa); + my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55); + my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0); + my_out_be16((unsigned short *)(dest + (i * 2)), + data_short[i]); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer(0); + while ((my_in_be16((unsigned short *)(dest + (i * 2)))) != + (data_short[i])) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; + } } -#elif defined( CONFIG_BOOT_32B) +#elif defined(CONFIG_BOOT_32B) addr[0x0555] = 0x00AA00AA; addr[0x02AA] = 0x00550055; addr[0x0555] = 0x00A000A0; @@ -747,51 +629,54 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) enable_interrupts(); /* data polling for D7 */ - start = get_timer (0); + start = get_timer(0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) + return 1; } #endif - - - return (0); + return 0; } -#ifdef CONFIG_BOOT_8B -static int my_in_8 ( unsigned char *addr) + +#ifdef CONFIG_BOOT_8B +static int my_in_8(unsigned char *addr) { - int ret; - __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + int ret; + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); + + return ret; } -static void my_out_8 ( unsigned char *addr, int val) +static void my_out_8(unsigned char *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); } #endif -#ifdef CONFIG_BOOT_16B -static int my_in_be16( unsigned short *addr) +#ifdef CONFIG_BOOT_16B +static int my_in_be16(unsigned short *addr) { - int ret; - __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + int ret; + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); + + return ret; } -static void my_out_be16( unsigned short *addr, int val) + +static void my_out_be16(unsigned short *addr, int val) { - __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); } #endif -#ifdef CONFIG_BOOT_32B -static unsigned my_in_be32( unsigned *addr) +#ifdef CONFIG_BOOT_32B +static unsigned my_in_be32(unsigned *addr) { unsigned ret; - __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr)); + + return ret; } -static void my_out_be32( unsigned *addr, int val) + +static void my_out_be32(unsigned *addr, int val) { - __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val)); } #endif diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c index f34b83515..771bb4a5f 100644 --- a/board/svm_sc8xx/svm_sc8xx.c +++ b/board/svm_sc8xx/svm_sc8xx.c @@ -80,15 +80,12 @@ int checkboard(void) char buf[64]; int i; int l = getenv_f("serial#", buf, sizeof(buf)); - int board_type; if (l < 0 || strncmp(buf, "SVM8", 4)) { printf("### No HW ID - assuming SVM SC8xx\n"); return (0); } - board_type = 1; - for (i = 0; i < l; ++i) { if (buf[i] == ' ') break; @@ -97,7 +94,7 @@ int checkboard(void) putc('\n'); - return (0); + return 0; } /* ------------------------------------------------------------------------- */ diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c index 63a0d3344..72288fe4e 100644 --- a/board/syteco/jadecpu/jadecpu.c +++ b/board/syteco/jadecpu/jadecpu.c @@ -40,7 +40,6 @@ int board_init(void) writel(0x00000010, &ccnt->cmux_md); gd->flags = 0; - gd->bd->bi_arch_number = MACH_TYPE_JADECPU; gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; icache_enable(); diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c index a89ee1a08..c56b195ae 100644 --- a/board/syteco/zmx25/zmx25.c +++ b/board/syteco/zmx25/zmx25.c @@ -128,7 +128,6 @@ int board_late_init(void) #ifdef CONFIG_FEC_MXC struct iomuxc_mux_ctl *muxctl; - struct iomuxc_pad_ctl *padctl; u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); @@ -144,7 +143,6 @@ int board_late_init(void) * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 */ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index b17c0fbad..8c434633d 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -217,7 +217,22 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_SMC911X +#define STR_ENV_ETHADDR "ethaddr" + + struct eth_device *dev; + uchar eth_addr[6]; + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + + if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { + dev = eth_get_dev_by_index(0); + if (dev) { + eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); + } else { + printf("omap3evm: Couldn't get eth device\n"); + rc = -1; + } + } #endif return rc; } diff --git a/board/innokom/Makefile b/board/ti/omap5_evm/Makefile index 8b58b7f19..fa81d64be 100644 --- a/board/innokom/Makefile +++ b/board/ti/omap5_evm/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := innokom.o flash.o +COBJS := evm.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -33,6 +33,12 @@ OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c new file mode 100644 index 000000000..ea0cb13b4 --- /dev/null +++ b/board/ti/omap5_evm/evm.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * Steve Sakoman <steve@sakoman.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl6030.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> + +#include "mux_data.h" + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: OMAP5430 EVM\n" +}; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; + gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +/** + * @brief misc_init_r - Configure EVM board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ +#ifdef CONFIG_TWL6030_POWER + twl6030_init_battery_charging(); +#endif + return 0; +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +void set_muxconf_regs_non_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + omap_mmc_init(1); + return 0; +} +#endif diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h new file mode 100644 index 000000000..18f472925 --- /dev/null +++ b/board/ti/omap5_evm/mux_data.h @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * + * Balaji Krishnamoorthy <balajitk@ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EVM5430_MUX_DATA_H +#define _EVM5430_MUX_DATA_H + +#include <asm/arch/mux_omap5.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +const struct pad_conf_entry core_padconf_array_non_essential[] = { + {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ + {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ + {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ + {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ + {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ + {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ + {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ + {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ + {GPMC_A16, (M3)}, /* gpio_40 */ + {GPMC_A17, (PTD | M3)}, /* gpio_41 */ + {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ + {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ + {GPMC_A20, (IEN | M3)}, /* gpio_44 */ + {GPMC_A21, (M3)}, /* gpio_45 */ + {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ + {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ + {GPMC_A24, (PTD | M3)}, /* gpio_48 */ + {GPMC_A25, (PTD | M3)}, /* gpio_49 */ + {GPMC_NCS0, (M3)}, /* gpio_50 */ + {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ + {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ + {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ + {GPMC_NWP, (M3)}, /* gpio_54 */ + {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ + {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ + {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ + {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ + {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ + {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ + {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ + {C2C_DATA12, (M1)}, /* dsi1_te0 */ + {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ + {C2C_DATA14, (M1)}, /* dsi2_te0 */ + {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ + {HDMI_HPD, (M0)}, /* hdmi_hpd */ + {HDMI_CEC, (M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ + {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ + {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ + {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ + {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ + {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ + {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ + {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ + {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ + {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ + {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ + {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ + {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ + {UART2_RTS, (M0)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ + {UART2_TX, (M0)}, /* uart2_tx */ + {HDQ_SIO, (M3)}, /* gpio_127 */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ + {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ + {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ + {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ + {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ + {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ + {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ + {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ + {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ + {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ + {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ + {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ + {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ + {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ + {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ + {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ + {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ + {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ + {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ + {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ + {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ + {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ + {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ + {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ + {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ + {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ + {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ + {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ + {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ + {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ + {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ + {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ + {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ + {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ + {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ + {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ + {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ + {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ + {DPM_EMU16, (M3)}, /* gpio_27 */ + {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ + {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ + {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ +}; + +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ + {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ +}; + +#endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile index ec493f5c3..b299e2fff 100644 --- a/board/ti/panda/Makefile +++ b/board/ti/panda/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -ifndef CONFIG_SPL_BUILD COBJS := panda.o -endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 97320cb27..b4271fb58 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -65,6 +65,23 @@ int misc_init_r(void) return 0; } +void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + if (omap_revision() >= OMAP4460_ES1_0) + do_set_mux(CONTROL_PADCONF_WKUP, + wkup_padconf_array_essential_4460, + sizeof(wkup_padconf_array_essential_4460) / + sizeof(struct pad_conf_entry)); +} + void set_muxconf_regs_non_essential(void) { do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, @@ -93,10 +110,18 @@ void set_muxconf_regs_non_essential(void) sizeof(struct pad_conf_entry)); } -#ifdef CONFIG_GENERIC_MMC +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); return 0; } #endif + +/* + * get_board_rev() - get board revision + */ +u32 get_board_rev(void) +{ + return 0x20; +} diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 83d0c3fd8..c05170e33 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -28,6 +28,58 @@ #include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ +{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ +{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ +{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ +{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ +{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ +{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ +{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { + +{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */ + +}; + const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ @@ -219,7 +271,7 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ + {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile index 806fdf476..72ad3eb07 100644 --- a/board/ti/sdp4430/Makefile +++ b/board/ti/sdp4430/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS := sdp.o + ifndef CONFIG_SPL_BUILD -COBJS := sdp.o cmd_bat.o +COBJS += cmd_bat.o endif SRCS := $(COBJS:.o=.c) diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index a5ea6829c..e1b853c4e 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -70,6 +70,23 @@ int misc_init_r(void) return 0; } +void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + if (omap_revision() >= OMAP4460_ES1_0) + do_set_mux(CONTROL_PADCONF_WKUP, + wkup_padconf_array_essential_4460, + sizeof(wkup_padconf_array_essential_4460) / + sizeof(struct pad_conf_entry)); +} + void set_muxconf_regs_non_essential(void) { do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, @@ -81,7 +98,7 @@ void set_muxconf_regs_non_essential(void) sizeof(struct pad_conf_entry)); } -#ifdef CONFIG_GENERIC_MMC +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); @@ -89,3 +106,11 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +/* + * get_board_rev() - get board revision + */ +u32 get_board_rev(void) +{ + return 0x20; +} diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 06efaeaa4..1c6e0eeb6 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -28,6 +28,49 @@ #include <asm/arch/mux_omap4.h> +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { + +{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7, TPS */ + +}; + const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ @@ -200,6 +243,15 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ + }; const struct pad_conf_entry wkup_padconf_array_non_essential[] = { @@ -214,7 +266,6 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 - Debug led-2 */ {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index 4c8922f35..5329c2a41 100644 --- a/board/tqc/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c @@ -279,7 +279,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) @@ -305,8 +305,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) printf("\n"); - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -322,7 +320,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -609,7 +606,7 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) @@ -635,8 +632,6 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) printf("\n"); - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -652,7 +647,6 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index 0789c5848..c40f7f042 100644 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c @@ -82,18 +82,17 @@ static void spi_init(void) static int spi_transmit(unsigned char data) { - int dummy; struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; spi->dr = data; /* wait for SPI transmission completed */ - while(!(spi->sr & 0x80)) - { - if (spi->sr & 0x40) /* if write collision occured */ - { + while (!(spi->sr & 0x80)) { + if (spi->sr & 0x40) { /* if write collision occured */ + int dummy; + /* do dummy read to clear status register */ dummy = spi->dr; - printf ("SPI write collision\n"); + printf("SPI write collision: dr=0x%x\n", dummy); return -1; } } @@ -172,10 +171,8 @@ static void i2s_init(void) psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ psc->ctur = 0x0F; /* 16 bit frame width */ - for(i=0;i<128;i++) - { + for (i = 0; i < 128; i++) psc->psc_buffer_32 = 0; /* clear tx fifo */ - } } static int i2s_play_wave(unsigned long addr, unsigned long len) @@ -183,7 +180,6 @@ static int i2s_play_wave(unsigned long addr, unsigned long len) unsigned long i; unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip * wav header*/ - unsigned char swapped[4]; struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; /* @@ -192,11 +188,16 @@ static int i2s_play_wave(unsigned long addr, unsigned long len) psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); for(i = 0;i < (len / 4); i++) { + unsigned char swapped[4]; + unsigned long *p = (unsigned long*)swapped; + swapped[3] = *wave_file++; swapped[2] = *wave_file++; swapped[1] = *wave_file++; swapped[0] = *wave_file++; - psc->psc_buffer_32 = *((unsigned long*)swapped); + + psc->psc_buffer_32 = *p; + while (psc->tfnum > 400) { if(ctrlc()) return 0; diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index 9efb54125..5aca22778 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -459,10 +459,9 @@ phys_size_t initdram (int board_type) #ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif - long psize, lsize; + long psize; psize = 16 * 1024 * 1024; - lsize = 0; memctl->memc_psrt = CONFIG_SYS_PSRT; memctl->memc_mptpr = CONFIG_SYS_MPTPR; diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index d3815b2ee..f556d308e 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -31,7 +31,6 @@ #include <asm/arch/iomux.h> #include <asm/gpio.h> #include <asm/arch/sys_proto.h> -#include <asm/errno.h> #include <i2c.h> #include <mmc.h> #include <pmic.h> @@ -44,8 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; -static u32 system_rev; - static struct fb_videomode nec_nl6448bc26_09c = { "NEC_NL6448BC26-09C", 60, /* Refresh */ @@ -151,13 +148,6 @@ static void init_drive_strength(void) PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); } -u32 get_board_rev(void) -{ - system_rev = get_cpu_rev(); - - return system_rev; -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 166e459a3..924d87112 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -65,8 +65,14 @@ static long fixed_sdram(void) */ __udelay(50000); - out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG); +#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0) +#warning Chip select bounds is only configurable in 16MB increments +#endif + out_be32(&im->ddr.csbnds[0].csbnds, + ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) & + CSBNDS_EA)); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); /* Currently we use only one CS, so disable the other bank. */ out_be32(&im->ddr.cs_config[1], 0); diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 43bbdff70..cf8e7b61d 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -21,6 +21,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/regs-mmc.h> #include <netdev.h> #include <serial.h> #include <asm/io.h> @@ -72,6 +73,14 @@ void dram_init_banksize(void) #endif } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_USB int usb_board_init(void) { |