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authorwdenk <wdenk>2005-04-05 22:30:50 +0000
committerwdenk <wdenk>2005-04-05 22:30:50 +0000
commitb304c96871c92d1ec8fa57dda36cc198660fd10e (patch)
treeb45ea6bbac8eee483d99eccbddda21af57f8e8be /cpu/arm920t/start.S
parent12b43d515c62682fcf7b578f31920a2be49142fe (diff)
Patches by Steven Scholz, 05 Apr 2005:
- Use i.MX watchdog timer for reset_cpu() - Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ (now in interupts.c)
Diffstat (limited to 'cpu/arm920t/start.S')
-rw-r--r--cpu/arm920t/start.S36
1 files changed, 0 insertions, 36 deletions
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index afe654b8c..74a97d529 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -433,39 +433,3 @@ fiq:
bl do_fiq
#endif
-
- .align 5
-.globl reset_cpu
-reset_cpu:
-#ifdef CONFIG_S3C2400
- bl disable_interrupts
-# ifdef CONFIG_TRAB
- bl disable_vfd
-# endif
- ldr r1, _rWTCON
- ldr r2, _rWTCNT
- /* Disable watchdog */
- mov r3, #0x0000
- str r3, [r1]
- /* Initialize watchdog timer count register */
- mov r3, #0x0001
- str r3, [r2]
- /* Enable watchdog timer; assert reset at timer timeout */
- mov r3, #0x0021
- str r3, [r1]
-_loop_forever:
- b _loop_forever
-_rWTCON:
- .word 0x15300000
-_rWTCNT:
- .word 0x15300008
-#else /* ! CONFIG_S3C2400 */
- mov ip, #0
- mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
- mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
- mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
- bic ip, ip, #0x000f @ ............wcam
- bic ip, ip, #0x2100 @ ..v....s........
- mcr p15, 0, ip, c1, c0, 0 @ ctrl register
- mov pc, r0
-#endif /* CONFIG_S3C2400 */