diff options
| author | Tom Rini <trini@ti.com> | 2011-11-18 12:48:06 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-12-06 23:59:38 +0100 |
| commit | 9ae0d550741db45e933dc73e7135d1861e3a9b62 (patch) | |
| tree | b640b1a6600c6b7716ac922037e8f908e2126937 /board/timll | |
| parent | fc41ba1e2b4271bef197bfbf89d49458368319ce (diff) | |
OMAP3 SPL: Rework memory initalization and devkit8000 support
This changes to making the board be responsible for providing the
memory initialization timings in SPL and converts the devkit8000
to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz <frederik@kriewitz.eu>
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/timll')
| -rw-r--r-- | board/timll/devkit8000/devkit8000.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index fee0dff33..b06aab617 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. We have either one or two banks of 128MB DDR. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + /* General SDRC config */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + /* AC timings */ + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + + *mr = MICRON_V_MR_165; +} |