Reworked FSL Book-E TLB macros to be more readable

The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry.  Actually use the bit masks for these items
since they are only a single bit.

Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 66 insertions, 66 deletions

diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S
index 8c2ca65a9..a8ac3fb8c 100644
--- a/board/mpc8540eval/init.S
+++ b/board/mpc8540eval/init.S
@@ -46,93 +46,93 @@ tlb1_entry:
 
 	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
 
-	.long TLB1_MAS0(1,1,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,1,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G))
+	.long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
   #if defined(CFG_FLASH_PORT_WIDTH_16)
-	.long TLB1_MAS0(1,2,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,3,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,2,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
+	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+	.long FSL_BOOKE_MAS0(1,3,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x400000,(MAS2_I|MAS2_G))
+	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x400000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #else
-	.long TLB1_MAS0(1,2,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
-	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,3,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,2,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+	.long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G))
+	.long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+	.long FSL_BOOKE_MAS0(1,3,0)
+	.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long FSL_BOOKE_MAS2(0,0)
+	.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #endif
 
   #if !defined(CONFIG_SPD_EEPROM)
-	.long TLB1_MAS0(1,4,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,5,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,4,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0)
+	.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+	.long FSL_BOOKE_MAS0(1,5,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x4000000,0)
+	.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x4000000,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #else
-	.long TLB1_MAS0(1,4,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-
-	.long TLB1_MAS0(1,5,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,4,0)
+	.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long FSL_BOOKE_MAS2(0,0)
+	.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
+
+	.long FSL_BOOKE_MAS0(1,5,0)
+	.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long FSL_BOOKE_MAS2(0,0)
+	.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #endif
 
-	.long TLB1_MAS0(1,6,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long FSL_BOOKE_MAS0(1,6,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
   #if defined(CONFIG_RAM_AS_FLASH)
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,(MAS2_I|MAS2_G))
   #else
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,0)
   #endif
-	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-	.long TLB1_MAS0(1,7,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long FSL_BOOKE_MAS0(1,7,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
   #ifdef CONFIG_L2_INIT_RAM
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0)
   #else
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0)
   #endif
-	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-	.long TLB1_MAS0(1,8,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,8,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G))
+	.long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
-	.long TLB1_MAS0(1,9,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
-	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,9,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long FSL_BOOKE_MAS2(CFG_BCSR,(MAS2_I|MAS2_G))
+	.long FSL_BOOKE_MAS3(CFG_BCSR,0,(MAS3_SX|MAS3_SW|MAS3_SR))
 
   #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,15,0)
+	.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G))
+	.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #else
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+	.long FSL_BOOKE_MAS0(1,15,0)
+	.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long FSL_BOOKE_MAS2(0,0)
+	.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR))
   #endif
 	entry_end