aboutsummaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorJeong-Hyeon Kim <jhkim@insignal.co.kr>2012-08-28 20:52:09 +0900
committerJohn Rigby <john.rigby@linaro.org>2012-12-06 13:51:42 -0700
commitcd191553c40ab35703847ea2bb1f4c360fc3a49e (patch)
treef54d3a083323cd90fd52c00df797e084dda21225 /arch
parent5777e12667d2d7ee15aaf74cd3a2f7800f2c847d (diff)
downloadu-boot-linaro-stable-cd191553c40ab35703847ea2bb1f4c360fc3a49e.tar.gz
EXYNOS: add XXTI for clock source
Exynos SoC series are various and cover the different range of MCLK. Several clock setting is based on MPLL, but it's to easy change depend on board configuration. So, common setting of clock need for cover the various type of memory. System clock (XXTI) is one of solution for it. Signed-off-by: Jeong-Hyeon Kim <jhkim@insignal.co.kr>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 4f3b451be..680aeeb4d 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -246,7 +246,9 @@ static unsigned long exynos4_get_pwm_clk(void)
sel = readl(&clk->src_peril0);
sel = (sel >> 24) & 0xf;
- if (sel == 0x6)
+ if (sel == 0x0 || sel == 0x1)
+ sclk = CONFIG_SYS_CLK_FREQ;
+ else if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
@@ -314,7 +316,9 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
sel = readl(&clk->src_peril0);
sel = (sel >> (dev_index << 2)) & 0xf;
- if (sel == 0x6)
+ if (sel == 0x0 || sel == 0x1)
+ sclk = CONFIG_SYS_CLK_FREQ;
+ else if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
@@ -361,7 +365,9 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
sel = readl(&clk->src_peric0);
sel = (sel >> (dev_index << 2)) & 0xf;
- if (sel == 0x6)
+ if (sel == 0x0 || sel == 0x1)
+ sclk = CONFIG_SYS_CLK_FREQ;
+ else if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);
@@ -462,7 +468,9 @@ static unsigned long exynos4_get_lcd_clk(void)
* 0x7: SCLK_EPLL
* 0x8: SCLK_VPLL
*/
- if (sel == 0x6)
+ if (sel == 0x0 || sel == 0x1)
+ sclk = CONFIG_SYS_CLK_FREQ;
+ else if (sel == 0x6)
sclk = get_pll_clk(MPLL);
else if (sel == 0x7)
sclk = get_pll_clk(EPLL);