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authorMathieu J. Poirier <mathieu.poirier@linaro.org>2012-07-31 08:59:33 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-08-14 02:22:13 +0200
commit1b1d166eed221de2b2607c25f76b4a6fe21cd2be (patch)
treea93275aace9f79b2ee067d7b2a5851b66ba30ffb /arch
parent687a799690d19b5e09f0c7977e994223699ab9d7 (diff)
downloadu-boot-linaro-stable-1b1d166eed221de2b2607c25f76b4a6fe21cd2be.tar.gz
snowball: Adding board specific cache cleanup routine
Following ARM's reference manuel for initializing the cache - the kernel won't boot otherwise. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/u8500/cpu.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c
index 02bb33209..6f95c3067 100644
--- a/arch/arm/cpu/armv7/u8500/cpu.c
+++ b/arch/arm/cpu/armv7/u8500/cpu.c
@@ -36,6 +36,14 @@
#define CPUID_DB8500V2 0x412fc091
#define ASICID_DB8500V11 0x008500A1
+#define CACHE_CONTR_BASE 0xA0412000
+/* Cache controller register offsets
+ * as found in ARM's technical reference manual
+ */
+#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
+#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
+#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
+
static unsigned int read_asicid(void);
static inline unsigned int read_cpuid(void)
@@ -73,6 +81,24 @@ static unsigned int read_asicid(void)
return readl(address);
}
+void cpu_cache_initialization(void)
+{
+ unsigned int value;
+ /* invalidate all cache entries */
+ writel(0xFFFF, CACHE_INVAL_BY_WAY);
+
+ /* ways are set to '0' when they are totally
+ * cleaned and invalidated
+ */
+ do {
+ value = readl(CACHE_INVAL_BY_WAY);
+ } while (value & 0xFF);
+
+ /* Invalidate register 9 D and I lockdown */
+ writel(0xFF, CACHE_LOCKDOWN_BY_D);
+ writel(0xFF, CACHE_LOCKDOWN_BY_I);
+}
+
#ifdef CONFIG_ARCH_CPU_INIT
/*
* SOC specific cpu init