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authorWolfgang Denk <wd@denx.de>2011-08-02 21:46:53 +0200
committerWolfgang Denk <wd@denx.de>2011-08-02 21:46:53 +0200
commit1902692aa0b2dcbb9351172be03c57d1e82447e4 (patch)
treef6250202aaa6e98a7beaa08841a55b9e2d54d670 /arch/blackfin/include/asm/mach-bf506/anomaly.h
parentcc4e6d25561b1aaa8501fa6017a0d17fd4f92ed6 (diff)
parentd8940a654435dfa48013229edf53bd3e353e97c1 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
* 'master' of git://git.denx.de/u-boot-blackfin: Blackfin: jtag-console: fix timer usage Blackfin: switch to common display_options() Blackfin: serial: move early debug strings into .rodata section Blackfin: adi boards: also set stderr to nc with helper Blackfin: update anomaly lists to latest public info Blackfin: serial: convert to bfin_{read,write} helpers Blackfin: split out async setup Blackfin: adi boards: enable pretty flash progress output Blackfin: drop unused dma.h header from start code Blackfin: portmux: allow header to be included in assembly files Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings Blackfin: sync MMR read/write helpers with Linux Blackfin: gpio: optimize free path a little Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR Blackfin: uart: fix printf warning Blackfin: add init.elf helper code Blackfin: dont reset SWRST on newer bf526 parts Blackfin: adi boards: enable multi serial support by default Blackfin: uart: add multiple serial support Blackfin: uart: move debug buffers into local bss
Diffstat (limited to 'arch/blackfin/include/asm/mach-bf506/anomaly.h')
-rw-r--r--arch/blackfin/include/asm/mach-bf506/anomaly.h25
1 files changed, 21 insertions, 4 deletions
diff --git a/arch/blackfin/include/asm/mach-bf506/anomaly.h b/arch/blackfin/include/asm/mach-bf506/anomaly.h
index e76723322..5b3227a8e 100644
--- a/arch/blackfin/include/asm/mach-bf506/anomaly.h
+++ b/arch/blackfin/include/asm/mach-bf506/anomaly.h
@@ -5,12 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
+ * - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
*/
#if __SILICON_REVISION__ < 0
@@ -36,8 +37,6 @@
#define ANOMALY_05000310 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
@@ -52,12 +51,28 @@
#define ANOMALY_05000472 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
+/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
+#define ANOMALY_05000476 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
+/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
+#define ANOMALY_05000478 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
+/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
+#define ANOMALY_05000486 (1)
+/* SPI Master Boot Can Fail Under Certain Conditions */
+#define ANOMALY_05000490 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
+/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
+#define ANOMALY_05000494 (1)
+/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
+#define ANOMALY_05000495 (1)
+/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
+#define ANOMALY_05000498 (1)
+/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
+#define ANOMALY_05000501 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@@ -109,6 +124,7 @@
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
@@ -123,6 +139,7 @@
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif