diff options
| author | Tom Rini <trini@ti.com> | 2012-07-24 13:05:10 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:12 +0200 |
| commit | c8da4a587c5aaa070096db923ac45e5cf5d97ceb (patch) | |
| tree | a56bec13ca4dce23d2c6878a2f804e73623b650c /arch/arm/cpu/armv7/am33xx/emif4.c | |
| parent | b971dfad6a1c8c37857390d847ee22ec7af4aee2 (diff) | |
am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/am33xx/emif4.c')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/emif4.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 12f270a2d..684b12385 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -112,22 +112,22 @@ static void config_emif_ddr2(void) struct sdram_timing tmg; struct ddr_phy_control phyc; - /*Program EMIF0 CFG Registers*/ - phyc.reg = EMIF_READ_LATENCY; - phyc.reg_sh = EMIF_READ_LATENCY; - phyc.reg2 = EMIF_READ_LATENCY; - - tmg.time1 = EMIF_TIM1; - tmg.time1_sh = EMIF_TIM1; - tmg.time2 = EMIF_TIM2; - tmg.time2_sh = EMIF_TIM2; - tmg.time3 = EMIF_TIM3; - tmg.time3_sh = EMIF_TIM3; - - cfg.sdrcr = EMIF_SDCFG; - cfg.sdrcr2 = EMIF_SDCFG; - cfg.refresh = EMIF_SDREF; - cfg.refresh_sh = EMIF_SDREF; + /* Program EMIF0 CFG Registers */ + phyc.reg = DDR2_EMIF_READ_LATENCY; + phyc.reg_sh = DDR2_EMIF_READ_LATENCY; + phyc.reg2 = DDR2_EMIF_READ_LATENCY; + + tmg.time1 = DDR2_EMIF_TIM1; + tmg.time1_sh = DDR2_EMIF_TIM1; + tmg.time2 = DDR2_EMIF_TIM2; + tmg.time2_sh = DDR2_EMIF_TIM2; + tmg.time3 = DDR2_EMIF_TIM3; + tmg.time3_sh = DDR2_EMIF_TIM3; + + cfg.sdrcr = DDR2_EMIF_SDCFG; + cfg.sdrcr2 = DDR2_EMIF_SDCFG; + cfg.refresh = DDR2_EMIF_SDREF; + cfg.refresh_sh = DDR2_EMIF_SDREF; /* Program EMIF instance */ ret = config_ddr_phy(&phyc); @@ -159,14 +159,14 @@ void config_ddr(short ddr_type) config_ddr_data(0, &ddr2_data); config_ddr_data(1, &ddr2_data); - writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); - writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); + writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); + writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); - ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; - ioctrl.data1ctl = DDR_IOCTRL_VALUE; - ioctrl.data2ctl = DDR_IOCTRL_VALUE; + ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE; + ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE; + ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE; + ioctrl.data1ctl = DDR2_IOCTRL_VALUE; + ioctrl.data2ctl = DDR2_IOCTRL_VALUE; config_io_ctrl(&ioctrl); |