diff options
| author | Laurence Withers <lwithers@guralp.com> | 2012-07-30 23:30:36 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-08-05 22:02:40 +0200 |
| commit | 87e3917ecb412d7f3f8f3e1f572b37fc892202dc (patch) | |
| tree | 9b15aac5542db8d6746ef62a71c91e0dab9dbbfc /arch/arm/cpu/arm926ejs/davinci | |
| parent | a29d69e4640ce8b12e9f77cd37263dddf7455335 (diff) | |
DaVinci DA8xx: replace magic number for DDR speed
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper
definition. In addition, don't request this clock ID on DA830 hardware,
which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Cc: Tom Rini <trini@ti.com>
Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/davinci')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 6cb857aef..41201d0a4 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -194,7 +194,8 @@ int set_cpu_clk_info(void) #ifdef CONFIG_SOC_DA8XX gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); #else unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; |