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| author | Sandeep Paulraj <s-paulraj@ti.com> | 2010-12-29 14:31:26 -0500 |
|---|---|---|
| committer | Albert Aribaud <albert.aribaud@free.fr> | 2011-02-02 00:54:44 +0100 |
| commit | 5342a710c9f67e1adb4505423eccf64d1eca5eb8 (patch) | |
| tree | fcec8b8561aadcd61c61a330d561338f366c1bb8 /arch/arm/cpu/arm926ejs/davinci | |
| parent | b157dd51de35405940b5b6454f6e5b0bf3abd102 (diff) | |
DaVinci DM6467: Fix Build Error
This commit fixes build errors on the DM6467 port.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/davinci')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/cpu.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index fc3551c30..340c5becd 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -60,6 +60,12 @@ #define DDR_PLLDIV PLLC_PLLDIV1 #endif +#ifdef CONFIG_SOC_DM646X +#define DSP_PLLDIV PLLC_PLLDIV1 +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DDR_PLLDIV PLLC_PLLDIV1 +#endif + #ifdef CONFIG_SOC_DA8XX const dv_reg * const sysdiv[7] = { &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2, @@ -145,7 +151,11 @@ static inline unsigned pll_postdiv(volatile void *pllbase) static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) { volatile void *pllbase = (volatile void *) pll_addr; +#ifdef CONFIG_SOC_DM646X + unsigned base = CFG_REFCLK_FREQ / 1000; +#else unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; +#endif /* the PLL might be bypassed */ if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { @@ -176,6 +186,12 @@ int print_cpuinfo(void) return 0; } +#ifdef DAVINCI_DM6467EVM +unsigned int davinci_arm_clk_get() +{ + return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000; +} +#endif #endif /* |