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authorIlya Yanok <yanok@emcraft.com>2010-09-17 23:41:46 +0200
committerWolfgang Denk <wd@denx.de>2010-09-23 21:13:44 +0200
commitbab00b95b76d704878af0d70e66959c27bdf8f52 (patch)
treec5fb40b375a09032df70e8d2890033b1ccbc9970
parent9f530d59e63f6a4584e0caee54f92255c7ed59ab (diff)
downloadu-boot-linaro-stable-bab00b95b76d704878af0d70e66959c27bdf8f52.tar.gz
mpc83xx/pcie: make it compile with PCIE2 unconfigured
MPC8308 has only one PCIE host controller so we want it to compile without CONFIG_SYS_PCIE2_CFG_{BASE,SIZE} defined. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
-rw-r--r--arch/powerpc/cpu/mpc83xx/pcie.c38
1 files changed, 25 insertions, 13 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 77f8906b9..e70d19e20 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -30,6 +30,22 @@ DECLARE_GLOBAL_DATA_PTR;
#define PCIE_MAX_BUSES 2
+static struct {
+ u32 base;
+ u32 size;
+} mpc83xx_pcie_cfg_space[] = {
+ {
+ .base = CONFIG_SYS_PCIE1_CFG_BASE,
+ .size = CONFIG_SYS_PCIE1_CFG_SIZE,
+ },
+#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
+ {
+ .base = CONFIG_SYS_PCIE2_CFG_BASE,
+ .size = CONFIG_SYS_PCIE2_CFG_SIZE,
+ },
+#endif
+};
+
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
@@ -124,10 +140,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
hose->first_busno = pci_last_busno() + 1;
hose->last_busno = 0xff;
- if (bus == 0)
- hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
- else
- hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
+ hose->cfg_addr = mpc83xx_pcie_cfg_space[bus].base;
pci_set_ops(hose,
pcie_read_config_byte,
@@ -182,15 +195,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
PEX_CSB_OBCTRL_CFGWE);
out_win = &pex->bridge.pex_outbound_win[0];
- if (bus) {
- out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
- CONFIG_SYS_PCIE2_CFG_SIZE);
- out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
- } else {
- out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
- CONFIG_SYS_PCIE1_CFG_SIZE);
- out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
- }
+ out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
+ mpc83xx_pcie_cfg_space[bus].size);
+ out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
out_le32(&out_win->tarl, 0);
out_le32(&out_win->tarh, 0);
@@ -312,6 +319,11 @@ void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
*/
udelay(warmboot ? 1000 : 100000);
+ if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
+ printf("Second PCIE host contoller not configured!\n");
+ num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
+ }
+
for (i = 0; i < num_buses; i++)
mpc83xx_pcie_init_bus(i, reg[i]);
}