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authorYork Sun <yorksun@freescale.com>2012-05-07 07:26:45 +0000
committerAndy Fleming <afleming@freescale.com>2012-07-06 17:30:33 -0500
commit1e9ea85f7dffe949ca5e4845e6336810c144e06d (patch)
treeb0dd4cf4a6f7cb05031c67242660fcfac0af8fcb
parent7b6e80538b919c814c94ce8887cec7b892f98a71 (diff)
downloadu-boot-linaro-stable-1e9ea85f7dffe949ca5e4845e6336810c144e06d.tar.gz
powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c8
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S8
3 files changed, 15 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2ed5a9842..d7a62e9c7 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -51,7 +51,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
puts("Work-around for Erratum SERDES-A005 enabled\n");
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- puts("Work-around for Erratum CPU22 enabled\n");
+ if (SVR_MAJ(svr) < 3)
+ puts("Work-around for Erratum CPU22 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
puts("Work-around for Erratum CPU-A003999 enabled\n");
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e7b2d3779..b64eda3eb 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -309,9 +309,11 @@ int cpu_init_r(void)
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
- flush_dcache();
- mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
- sync();
+ if (SVR_MAJ(svr) < 3) {
+ flush_dcache();
+ mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+ sync();
+ }
#endif
puts ("L2: ");
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index c81e19c0e..fe3b6d6cb 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -144,9 +144,17 @@ __secondary_start_page:
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+ /* apply to P4080 rev 1 and rev 2 */
+ mfspr r3,SPRN_SVR
+ rlwinm r3,r3,0,0xf0
+ li r4,0x30
+ cmpw r3,r4
+ bge 2f
+
mfspr r8,L1CSR2
oris r8,r8,(L1CSR2_DCWS)@h
mtspr L1CSR2,r8
+2:
#endif
#ifdef CONFIG_BACKSIDE_L2_CACHE