diff options
author | Jaehoon Chung <jh80.chung@samsung.com> | 2012-07-03 13:57:52 +0900 |
---|---|---|
committer | John Rigby <john.rigby@linaro.org> | 2012-12-06 13:51:45 -0700 |
commit | 0b1c7d66e7e218f88096378dfa34eb8950c78742 (patch) | |
tree | aff98c9216f55068b1631fee81cbc8dd6bf5ea98 | |
parent | b179eb06a0d403e8c7b05ada5251e09918ece3b1 (diff) |
EXYNOS: clock: add the get_mmc_clk function
To get more exactly sclk value, used the get_mmc_clk.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
-rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 78 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-exynos/clk.h | 1 |
2 files changed, 79 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 002a49390..1c5ec96a4 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -457,6 +457,44 @@ static unsigned long exynos5_get_uart_clk(int dev_index) return uclk; } +/* exynos4: return mmc clock frequency */ +static unsigned long exynos4_get_mmc_clk(int dev_index) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + if (dev_index == 0) { + ratio = readl(&clk->div_fsys0); + pre_ratio = readl(&clk->div_fsys0); + } else if (dev_index == 4) { + ratio = readl(&clk->div_fsys3); + pre_ratio = readl(&clk->div_fsys3); + } else + return 0; + + ratio = ratio & 0xf; + pre_ratio = (pre_ratio >> (dev_index + 8)) & 0xff; + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + return uclk; +} + /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -484,6 +522,38 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos5: return mmc clock frequency */ +static unsigned long exynos5_get_mmc_clk(int dev_index) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + unsigned int pre_ratio; + + sel = readl(&clk->src_fsys); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + ratio = readl(&clk->div_fsys1); + ratio = (ratio >> (dev_index << 2)) & 0xf; + pre_ratio = readl(&clk->div_fsys1); + pre_ratio = (pre_ratio >> ((dev_index<< 4) + 8)) & 0xff; + + uclk = (sclk /(ratio + 1))/(pre_ratio + 1); + + return uclk; +} + /* exynos5: set the mmc clock */ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) { @@ -849,6 +919,14 @@ unsigned long get_uart_clk(int dev_index) return exynos4_get_uart_clk(dev_index); } +unsigned long get_mmc_clk(int dev_index) +{ + if (cpu_is_exynos5()) + return exynos5_get_mmc_clk(dev_index); + else + return exynos4_get_mmc_clk(dev_index); +} + void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 552902573..e015668d6 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -33,6 +33,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); +unsigned long get_mmc_clk(int dev_index); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); unsigned long get_lcd_clk(void); |