aboutsummaryrefslogtreecommitdiff
path: root/sim-neg-4s-trace-arm64.h
blob: 1471d00e641899f2da1996adbcd36aaa294a96fa (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//   * Redistributions of source code must retain the above copyright notice,
//     this list of conditions and the following disclaimer.
//   * Redistributions in binary form must reproduce the above copyright notice,
//     this list of conditions and the following disclaimer in the documentation
//     and/or other materials provided with the distribution.
//   * Neither the name of ARM Limited nor the names of its contributors may be
//     used to endorse or promote products derived from this software without
//     specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------

#ifndef VIXL_SIM_NEG_4S_TRACE_AARCH64_H_
#define VIXL_SIM_NEG_4S_TRACE_AARCH64_H_

const uint32_t kExpected_NEON_neg_4S[] = {
  0x00000003, 0x00000002, 0x00000001, 0x00000000,
  0x00000002, 0x00000001, 0x00000000, 0xffffffff,
  0x00000001, 0x00000000, 0xffffffff, 0xfffffffe,
  0x00000000, 0xffffffff, 0xfffffffe, 0xffffffe0,
  0xffffffff, 0xfffffffe, 0xffffffe0, 0xffffff83,
  0xfffffffe, 0xffffffe0, 0xffffff83, 0xffffff82,
  0xffffffe0, 0xffffff83, 0xffffff82, 0xffffff81,
  0xffffff83, 0xffffff82, 0xffffff81, 0xffff8003,
  0xffffff82, 0xffffff81, 0xffff8003, 0xffff8002,
  0xffffff81, 0xffff8003, 0xffff8002, 0xffff8001,
  0xffff8003, 0xffff8002, 0xffff8001, 0xcccccccd,
  0xffff8002, 0xffff8001, 0xcccccccd, 0xaaaaaaab,
  0xffff8001, 0xcccccccd, 0xaaaaaaab, 0x80000003,
  0xcccccccd, 0xaaaaaaab, 0x80000003, 0x80000002,
  0xaaaaaaab, 0x80000003, 0x80000002, 0x80000001,
  0x80000003, 0x80000002, 0x80000001, 0x80000000,
  0x80000002, 0x80000001, 0x80000000, 0x7fffffff,
  0x80000001, 0x80000000, 0x7fffffff, 0x55555556,
  0x80000000, 0x7fffffff, 0x55555556, 0x33333334,
  0x7fffffff, 0x55555556, 0x33333334, 0x00008000,
  0x55555556, 0x33333334, 0x00008000, 0x00007fff,
  0x33333334, 0x00008000, 0x00007fff, 0x00007ffe,
  0x00008000, 0x00007fff, 0x00007ffe, 0x00007ffd,
  0x00007fff, 0x00007ffe, 0x00007ffd, 0x00000080,
  0x00007ffe, 0x00007ffd, 0x00000080, 0x0000007f,
  0x00007ffd, 0x00000080, 0x0000007f, 0x0000007e,
  0x00000080, 0x0000007f, 0x0000007e, 0x0000007d,
  0x0000007f, 0x0000007e, 0x0000007d, 0x00000020,
  0x0000007e, 0x0000007d, 0x00000020, 0x00000003,
  0x0000007d, 0x00000020, 0x00000003, 0x00000002,
  0x00000020, 0x00000003, 0x00000002, 0x00000001,
};
const unsigned kExpectedCount_NEON_neg_4S = 31;

#endif  // VIXL_SIM_NEG_4S_TRACE_AARCH64_H_