blob: 19d551dab2b9ab45b06b82582c1ee258db2be1ad (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
|
/** @file
* Header defining Versatile Express constants (Base addresses, sizes, flags)
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __ARM_VEXPRESS_H__
#define __ARM_VEXPRESS_H__
#include <Base.h>
#include <VExpressMotherBoard.h>
/***********************************************************************************
// Platform Memory Map
************************************************************************************/
// Can be NOR0, NOR1, DRAM
#define ARM_VE_REMAP_BASE 0x00000000
#define ARM_VE_REMAP_SZ SIZE_64MB
// Motherboard Peripheral and On-chip peripheral
#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x1C000000
#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB
#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
#define ARM_VE_CHIP_PERIPH_BASE 0x2A000000
// SMC
#define ARM_VE_SMC_BASE 0x08000000
#define ARM_VE_SMC_SZ 0x1C000000
// NOR Flash 1
// There is typo in the reference manual for the Base address of NOR Flash 1
#define ARM_VE_SMB_NOR0_BASE 0x08000000
#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
// NOR Flash 2
#define ARM_VE_SMB_NOR1_BASE 0x0C000000
#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
// SRAM
#define ARM_VE_SMB_SRAM_BASE 0x2E000000
#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
// USB, Ethernet, VRAM
#define ARM_VE_SMB_PERIPH_BASE 0x18000000
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
// DRAM
#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)
#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)
// This can be any value since we only support motherboard PL111
#define LCD_VRAM_CORE_TILE_BASE 0x84000000
// On-chip peripherals (Snoop Control Unit etc...)
#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000
// Note: The TRM says not all the peripherals are implemented
#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB
// External AXI between daughterboards (Logic Tile)
#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled
#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
/***********************************************************************************
Core Tile memory-mapped Peripherals
************************************************************************************/
// SP810 Controller
#undef SP810_CTRL_BASE
#define SP810_CTRL_BASE 0x1C020000
// PL111 Colour LCD Controller
#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
// PL341 Dynamic Memory Controller Base
#define ARM_VE_DMC_BASE (0x2B0A0000)
// PL354 Static Memory Controller Base
#define ARM_VE_SMC_CTRL_BASE (0x7FFD0000)
// SCC Base
#define ARM_VE_SCC_BASE (0x7FFF0000)
// VRAM offset for the PL111 Colour LCD Controller on the motherboard
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
#endif
|
