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authorJuan Castillo <juan.castillo@arm.com>2014-06-13 17:05:10 +0100
committerJuan Castillo <juan.castillo@arm.com>2014-06-24 12:50:00 +0100
commit4f2104ff20753d78af0058e3ca5e9e042cd707af (patch)
tree82c3050940f816e3de424958d23bfa691b44b152
parent41cf7bdfd7114ee437d165974367a483636df76d (diff)
downloadarm-trusted-firmware-4f2104ff20753d78af0058e3ca5e9e042cd707af.tar.gz
Remove all checkpatch errors from codebase
Exclude stdlib files because they do not follow kernel code style. Fixes ARM-software/tf-issues#73 Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
-rw-r--r--Makefile4
-rw-r--r--bl1/aarch64/bl1_arch_setup.c3
-rw-r--r--bl31/bl31_main.c4
-rw-r--r--bl31/context_mgmt.c2
-rw-r--r--bl31/runtime_svc.c2
-rw-r--r--bl32/tsp/tsp_interrupt.c4
-rw-r--r--bl32/tsp/tsp_timer.c10
-rw-r--r--include/bl31/bl31.h2
-rw-r--r--include/bl31/runtime_svc.h2
-rw-r--r--include/lib/aarch64/arch_helpers.h4
-rw-r--r--include/plat/common/platform.h4
-rw-r--r--plat/common/aarch64/plat_common.c4
-rw-r--r--plat/fvp/bl2_fvp_setup.c2
-rw-r--r--plat/fvp/bl31_fvp_setup.c4
-rw-r--r--plat/fvp/bl32_fvp_setup.c4
-rw-r--r--plat/fvp/fvp_gic.c6
-rw-r--r--plat/fvp/fvp_topology.c4
-rw-r--r--services/std_svc/psci/psci_common.c2
18 files changed, 34 insertions, 33 deletions
diff --git a/Makefile b/Makefile
index 9131f1c..7b5288d 100644
--- a/Makefile
+++ b/Makefile
@@ -234,9 +234,9 @@ realclean distclean:
checkcodebase: locate-checkpatch
@echo " CHECKING STYLE"
@if test -d .git ; then \
- git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
+ git ls-files | grep -v stdlib | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
else \
- find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
+ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -not -iwholename "*stdlib*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
fi
checkpatch: locate-checkpatch
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c
index 8ed45d9..cf69ac7 100644
--- a/bl1/aarch64/bl1_arch_setup.c
+++ b/bl1/aarch64/bl1_arch_setup.c
@@ -62,7 +62,8 @@ void bl1_arch_setup(void)
/*******************************************************************************
* Set the Secure EL1 required architectural state
******************************************************************************/
-void bl1_arch_next_el_setup(void) {
+void bl1_arch_next_el_setup(void)
+{
unsigned long next_sctlr;
/* Use the same endianness than the current BL */
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 8cc7e0d..d949a08 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -56,7 +56,7 @@ static uint32_t next_image_type;
/*******************************************************************************
* Simple function to initialise all BL31 helper libraries.
******************************************************************************/
-void bl31_lib_init()
+void bl31_lib_init(void)
{
cm_init();
}
@@ -137,7 +137,7 @@ uint32_t bl31_get_next_image_type(void)
* This function programs EL3 registers and performs other setup to enable entry
* into the next image after BL31 at the next ERET.
******************************************************************************/
-void bl31_prepare_next_image_entry()
+void bl31_prepare_next_image_entry(void)
{
entry_point_info_t *next_image_info;
uint32_t image_type;
diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c
index 81c7c56..65f1213 100644
--- a/bl31/context_mgmt.c
+++ b/bl31/context_mgmt.c
@@ -56,7 +56,7 @@
* which will used for programming an entry into a lower EL. The same context
* will used to save state upon exception entry from that EL.
******************************************************************************/
-void cm_init()
+void cm_init(void)
{
/*
* The context management library has only global data to intialize, but
diff --git a/bl31/runtime_svc.c b/bl31/runtime_svc.c
index 08cd2d8..c33748f 100644
--- a/bl31/runtime_svc.c
+++ b/bl31/runtime_svc.c
@@ -78,7 +78,7 @@ static int32_t validate_rt_svc_desc(rt_svc_desc_t *desc)
* The unique oen is used as an index into the 'rt_svc_descs_indices' array.
* The index of the runtime service descriptor is stored at this index.
******************************************************************************/
-void runtime_svc_init()
+void runtime_svc_init(void)
{
int32_t rc = 0;
uint32_t index, start_idx, end_idx;
diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c
index 4a4b877..ff6bdc5 100644
--- a/bl32/tsp/tsp_interrupt.c
+++ b/bl32/tsp/tsp_interrupt.c
@@ -72,7 +72,7 @@ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3)
* architecture version in v2.0 and the secure physical timer interrupt is the
* only S-EL1 interrupt that it needs to handle.
******************************************************************************/
-int32_t tsp_fiq_handler()
+int32_t tsp_fiq_handler(void)
{
uint64_t mpidr = read_mpidr();
uint32_t linear_id = platform_get_core_pos(mpidr), id;
@@ -109,7 +109,7 @@ int32_t tsp_fiq_handler()
return 0;
}
-int32_t tsp_irq_received()
+int32_t tsp_irq_received(void)
{
uint64_t mpidr = read_mpidr();
uint32_t linear_id = platform_get_core_pos(mpidr);
diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c
index 366640f..a7fdfda 100644
--- a/bl32/tsp/tsp_timer.c
+++ b/bl32/tsp/tsp_timer.c
@@ -46,7 +46,7 @@ static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT];
/*******************************************************************************
* This function initializes the generic timer to fire every 0.5 second
******************************************************************************/
-void tsp_generic_timer_start()
+void tsp_generic_timer_start(void)
{
uint64_t cval;
uint32_t ctl = 0;
@@ -63,7 +63,7 @@ void tsp_generic_timer_start()
/*******************************************************************************
* This function deasserts the timer interrupt and sets it up again
******************************************************************************/
-void tsp_generic_timer_handler()
+void tsp_generic_timer_handler(void)
{
/* Ensure that the timer did assert the interrupt */
assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
@@ -76,7 +76,7 @@ void tsp_generic_timer_handler()
/*******************************************************************************
* This function deasserts the timer interrupt prior to cpu power down
******************************************************************************/
-void tsp_generic_timer_stop()
+void tsp_generic_timer_stop(void)
{
/* Disable the timer */
write_cntps_ctl_el1(0);
@@ -85,7 +85,7 @@ void tsp_generic_timer_stop()
/*******************************************************************************
* This function saves the timer context prior to cpu suspension
******************************************************************************/
-void tsp_generic_timer_save()
+void tsp_generic_timer_save(void)
{
uint32_t linear_id = platform_get_core_pos(read_mpidr());
@@ -98,7 +98,7 @@ void tsp_generic_timer_save()
/*******************************************************************************
* This function restores the timer context post cpu resummption
******************************************************************************/
-void tsp_generic_timer_restore()
+void tsp_generic_timer_restore(void)
{
uint32_t linear_id = platform_get_core_pos(read_mpidr());
diff --git a/include/bl31/bl31.h b/include/bl31/bl31.h
index 33e4ece..96867b0 100644
--- a/include/bl31/bl31.h
+++ b/include/bl31/bl31.h
@@ -40,7 +40,7 @@ void bl31_arch_setup(void);
void bl31_next_el_arch_setup(uint32_t security_state);
void bl31_set_next_image_type(uint32_t type);
uint32_t bl31_get_next_image_type(void);
-void bl31_prepare_next_image_entry();
+void bl31_prepare_next_image_entry(void);
void bl31_register_bl32_init(int32_t (*)(void));
#endif /* __BL31_H__ */
diff --git a/include/bl31/runtime_svc.h b/include/bl31/runtime_svc.h
index f3543d4..2d84986 100644
--- a/include/bl31/runtime_svc.h
+++ b/include/bl31/runtime_svc.h
@@ -264,7 +264,7 @@ CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
-void runtime_svc_init();
+void runtime_svc_init(void);
extern uint64_t __RT_SVC_DESCS_START__;
extern uint64_t __RT_SVC_DESCS_END__;
void init_crash_reporting(void);
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 673e897..6ba37c2 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -85,14 +85,14 @@ static inline void write_ ## _name(const uint64_t v) \
/* Define function for simple system instruction */
#define DEFINE_SYSOP_FUNC(_op) \
-static inline void _op() \
+static inline void _op(void) \
{ \
__asm__ (#_op); \
}
/* Define function for system instruction with type specifier */
#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
-static inline void _op ## _type() \
+static inline void _op ## _type(void) \
{ \
__asm__ (#_op " " #_type); \
}
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 714f6e0..c087dc6 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -165,7 +165,7 @@ unsigned int plat_get_aff_state(unsigned int, unsigned long);
/*******************************************************************************
* Optional BL3-1 functions (may be overridden)
******************************************************************************/
-void bl31_plat_enable_mmu();
+void bl31_plat_enable_mmu(void);
/*******************************************************************************
* Mandatory BL3-2 functions (only if platform contains a BL3-2)
@@ -175,6 +175,6 @@ void bl32_platform_setup(void);
/*******************************************************************************
* Optional BL3-2 functions (may be overridden)
******************************************************************************/
-void bl32_plat_enable_mmu();
+void bl32_plat_enable_mmu(void);
#endif /* __PLATFORM_H__ */
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 2abf29d..94b9dfd 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -38,12 +38,12 @@
#pragma weak bl31_plat_enable_mmu
#pragma weak bl32_plat_enable_mmu
-void bl31_plat_enable_mmu()
+void bl31_plat_enable_mmu(void)
{
enable_mmu_el3();
}
-void bl32_plat_enable_mmu()
+void bl32_plat_enable_mmu(void)
{
enable_mmu_el1();
}
diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c
index de9c6a4..a030bd5 100644
--- a/plat/fvp/bl2_fvp_setup.c
+++ b/plat/fvp/bl2_fvp_setup.c
@@ -212,7 +212,7 @@ void bl2_plat_flush_bl31_params(void)
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
-void bl2_plat_arch_setup()
+void bl2_plat_arch_setup(void)
{
fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
diff --git a/plat/fvp/bl31_fvp_setup.c b/plat/fvp/bl31_fvp_setup.c
index 6554ec3..50ed0b0 100644
--- a/plat/fvp/bl31_fvp_setup.c
+++ b/plat/fvp/bl31_fvp_setup.c
@@ -167,7 +167,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
* Initialize the gic, configure the CLCD and zero out variables needed by the
* secondaries to boot up correctly.
******************************************************************************/
-void bl31_platform_setup()
+void bl31_platform_setup(void)
{
unsigned int reg_val;
@@ -207,7 +207,7 @@ void bl31_platform_setup()
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
-void bl31_plat_arch_setup()
+void bl31_plat_arch_setup(void)
{
#if RESET_TO_BL31
fvp_cci_setup();
diff --git a/plat/fvp/bl32_fvp_setup.c b/plat/fvp/bl32_fvp_setup.c
index f8dc3c7..3c09ca2 100644
--- a/plat/fvp/bl32_fvp_setup.c
+++ b/plat/fvp/bl32_fvp_setup.c
@@ -81,7 +81,7 @@ void bl32_early_platform_setup(void)
/*******************************************************************************
* Perform platform specific setup placeholder
******************************************************************************/
-void bl32_platform_setup()
+void bl32_platform_setup(void)
{
}
@@ -90,7 +90,7 @@ void bl32_platform_setup()
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the MMU
******************************************************************************/
-void bl32_plat_arch_setup()
+void bl32_plat_arch_setup(void)
{
fvp_configure_mmu_el1(BL32_RO_BASE,
(BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
diff --git a/plat/fvp/fvp_gic.c b/plat/fvp/fvp_gic.c
index 3156da9..a48b29b 100644
--- a/plat/fvp/fvp_gic.c
+++ b/plat/fvp/fvp_gic.c
@@ -324,7 +324,7 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
* interrupt pending.
******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_type()
+uint32_t plat_ic_get_pending_interrupt_type(void)
{
uint32_t id, gicc_base;
@@ -346,7 +346,7 @@ uint32_t plat_ic_get_pending_interrupt_type()
* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
* interrupt pending.
******************************************************************************/
-uint32_t plat_ic_get_pending_interrupt_id()
+uint32_t plat_ic_get_pending_interrupt_id(void)
{
uint32_t id, gicc_base;
@@ -370,7 +370,7 @@ uint32_t plat_ic_get_pending_interrupt_id()
* This functions reads the GIC cpu interface Interrupt Acknowledge register
* to start handling the pending interrupt. It returns the contents of the IAR.
******************************************************************************/
-uint32_t plat_ic_acknowledge_interrupt()
+uint32_t plat_ic_acknowledge_interrupt(void)
{
return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR));
}
diff --git a/plat/fvp/fvp_topology.c b/plat/fvp/fvp_topology.c
index cf21503..49f7daf 100644
--- a/plat/fvp/fvp_topology.c
+++ b/plat/fvp/fvp_topology.c
@@ -180,7 +180,7 @@ unsigned int plat_get_aff_state(unsigned int aff_lvl,
* Handy optimization to prevent the psci implementation from traversing through
* affinity levels which are not present while detecting the platform topology.
******************************************************************************/
-int plat_get_max_afflvl()
+int plat_get_max_afflvl(void)
{
return MPIDR_AFFLVL1;
}
@@ -190,7 +190,7 @@ int plat_get_max_afflvl()
* the FVP flavour its running on. We construct all the mpidrs we can handle
* and rely on the PWRC.PSYSR to flag absent cpus when their status is queried.
******************************************************************************/
-int fvp_setup_topology()
+int fvp_setup_topology(void)
{
unsigned char aff0, aff1, aff_state, aff0_offset = 0;
unsigned long mpidr;
diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c
index 87be843..23235d3 100644
--- a/services/std_svc/psci/psci_common.c
+++ b/services/std_svc/psci/psci_common.c
@@ -98,7 +98,7 @@ int get_power_on_target_afflvl(unsigned long mpidr)
* Simple routine to retrieve the maximum affinity level supported by the
* platform and check that it makes sense.
******************************************************************************/
-int get_max_afflvl()
+int get_max_afflvl(void)
{
int aff_lvl;