diff options
| author | Dave Airlie <airlied@redhat.com> | 2012-06-27 08:35:54 +0100 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2012-07-19 22:30:32 -0400 |
| commit | 197bbb3d464f33eac1b458e83c1929d2f268d4c9 (patch) | |
| tree | fdbbe5d8515307772fbce4ef30ff1d55300d8275 /drivers/gpu/drm/radeon/evergreen.c | |
| parent | f42977841f4a28b82820384fdb9b9581b410dbb1 (diff) | |
drm/radeon/kms: auto detect pcie link speed from root port
This check the root ports supported link speeds and enables
GEN2 mode if the 5.0 GT link speed is available.
The first 3.0 cards are SI so they will probably need more investigation.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 14098ace1569..e585a3b947eb 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -3421,7 +3421,8 @@ void evergreen_fini(struct radeon_device *rdev) void evergreen_pcie_gen2_enable(struct radeon_device *rdev) { - u32 link_width_cntl, speed_cntl; + u32 link_width_cntl, speed_cntl, mask; + int ret; if (radeon_pcie_gen2 == 0) return; @@ -3436,6 +3437,15 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) if (ASIC_IS_X2(rdev)) return; + ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); + if (ret != 0) + return; + + if (!(mask & DRM_PCIE_SPEED_50)) + return; + + DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); + speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |