diff options
Diffstat (limited to 'daemon/events-Cortex-A15.xml')
| -rw-r--r-- | daemon/events-Cortex-A15.xml | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/daemon/events-Cortex-A15.xml b/daemon/events-Cortex-A15.xml index e0bd201..e3de814 100644 --- a/daemon/events-Cortex-A15.xml +++ b/daemon/events-Cortex-A15.xml @@ -1,6 +1,6 @@ <counter_set name="ARM_Cortex-A15_cnt" count="6"/> <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cnt" per_cpu="yes" supports_event_based_sampling="yes"> - <event counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> + <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/> <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/> <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/> <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/> @@ -19,13 +19,13 @@ <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/> <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/> <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/> - <event event="0x19" title="Bus" name="Access" description=""/> + <event event="0x19" title="Bus" name="Access" description="Bus - Access"/> <event event="0x1a" title="Memory" name="Error" description="Local memory error"/> <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/> <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/> - <event event="0x1d" title="Bus" name="Cycle" description=""/> + <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/> <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/> - <event event="0x41" title="Cache" name="L1 data write" description="Level 1 data cache access - Write"/> + <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/> <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/> <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/> <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/> @@ -34,7 +34,7 @@ <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/> <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/> <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/> - <event event="0x51" title="Cache" name="L2 data write" description="Level 2 data cache access - Write"/> + <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/> <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/> <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/> <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/> @@ -42,7 +42,7 @@ <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/> <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/> <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/> - <event event="0x64" title="Bus" name="Access" description="Bus access - Normal"/> + <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/> <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/> <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/> <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/> |