diff options
Diffstat (limited to 'big-little/virtualisor/virt_handle.c')
| -rw-r--r-- | big-little/virtualisor/virt_handle.c | 29 |
1 files changed, 20 insertions, 9 deletions
diff --git a/big-little/virtualisor/virt_handle.c b/big-little/virtualisor/virt_handle.c index 092af67..da163cf 100644 --- a/big-little/virtualisor/virt_handle.c +++ b/big-little/virtualisor/virt_handle.c @@ -180,20 +180,32 @@ void trap_cp15_mrc_mcr_handle(unsigned hsr, gp_regs * regs) switch (CRm) { case 0: switch (Op2) { + unsigned csselr, level, ind; case CCSIDR: if (write) goto error; + /* + * The L1 instruction cache CCSIDR + * value is incorrectly set on A7 and + * A15 for Virtualizer configuration + * [BC=x, TC=A15, HC=A7]. + * The error is later corrected in the + * A7 or A15 specific trap function. + */ + csselr = target_cache_geometry[cpu_id]. + csselr; + level = get_cache_level(csselr); + ind = get_cache_ind(csselr); regs->r[Rt] = - target_cache_geometry[cpu_id].ccsidr - [get_cache_level - (target_cache_geometry - [cpu_id].csselr)]; + target_cache_geometry[cpu_id]. + ccsidr[level][ind]; break; case CLIDR: if (write) goto error; regs->r[Rt] = - target_cache_geometry[cpu_id].clidr; + target_cache_geometry[cpu_id]. + clidr; break; case AIDR: if (write) @@ -215,14 +227,13 @@ void trap_cp15_mrc_mcr_handle(unsigned hsr, gp_regs * regs) case CSSELR: if (write) { target_cache_geometry - [cpu_id].csselr = - regs->r[Rt]; + [cpu_id].csselr = regs->r[Rt]; write_csselr(regs->r[Rt]); } else regs->r[Rt] = - target_cache_geometry - [cpu_id].csselr; + target_cache_geometry + [cpu_id].csselr; break; default: goto error; |