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-rw-r--r--big-little/include/arm.h70
-rw-r--r--big-little/include/bakery.h53
-rw-r--r--big-little/include/bl.h47
-rw-r--r--big-little/include/context.h133
-rw-r--r--big-little/include/events.h78
-rw-r--r--big-little/include/gic_registers.h102
-rw-r--r--big-little/include/handler.h32
-rw-r--r--big-little/include/hvc.h44
-rw-r--r--big-little/include/hyp_types.h38
-rw-r--r--big-little/include/hyp_vmmap.h42
-rw-r--r--big-little/include/int_master.h50
-rw-r--r--big-little/include/misc.h404
-rw-r--r--big-little/include/traps.h102
-rw-r--r--big-little/include/vgiclib.h51
-rw-r--r--big-little/include/virt_helpers.h98
15 files changed, 1344 insertions, 0 deletions
diff --git a/big-little/include/arm.h b/big-little/include/arm.h
new file mode 100644
index 0000000..7db58ce
--- /dev/null
+++ b/big-little/include/arm.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef ARM_H
+#define ARM_H
+
+/*
+ * File for ARM Architecture specific defines and constants
+ */
+#define CP15CTL_M 0x1
+#define CP15CTL_A 0x2
+#define CP15CTL_C 0x4
+#define CP15CTL_W 0x8
+/*
+ * 4:6 SBO
+ */
+#define CP15CTL_B 0x80
+#define CP15CTL_S 0x100
+#define CP15CTL_R 0x200
+#define CP15CTL_F 0x400
+#define CP15CTL_Z 0x800
+#define CP15CTL_I 0x1000
+#define CP15CTL_V 0x2000
+#define CP15CTL_RR 0x4000
+#define CP15CTL_L4 0x8000
+
+#define FSR_XTABT_L1 0x0C
+#define FSR_XTABT_L2 0x0E
+
+#define FSR_SECTRANS 0x05
+#define FSR_PAGETRANS 0x07
+
+/*
+ * These macros extract the page/section numbers from an address
+ */
+#define pagenum(x) (((x) >> 12) & 0xFF)
+#define secnum(x) ((x) >> 21) /* i$$NEW$$ */
+//#define secnum(x) ((x) >> 20) /* orig */
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_ABT 0x17
+#define MODE_UND 0x1D
+#define MODE_SYS 0x1F
+#define MODE_MON 0x16
+
+#define getmode(x) ((x) & 0x1F)
+
+#endif
diff --git a/big-little/include/bakery.h b/big-little/include/bakery.h
new file mode 100644
index 0000000..e8b9ecc
--- /dev/null
+++ b/big-little/include/bakery.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+#ifndef _BAKERY_H_
+#define _BAKERY_H_
+
+#define MAX_CPUS 4
+
+/*
+ * Bakery structure - declare/allocate one of these for each lock.
+ * A pointer to this struct is passed to the lock/unlock functions.
+ */
+typedef struct {
+ volatile char entering[MAX_CPUS];
+ volatile unsigned number[MAX_CPUS];
+} bakery_t;
+
+/*
+ * Initialize a bakery - only required if the bakery_t is
+ * on the stack or heap, as static data is zeroed anyway.
+ */
+extern void init_bakery_spinlock(bakery_t * bakery);
+
+/*
+ * Claim a bakery lock. Function does not return until
+ * lock has been obtained.
+ */
+extern void get_bakery_spinlock(unsigned cpuid, bakery_t * bakery);
+
+/*
+ * Release a bakery lock.
+ */
+extern void release_bakery_spinlock(unsigned cpuid, bakery_t * bakery);
+
+#endif /* _BAKERY_H_ */
diff --git a/big-little/include/bl.h b/big-little/include/bl.h
new file mode 100644
index 0000000..700afa2
--- /dev/null
+++ b/big-little/include/bl.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __BL_H__
+#define __BL_H__
+
+#include "misc.h"
+
+typedef struct vm_c {
+ unsigned gp_regs[15];
+ unsigned elr_hyp;
+ unsigned spsr;
+ unsigned usr_lr;
+} vm_context;
+
+/*
+ * VM context structure: To hold execution context of the preceding
+ * mode upon entry into the HYP mode synchronously/asynchronously.
+ */
+typedef struct vm_s {
+ unsigned stack[STACK_SIZE];
+ vm_context context;
+} vm_state;
+
+extern vm_state guestos_state[MAX_CPUIFS];
+extern void bl_setup(void);
+extern void hyp_warm_reset_handler(void);
+#endif /* __BL_H__ */
diff --git a/big-little/include/context.h b/big-little/include/context.h
new file mode 100644
index 0000000..17656a8
--- /dev/null
+++ b/big-little/include/context.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __CONTEXT_H__
+#define __CONTEXT_H__
+
+#include "misc.h"
+
+typedef struct ns_gic_cpu_context {
+ unsigned int gic_cpu_if_regs[32]; /* GIC context local to the CPU */
+ unsigned int gic_dist_if_pvt_regs[32]; /* GIC SGI/PPI context local to the CPU */
+} gic_cpu_context;
+
+typedef struct fault_regs {
+ unsigned dfar;
+ unsigned ifar;
+ unsigned ifsr;
+ unsigned dfsr;
+ unsigned adfsr;
+ unsigned aifsr;
+} cp15_fault_regs;
+
+typedef struct ns_banked_cp15_context {
+ unsigned int cp15_misc_regs[2]; /* cp15 miscellaneous registers */
+ unsigned int cp15_ctrl_regs[20]; /* cp15 control registers */
+ unsigned int cp15_mmu_regs[16]; /* cp15 mmu registers */
+ cp15_fault_regs ns_cp15_fault_regs; /* cp15 fault status registers */
+} banked_cp15_context;
+
+typedef struct gen_tmr_ctx {
+ unsigned cntfrq;
+ unsigned long long cntvoff;
+ unsigned cnthctl;
+ unsigned cntkctl;
+ unsigned long long cntp_cval;
+ unsigned cntp_tval;
+ unsigned cntp_ctl;
+ unsigned long long cntv_cval;
+ unsigned cntv_tval;
+ unsigned cntv_ctl;
+ unsigned long long cnthp_cval;
+ unsigned cnthp_tval;
+ unsigned cnthp_ctl;
+} generic_timer_context;
+
+typedef struct ns_cpu_context {
+ unsigned int banked_cpu_regs[32]; /* Banked cpu registers */
+ banked_cp15_context banked_cp15_regs; /* Per cpu banked cp15 context */
+ unsigned int pmon_regs[32]; /* Generic performance monitor registers */
+ generic_timer_context cp15_timer_ctx; /* Global counter registers if accessible in NS world */
+ gic_cpu_context gic_cpu_ctx; /* Per cpu GIC distributor and interface context */
+ unsigned int endianess; /* Per cpu endianess */
+ unsigned int vfp_regs[34]; /* Dummy entry for VFP context. */
+ unsigned int debug_regs[32]; /* Dummy entry for Debug context. TODO */
+} cpu_context;
+
+typedef struct ns_global_context {
+ unsigned int gic_dist_if_regs[512]; /* GIC distributor context to be saved by the last cpu. */
+ unsigned int generic_timer_regs[8]; /* Global timers if the NS world has access to them */
+} global_context;
+
+/*
+ * Structure to preserve the OS mmu and stack state for swtich from OS to Switcher
+ * context handler.
+ */
+typedef struct os_state {
+ unsigned sctlr;
+ unsigned dacr;
+ unsigned ttbr0;
+ unsigned nmrr;
+ unsigned prrr;
+} os_state;
+
+/*
+ * Top level structure to hold the complete context of a core in a cluster in
+ * a multi-cluster system
+ */
+typedef struct core_context {
+ /*
+ * Non-secure context save area
+ */
+ cpu_context ns_cpu_ctx;
+
+} core_context;
+
+/*
+ * Top level structure to hold the complete context of a cluster in a multi-
+ * cluster system
+ */
+typedef struct cluster_context {
+ core_context core[MAX_CORES];
+ unsigned num_cores;
+ global_context ns_cluster_ctx;
+} cluster_context;
+
+/*
+ * Top level structure to hold the complete context of a multi cluster system
+ */
+typedef struct system_context {
+ cluster_context cluster;
+ unsigned num_clusters;
+ unsigned warm_reset;
+} system_context;
+
+extern void context_save(unsigned, unsigned);
+extern void context_restore(unsigned, unsigned);
+extern void save_generic_timers(generic_timer_context *);
+extern void restore_eagle_timers(generic_timer_context *);
+extern void save_hyp_context(unsigned, unsigned);
+extern void restore_hyp_context(unsigned, unsigned);
+extern void save_vfp(unsigned *);
+extern void restore_vfp(unsigned *);
+extern void enable_trigger(unsigned);
+#endif /* __CONTEXT_H__ */
diff --git a/big-little/include/events.h b/big-little/include/events.h
new file mode 100644
index 0000000..d6523e3
--- /dev/null
+++ b/big-little/include/events.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __EVENTS_H__
+#define __EVENTS_H__
+
+#include "context.h"
+#include "virt_helpers.h"
+#include "misc.h"
+
+/*
+ * Events for inter/intra-cluster sync
+ */
+#define MAX_EVENTS 12
+
+/* Inter cluster events */
+#define IB_CONTEXT_DONE 0
+#define OB_CONTEXT_DONE 1
+
+/* Intra cluster events */
+#define L2_READY 2
+#define L1_DONE 3
+#define CCI_READY 4
+#define GIC_READY 5
+/* Cores have finished performing inbound headstart specific initialisation */
+#define HS_DONE 6
+/*
+ * Holding pen to ensure that all other context is restored only after all
+ * cpus have finished initialised local and global HYP mode context.
+ */
+#define HYP_CONTEXT_DONE 7
+/*
+ * Holding pen to ensure that all cores have setup the local and global
+ * virtualisor context before any one of them uses it
+ */
+#define VIRT_SETUP_DONE 8
+/*
+ * Event to synchronise creation of HYP mode pagetables
+ */
+#define VIRT_PGT_DONE 9
+
+#define CACHE_GEOM_DONE 10
+#define VID_REGS_DONE 11
+
+/* Defines for Secure events */
+#define MAX_SEC_EVENTS 4
+#define SEC_L1_DONE 0
+#define OB_SHUTDOWN 1
+#define FLUSH_L2 2
+#define SETUP_RST 3
+
+extern void set_event(unsigned, unsigned);
+extern void set_events(unsigned);
+extern unsigned get_event(unsigned, unsigned);
+extern void reset_event(unsigned, unsigned);
+extern void wait_for_event(unsigned, unsigned);
+extern void wait_for_events(unsigned);
+
+#endif /* __EVENTS_H__ */
diff --git a/big-little/include/gic_registers.h b/big-little/include/gic_registers.h
new file mode 100644
index 0000000..92ff5c0
--- /dev/null
+++ b/big-little/include/gic_registers.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __GIC_REGISTERS_H__
+#define __GIC_REGISTERS_H__
+
+#include "hyp_vmmap.h"
+
+#define MAX_INTS 256
+
+/* Distributor interface registers */
+#define GICD_CTL 0x0
+#define GICD_CTR 0x4
+#define GICD_SEC 0x80
+#define GICD_ENABLESET 0x100
+#define GICD_ENABLECLEAR 0x180
+#define GICD_PENDINGSET 0x200
+#define GICD_PENDINGCLEAR 0x280
+#define GICD_ACTIVESET 0x300
+#define GICD_ACTIVECLEAR 0x380
+#define GICD_PRI 0x400
+#define GICD_CPUS 0x800
+#define GICD_CONFIG 0xC00
+#define GICD_SW 0xF00
+#define GICD_CPENDSGIR 0xF10
+#define GICD_SPENDSGIR 0xF20
+
+/* Physical CPU Interface registers */
+#define GICC_CTL 0x0
+#define GICC_PRIMASK 0x4
+#define GICC_BP 0x8
+#define GICC_INTACK 0xC
+#define GICC_EOI 0x10
+#define GICC_RUNNINGPRI 0x14
+#define GICC_HIGHESTPEND 0x18
+#define GICC_DEACTIVATE 0x1000
+#define GICC_PRIODROP GICC_EOI
+
+/* HYP view virtual CPU Interface registers */
+#define GICH_CTL 0x0
+#define GICH_VTR 0x4
+#define GICH_ELRSR0 0x30
+#define GICH_ELRSR1 0x34
+#define GICH_APR0 0xF0
+#define GICH_LR_BASE 0x100
+
+/* GuestOS view virtual CPU Interface registers */
+#define GICV_CTL 0x0
+#define GICV_PRIMASK 0x4
+#define GICV_BP 0x8
+#define GICV_INTACK 0xC
+#define GICV_EOI 0x10
+#define GICV_RUNNINGPRI 0x14
+#define GICV_HIGHESTPEND 0x18
+#define GICV_DEACTIVATE 0x1000
+
+#define VGICH_HCR_EN 0x1
+#define VGICV_NS_EN 0x2
+
+#define GS_ENABLED 0x01
+#define GS_EDGE 0x02
+#define GIC_INTS 128
+#define GIC_PRIMASK 0xF8 /* 32 levels only */
+#define GIC_DISTENABLE 0x1
+#define GIC_CPUIFENABLE 0x2
+
+#define VGIC_PRI 0x200
+#define VGIC_LIST 0x100
+#define VGIC_CONTROL 0x0
+/*
+ * TODO:
+ * Current mechanism to find free slots uses unsigned ints
+ * and is thus restricted to storing just 32 free slots.
+ */
+#define VGIC_LISTENTRIES 64
+
+#define VGIC_ENTRY_HW 0x80000000
+#define VGIC_ENTRY_ACTIVE 0x20000000
+#define VGIC_ENTRY_ACTIVE_PENDING 0x30000000
+#define VGIC_ENTRY_PENDING 0x10000000
+
+#endif /* __GIC_REGISTERS_H__ */
+
diff --git a/big-little/include/handler.h b/big-little/include/handler.h
new file mode 100644
index 0000000..747b31c
--- /dev/null
+++ b/big-little/include/handler.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __HANDLER_H__
+#define __HANDLER_H__
+
+#include "virt_helpers.h"
+#include "context.h"
+#include "misc.h"
+
+extern system_context switcher_context;
+
+#endif /* __HANDLER_H__ */
diff --git a/big-little/include/hvc.h b/big-little/include/hvc.h
new file mode 100644
index 0000000..1f71271
--- /dev/null
+++ b/big-little/include/hvc.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __HVC_H__
+#define __HVC_H__
+
+#include "traps.h"
+#include "handler.h"
+#include "context.h"
+#include "int_master.h"
+
+/* Opcode to trigger a switch from the OS */
+#define SWITCHER_ENTRY 0
+/* Opcode to return to the trigger handler after a switch (NS SVC -> HYP) */
+#define SWITCHER_EXIT 1
+/* Opcode to save HYP mode context */
+#define HYP_SAVE 2
+/* Opcode to restore HYP mode context */
+#define HYP_RESTORE 3
+/* Opcode to test vGIC active bit reg */
+#define VGIC_TEST 4
+
+vm_context *hvc_handler(unsigned, vm_context *);
+
+#endif /* __HVC_H__ */
diff --git a/big-little/include/hyp_types.h b/big-little/include/hyp_types.h
new file mode 100644
index 0000000..123242c
--- /dev/null
+++ b/big-little/include/hyp_types.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __HYP_TYPES_H__
+#define __HYP_TYPES_H__
+
+typedef signed int int32_t;
+typedef signed short int16_t;
+typedef unsigned int uint32_t;
+typedef unsigned short uint16_t;
+typedef unsigned char uint8_t;
+typedef signed char int8_t;
+typedef long long int64_t;
+typedef unsigned long long uint64_t;
+
+#define PRIVATE static
+#define PUBLIC
+
+#endif /* __HYP_TYPES_H__ */
diff --git a/big-little/include/hyp_vmmap.h b/big-little/include/hyp_vmmap.h
new file mode 100644
index 0000000..ef3eeb6
--- /dev/null
+++ b/big-little/include/hyp_vmmap.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __HYP_VMMAP_H__
+#define __HYP_VMMAP_H__
+
+#include "hyp_types.h"
+#include "misc.h"
+
+/* ----------------------------------------------------------------------------
+ * d e f i n e s
+ * --------------------------------------------------------------------------*/
+
+#define GIC_ID_PHY_BASE 0x2C001000 /* Physical Distributor */
+#define GIC_IC_PHY_BASE 0x2C002000 /* Physical CPU interface */
+
+#define VGIC_HV_PHY_BASE 0x2C004000 /* Hypervisor's VIew */
+#define VGIC_VM_PHY_BASE 0x2C006000 /* Virtual Machine view */
+
+#define UART0_PHY_BASE 0x1C090000
+#define UART1_PHY_BASE 0x1C0A0000
+
+#endif /* __HYP_VMMAP_H__ */
diff --git a/big-little/include/int_master.h b/big-little/include/int_master.h
new file mode 100644
index 0000000..ec3b1b7
--- /dev/null
+++ b/big-little/include/int_master.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+/*
+ * Master interrupt controller driver - talks to real IC and dispatches
+ * * interrupts to slave ICs or monitor drivers as appropriate
+ */
+
+#ifndef _INT_MASTER_H_
+#define _INT_MASTER_H_
+
+#include "bl.h"
+
+#define INT_ENABLED 0x1 /* Interrupt is enabled, something to pass it on to */
+#define INT_ACTIVE 0x2 /* Interrupt is currently actually disabled at the real controller because it is active */
+
+#define INT_TRIGGER 0
+#define INT_ENABLE 1
+#define INT_DISABLE 2
+#define INT_GETRAW 3
+#define INT_UNTRIGGER 4
+
+vm_context *handle_interrupt(vm_context * context);
+int gic_masterhandler(void *ptr, unsigned int num, unsigned int op);
+void gic_masterinit(void);
+void gic_deactivate_int(unsigned int num);
+void gic_setup_secure(unsigned, unsigned);
+void enable_2ndstage(void);
+void setup_hcr(void);
+void test_vgic(void);
+#endif
diff --git a/big-little/include/misc.h b/big-little/include/misc.h
new file mode 100644
index 0000000..c154ced
--- /dev/null
+++ b/big-little/include/misc.h
@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef MISC_H
+#define MISC_H
+
+#include <stdio.h>
+#include <string.h>
+
+#define NUM_CPUS 8
+
+#define inline __inline
+
+#define A7 0xC07
+#define A15 0xC0F
+#define PART_NO(x) ((x >> 4) & 0xfff)
+#define REVISION(x) (x & 0xf)
+#define VARIANT(x) ((x >> 20) & 0xf)
+
+#define MAX_CLUSTERS 2
+#define MAX_CORES 8
+#define MAX_CPUIFS 8
+#define STACK_SIZE 96
+
+#define TRUE 1
+#define FALSE 0
+#define CONTEXT_SAVE 0
+#define CONTEXT_RESTORE 1
+#define SYNC_SWITCHOVER 1
+#define READ_MPIDR 2
+
+/*************************************************
+ * Virtual GIC defines
+ *************************************************/
+
+/* Bit definitions in the secure GICC_CTLR */
+#define EOI_MODE_NS (1 << 10)
+#define EOI_MODE_S (1 << 9)
+
+/* Bit definitions in the Active list registers */
+#define HW_IRQ ((unsigned) 1 << 31)
+#define NS_IRQ (1 << 30)
+#define STATE(x) ((x & 0x3) << 28)
+#define PENDING 0x1
+
+/* Misc */
+#define INTACK_CPUID_MASK 0x7
+
+/*************************************************
+ * Bit definitions in the HYP configuration
+ * register.
+ *************************************************/
+#define HCR_AMO (1 << 5)
+#define HCR_IMO (1 << 4)
+#define HCR_FMO (1 << 3)
+#define HCR_VM (1 << 0)
+#define HCR_TID2 (1 << 17)
+#define HCR_TSW (1 << 22)
+
+/*************************************************
+ * TEX remap defines for first level translations
+ *************************************************/
+/* PRRR fields for memory attributes */
+#define TR0(x) ((x) << 0) // SO
+#define TR1(x) ((x) << 2) // DV
+#define TR4(x) ((x) << 8) // NC
+#define TR7(x) ((x) << 14) // C
+/* PRRR fields for shareability attributes */
+#define NOS0(x) ((x) << 24)
+#define NOS1(x) ((x) << 25)
+#define NOS4(x) ((x) << 28)
+#define NOS7(x) ((x) << 31)
+#define NS1(x) ((x) << 19)
+#define DS1(x) ((x) << 17)
+
+/* Memory attributes */
+#define NORMAL_MEM 0x2
+#define DEVICE_MEM 0x1
+#define SO_MEM 0x0
+#define INNER_SH 0x1
+#define SHAREABLE 0x1
+
+/* NMRR fields */
+#define IR7(x) ((x) << 14) // Inner Cache attributes for TEX,C,B = 1,1,1
+#define IR4(x) ((x) << 8) // Inner Cache attributes for TEX,C,B = 1,0,0
+#define OR7(x) ((x) << 30) // Outer Cache attributes for TEX,C,B = 1,1,1
+#define OR4(x) ((x) << 24) // Outer Cache attributes for TEX,C,B = 1,0,0
+
+/* Normal memory attributes */
+#define NMRR_NC 0x0
+#define NMRR_WBWA 0x1
+
+/************************************************
+ * Page table walk attributes in TTBR0/1
+ ************************************************/
+#define NOS(x) ((x) << 5)
+#define RGN(x) ((x) << 3)
+#define SH(x) ((x) << 1)
+#define IRGN(x) ((((x) & 0x2) << 5) | ((x) & 0x1))
+
+#define TTBR_SH 0x1
+#define TTBR_WBWA 0x1
+
+/*
+ * Bit definitions of Level 2 translation
+ * table entries.
+ */
+
+/* Mapping type[1:0] */
+#define INVALID_MAPPING 0x0
+#define BLOCK_MAPPING 0x1
+#define TABLE_MAPPING 0x3
+
+/*
+ * Bit definitions of Level 3 translation
+ * table entries.
+ */
+
+/* Mapping type[1:0] */
+#define VALID_MAPPING 0x3
+
+/* Lower block attributes[11:2] */
+#define NON_GLOBAL (1 << 11)
+#define ACCESS_FLAG (1 << 10)
+#define SHAREABILITY(x) ((x & 0x3) << 8)
+#define ACCESS_PERM(x) ((x & 0x3) << 6)
+#define MEM_ATTR(x) ((x & 0xf) << 2)
+
+/* Upper block attributes[63:52]. Defined as the upper word */
+#define XN (1 << 22)
+#define PXN (1 << 21)
+
+/*
+ * Cache levels.
+ */
+#define L1 0x0
+#define L2 0x1
+
+/*
+ * Cache maintenance op types.
+ */
+#define INV 0x0
+#define CLN 0x1
+#define CLN_INV 0x2
+
+/*
+ * Cache line length in bytes
+ */
+#define CACHE_LINE_SZ 64
+
+/*
+ * CCI defines
+ */
+#define CCI_BASE 0x2c090000
+#define CCI_PERF_CNT(x) CCI_BASE + ((0xa + x ) << 12)
+#define CCI_CYCLE_CNT CCI_BASE + 0x9000
+#define A15_SL_IFACE_BASE CCI_BASE + 0x4000
+#define A7_SL_IFACE_BASE CCI_BASE + 0x5000
+
+/* PMU Counter Registers */
+#define EVNT_SEL_REG 0x0
+#define CNT_REG 0x4
+#define CNT_CTLR_REG 0x8
+#define OVRFLW_STAT_REG 0xc
+
+/* Control interface register offsets */
+#define CTLR_OVERRIDE_REG 0x0
+#define SPEC_CTLR_REG 0x4
+#define SECURE_ACCESS_REG 0x8
+#define STATUS_REG 0xc
+#define IMPRECISE_ERR_REG 0x10
+#define PERF_MON_CTRL_REG 0x100
+
+/* Slave interface register */
+#define SNOOP_CTLR_REG 0x0
+
+/* PMCR bits */
+#define PMCR_CEN (1 << 0)
+#define PMCR_RST (1 << 1)
+#define PMCR_CCR (1 << 2)
+#define PMCR_CCD (1 << 3)
+#define reset_cci_pmu() write32(CCI_BASE + PERF_MON_CTRL_REG, PMCR_RST | PMCR_CCR)
+#define enable_cci_pmu() write32(CCI_BASE + PERF_MON_CTRL_REG, PMCR_CEN)
+#define enable_cci_cntr(x) write32(CCI_PERF_CNT(x) + CNT_CTLR_REG, 0x1)
+#define disable_cci_cntr(x) write32(CCI_PERF_CNT(x) + CNT_CTLR_REG, 0x0)
+#define select_cci_event(x, y) write32(CCI_PERF_CNT(x) + EVNT_SEL_REG, y)
+#define read_cci_cntr(x) read32(CCI_PERF_CNT(x) + CNT_REG)
+/*
+ * TODO:
+ * Move platform specific definitions to the right places
+ */
+#define KFSCB_BASE 0x60000000
+
+#define RST_HOLD0 0x0
+#define RST_HOLD1 0x4
+#define SYS_SWRESET 0x8
+#define RST_STAT0 0xc
+#define RST_STAT1 0x10
+#define EAG_CFG_R 0x20
+#define EAG_CFG_W 0x24
+#define KFC_CFG_R 0x28
+#define KFC_CFG_W 0x2c
+#define KFS_CFG_R 0x30
+#define RST_HANDLER0 0x40
+#define RST_HANDLER1 0x48
+#define RST_HANDLER2 0x50
+#define RST_HANDLER3 0x58
+#define RST_HANDLER4 0x60
+#define RST_HANDLER5 0x68
+#define RST_HANDLER6 0x70
+#define RST_HANDLER7 0x78
+#define KFS_ID 0xffc
+
+/*
+ * KFSCB Tube offsets. Models only
+ */
+#define KFS_TUBE0 0x400
+#define KFS_TUBE1 0x420
+#define KFS_TUBE2 0x440
+#define KFS_TUBE3 0x460
+
+/*
+ * Map the 4 tubes to the Secure
+ * & non-secure worlds
+ */
+#define SEC_TUBE0 KFS_TUBE0
+#define SEC_TUBE1 KFS_TUBE1
+#define NS_TUBE0 KFS_TUBE2
+#define NS_TUBE1 KFS_TUBE3
+
+/* KFSCB Tube register offsets. */
+#define TUBE_CHAR 0x00
+#define TUBE_DATA0 0x08
+#define TUBE_DATA1 0x10
+#define TUBE_DATA2 0x18
+
+#define CLUSTER_CPU_COUNT(x) (((read32(KFSCB_BASE + KFS_CFG_R) >> 16) >> (x << 2)) & 0xf)
+#define DC_SYSTYPE ((read32(KFSCB_BASE + KFS_ID) >> 16) & 0xf)
+#define asym_clusters() (((read32(KFSCB_BASE + KFS_CFG_R) >> 16) & 0xf) == \
+ ((read32(KFSCB_BASE + KFS_CFG_R) >> 20) & 0xf))
+
+/*
+ * "Always on" uses cpuids that span across clusters e.g.
+ * 0-7 for an MPx4+MPx4 system.
+ */
+#define abs_cpuid(cpu_id, cluster_id) (cluster_id ? cpu_id + CLUSTER_CPU_COUNT(!cluster_id) : cpu_id)
+#define CLUSTER_LVL_RST (1 << 0)
+#define RST_BIT(x) (1 << 4) << x
+#define RST_LVL(x, y) ((x & 0x3) << 8) << (y << 1)
+#define CORE_RESET 0x0
+#define CORE_PORESET 0x1
+#define CLUSTER_RESET 0x2
+#define EAGLE_CORES(x) ((x & 0xf) << 16)
+#define KFC_CORES(x) ((x & 0xf) << 20)
+#define SW_RESET (1 << 2)
+
+#define ENTER_RESET 0x1
+#define EXIT_RESET 0x2
+#define CASCADE_RESET 0x4
+
+#define A15_A15 0x0
+#define A7_A15 0x1
+#define A15_A7 0x2
+
+#define EAGLE 0x0
+#define KFC 0x1
+
+/* Control register bits */
+#define CR_M (1<<0) /* MMU enabled */
+#define CR_A (1<<1) /* Align fault enable */
+#define CR_C (1<<2) /* Data cache */
+#define CR_W (1<<3) /* Write buffer */
+#define CR_Z (1<<11) /* Branch prediction */
+#define CR_I (1<<12) /* Instruction cache */
+#define CR_V (1<<13) /* Vectors */
+#define CR_XP (1<<23) /* Extended page tables */
+#define CR_TRE (1<<28) /* TEX Remap */
+
+/*
+ * Processor modes
+ */
+#define MON_MODE 0x16
+#define SVC_MODE 0x13
+#define HYP_MODE 0x1A
+#define USR_MODE 0x10
+
+/* Timer Bits */
+#define HYP_TIMER_MULT 0xa /* 12Mhz * 10 i.e. interrupt every 10ms. Linux uses 12MHz * 10 */
+#define LCL_TIMER_FREQ 0x7f /* Every 128th timer acts as a trigger */
+#define HYP_TIMER_IRQ 0x1a
+#define LCL_TIMER_IRQ 0x1e
+#define TIMER_ENABLE 0x1
+#define TIMER_DISABLE 0x0
+#define TIMER_MASK_IRQ 0x2
+#define TIMER_IRQ_STAT 0x4
+
+/* Trap ids provided in the HSR */
+#define NUM_TRAPS 0x27
+#define TRAP_UNKNOWN 0x0
+#define TRAP_WFE_WFI 0x1
+#define TRAP_CP15_32 0x3
+#define TRAP_CP15_64 0x4
+#define TRAP_CP14_32 0x5
+#define TRAP_CP14_LDC_STC 0x6
+#define TRAP_HCPTR_1 0x7
+#define TRAP_HCPTR_2 0x8
+#define TRAP_JAZELLE 0x9
+#define TRAP_BXJ 0xA
+#define TRAP_CP14_64 0xC
+#define TRAP_HYP_SVC 0x11
+#define TRAP_HVC 0x12
+#define TRAP_HYP_SMC 0x13
+#define TRAP_IABORT 0x20
+#define TRAP_HYP_IABORT 0x21
+#define TRAP_DABORT 0x24
+#define TRAP_HYP_DABORT 0x25
+
+/*
+ * Defines for making SMC calls
+ */
+#define SMC_SEC_INIT 0x0
+#define SMC_SEC_SAVE 0x1
+#define SMC_SEC_SHUTDOWN 0x2
+
+#define MAX_CACHE_LEVELS 0x8
+#define CRN_C0 0x0
+#define CRN_C7 0x7
+#define CRN_C9 0x9
+#define CRN_C15 0xf
+
+/*
+ * Opcode2 definitions in the corresponding cp15 instruction
+ */
+#define MIDR 0x0
+#define CTR 0x1
+#define TCMTR 0x2
+#define TLBTR 0x3
+#define MPIDR 0x5
+#define CCSIDR 0x0
+#define CLIDR 0x1
+#define AIDR 0x4
+#define CSSELR 0x0
+#define DCISW 0x2
+#define DCCSW 0x2
+#define DCCISW 0x2
+
+#define ID_PFR0 0x0
+#define ID_PFR1 0x1
+#define ID_DFR0 0x2
+#define ID_AFR0 0x3
+#define ID_MMFR0 0x4
+#define ID_MMFR1 0x5
+#define ID_MMFR2 0x6
+#define ID_MMFR3 0x7
+#define ID_ISAR0 0x0
+#define ID_ISAR1 0x1
+#define ID_ISAR2 0x2
+#define ID_ISAR3 0x3
+#define ID_ISAR4 0x4
+#define ID_ISAR5 0x5
+
+extern void enable_cci_snoops(unsigned);
+extern void disable_cci_snoops(unsigned);
+extern void switch_cluster(unsigned);
+extern unsigned long long *get_powerdown_stack(unsigned);
+extern void spin_lock(unsigned int *);
+extern void spin_unlock(unsigned int *);
+extern void panic(void);
+extern unsigned get_inbound(void);
+extern unsigned reset_status(unsigned, unsigned, unsigned);
+extern unsigned map_cpuif(unsigned, unsigned);
+extern unsigned get_cpuif(unsigned, unsigned);
+extern unsigned remap_cpuif(unsigned *);
+extern unsigned get_cpuif_mask(unsigned);
+extern unsigned get_cpu_mask(unsigned);
+extern unsigned BL_DV_PAGE$$Base;
+extern unsigned BL_SEC_DV_PAGE$$Base;
+extern unsigned host_cluster;
+extern unsigned switcher;
+
+#define bitindex(x) (31-__builtin_clz(x))
+#define find_first_cpu() 0
+#define write32(addr, val) (*(volatile unsigned int *)(addr) = (val))
+#define read32(addr) (*(volatile unsigned int *)(addr))
+#endif
diff --git a/big-little/include/traps.h b/big-little/include/traps.h
new file mode 100644
index 0000000..323ba42
--- /dev/null
+++ b/big-little/include/traps.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef __TRAPS_H__
+#define __TRAPS_H__
+
+#include "misc.h"
+
+/*
+ * Ignoring the condition field [24:20] for now.
+ */
+#define HSR_ISS_OP2 (0x7 << 17)
+#define HSR_ISS_OP1 (0x7 << 14)
+#define HSR_ISS_CRN (0xf << 10)
+#define HSR_ISS_CRM (0xf << 1)
+#define HSR_ISS_RW (0x1 << 0)
+
+/*
+ * Macro to convert the cp15 instruction info in the HSR
+ * into a unique integer. The integer is used to identify
+ * the handler for that instruction. Format of the integer
+ * is [Op2:Op1:CRn:CRm:RW]
+ */
+#define GET_CP15_OP(x) ((x & HSR_ISS_OP2) >> 5) | ((x & HSR_ISS_OP1) >> 5) | ((x & HSR_ISS_CRN) >> 5) |\
+ (x & HSR_ISS_CRM) | (x & HSR_ISS_RW)
+
+#define MAKE_CP15_OP(op2, op1, crn, crm, rw) ((op2 << 12) | (op1 << 9) | (crn << 5) | (crm << 1) | rw)
+
+#define READ_MIDR MAKE_CP15_OP(0x0, 0x0, 0x0, 0x0, 0x1)
+#define READ_MPIDR MAKE_CP15_OP(0x5, 0x0, 0x0, 0x0, 0x1)
+#define READ_AUXCTRL MAKE_CP15_OP(0x1, 0x0, 0x1, 0x0, 0x1)
+
+#define WRITE_MIDR MAKE_CP15_OP(0x0, 0x0, 0x0, 0x0, 0x0)
+#define WRITE_MPIDR MAKE_CP15_OP(0x5, 0x0, 0x0, 0x0, 0x0)
+#define WRITE_AUXCTRL MAKE_CP15_OP(0x1, 0x0, 0x1, 0x0, 0x0)
+
+/*
+ * Indices into arrays of registers to whom acceses will be
+ * trapped.
+ */
+#define AUXCTRL 0x0
+#define MIDR 0x1
+#define MPIDR 0x2
+#define MAX_REGS 0x10
+
+/*
+ * Indices into array of handlers of the registered traps.
+ * Numbers correspond to the Exception Class field of HSR.
+ */
+#define UNKNOWN 0x0
+#define MRC_MCR_CP15 0x3
+#define MAX_TRAPS 0x25
+
+/*
+ * Structure to hold the registered traps
+ */
+typedef struct tlist {
+ unsigned int hcr;
+ unsigned int hstr;
+} trap_list;
+
+/*
+ * Structure to hold registers to whom accesses will be trapped
+ */
+typedef struct rlist {
+ unsigned int reg[MAX_REGS];
+} reg_list;
+
+/*
+ * Structure to hold platform defined trap handlers
+ */
+typedef struct hlist {
+ int (*handle[MAX_TRAPS]) (unsigned int hsr, unsigned int *operand);
+} handler_list;
+
+extern trap_list cp15_trap_list[NUM_CPUS];
+extern reg_list cp15_reg_list[NUM_CPUS];
+extern handler_list plat_handler_list[NUM_CPUS];
+
+#if !DEBUG
+#define printf(...)
+#endif
+#endif /* __TRAPS_H__ */
diff --git a/big-little/include/vgiclib.h b/big-little/include/vgiclib.h
new file mode 100644
index 0000000..869a8df
--- /dev/null
+++ b/big-little/include/vgiclib.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef VGICLIB_H
+#define VGICLIB_H
+
+#include "gic_registers.h"
+
+struct overflowint {
+ /* This is encoded in the value, but speed optimise by splitting out */
+ unsigned int priority;
+ unsigned int value;
+ struct overflowint *next;
+};
+
+struct gic_cpuif {
+ unsigned int status;
+ unsigned int activepris; /* Copies of the state from the VGIC itself */
+ unsigned int elrsr[2]; /* Copies of Empty list register status registers */
+ unsigned int ints[VGIC_LISTENTRIES];
+
+ struct overflowint *overflow; /* List of overflowed interrupts */
+ unsigned int freelist; /* Bitmask of which list entries are in use */
+};
+
+void vgic_init(void);
+void vgic_savestate(unsigned int cpu);
+void vgic_loadstate(unsigned int cpu);
+void vgic_refresh(unsigned int cpu);
+void enqueue_interrupt(unsigned int descr, unsigned int cpu);
+
+#endif /* VGICLIB_H */
diff --git a/big-little/include/virt_helpers.h b/big-little/include/virt_helpers.h
new file mode 100644
index 0000000..34e4d1c
--- /dev/null
+++ b/big-little/include/virt_helpers.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2011, ARM Limited. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with
+ * or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the
+ * following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the
+ * above copyright notice, this list of conditions and
+ * the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its
+ * contributors may be used to endorse or promote products
+ * derived from this software without specific prior written
+ * permission.
+ */
+
+#ifndef _VIRT_HELPERS_H_
+#define _VIRT_HELPERS_H_
+
+#include "bakery.h"
+#include "helpers.h"
+#include "misc.h"
+
+/*******************************************************
+ * Export prototypes of the functions which will be used
+ * to save/restore the Non-secure context.
+ *******************************************************/
+
+/*
+ * Misc functions
+ */
+extern unsigned read_sp(unsigned);
+extern unsigned read_lr(unsigned);
+extern unsigned num_secondaries(void);
+extern unsigned *get_sp(unsigned, unsigned);
+
+extern void virt_dead(void);
+extern void smc(unsigned, unsigned);
+extern void dcisw(unsigned);
+extern void dccsw(unsigned);
+extern void dccisw(unsigned);
+extern void write_sp(unsigned, unsigned);
+extern void write_lr(unsigned, unsigned);
+
+/*
+ * V7 functions
+ */
+extern void disable_clean_inv_l1_dcache_v7(void);
+extern void cache_maint_op(unsigned, unsigned);
+extern unsigned get_loc(void);
+extern void disable_coherency(void);
+extern void disable_dcache(void);
+extern void enable_coherency(void);
+extern void enable_dcache(void);
+extern void flush_to_loc(void);
+extern void inv_tlb_all(void);
+extern void inv_bpred_all(void);
+extern void inv_tlb_mva(unsigned *);
+extern void inv_icache_all(void);
+extern void inv_icache_mva_pou(unsigned *);
+extern void inv_dcache_mva_poc(unsigned *);
+extern void cln_dcache_mva_poc(unsigned *);
+extern void cln_dcache_mva_pou(unsigned *);
+
+/*
+ * GIC functions
+ */
+extern void save_gic_interface(unsigned int *pointer,
+ unsigned gic_interface_address);
+extern int save_gic_distributor_private(unsigned int *pointer,
+ unsigned gic_distributor_address);
+extern int save_gic_distributor_shared(unsigned int *pointer,
+ unsigned gic_distributor_address);
+extern void restore_gic_interface(unsigned int *pointer,
+ unsigned gic_interface_address);
+extern void restore_gic_distributor_private(unsigned int *pointer,
+ unsigned gic_distributor_address);
+extern void restore_gic_distributor_shared(unsigned int *pointer,
+ unsigned gic_distributor_address);
+extern void hyp_save(unsigned, unsigned);
+
+/*
+ * Tube functions
+ */
+#if TUBE
+extern void write_trace(bakery_t *, unsigned, char *, unsigned long long,
+ unsigned long long, unsigned long long);
+#else
+#define write_trace(...)
+#endif
+
+#endif /* _VIRT_HELPERS_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 03:39:39 +0000