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authorGiuseppe Calderaro <giuseppe.calderaro@arm.com>2012-05-02 15:45:23 +0100
committerDietmar Eggemann <dietmar.eggemann@arm.com>2012-05-23 12:44:34 +0100
commitcdaeeb4e9ff4c59ad6ac3ef7a733406bcd8742b8 (patch)
tree579949d785374ce9357439fcfc2ac438cf710352
parent2c1558d998bece21208ad9c69be892f27a6d9d93 (diff)
vsm: preparation for PMU handling.
Added PMU regs macros. Added PMU function wrappers.
-rw-r--r--big-little/include/context.h1
-rw-r--r--big-little/include/misc.h24
-rw-r--r--big-little/switcher/context/ns_context.c11
3 files changed, 31 insertions, 5 deletions
diff --git a/big-little/include/context.h b/big-little/include/context.h
index 9742ca8..6183f70 100644
--- a/big-little/include/context.h
+++ b/big-little/include/context.h
@@ -77,7 +77,6 @@ typedef struct gen_tmr_ctx {
typedef struct ns_cpu_context {
unsigned int banked_cpu_regs[32]; /* Banked cpu registers */
banked_cp15_context banked_cp15_regs; /* Per cpu banked cp15 context */
- unsigned int pmon_regs[32]; /* Generic performance monitor registers */
generic_timer_context cp15_timer_ctx; /* Global counter registers if accessible in NS world */
gic_cpu_context gic_cpu_ctx; /* Per cpu GIC distributor and interface context */
unsigned int endianess; /* Per cpu endianess */
diff --git a/big-little/include/misc.h b/big-little/include/misc.h
index 0b15d5a..0de5000 100644
--- a/big-little/include/misc.h
+++ b/big-little/include/misc.h
@@ -47,6 +47,30 @@
#define CONTEXT_RESTORE 1
#define SYNC_SWITCHOVER 1
#define READ_MPIDR 2
+/* PMU HVCs */
+#define PMCR_READ 0x90000001
+#define PMCR_WRITE 0x90000002
+#define PMSELR_READ 0x90000003
+#define PMSELR_WRITE 0x90000004
+#define PMXEVTYPER_READ 0x90000005
+#define PMXEVTYPER_WRITE 0x90000006
+#define PMCNTENSET_READ 0x90000007
+#define PMCNTENSET_WRITE 0x90000008
+#define PMCNTENCLR_READ 0x90000009
+#define PMCNTENCLR_WRITE 0x9000000A
+#define PMCCNTR_READ 0x9000000B
+#define PMCCNTR_WRITE 0x9000000C
+#define PMOVSR_READ 0x9000000D
+#define PMOVSR_WRITE 0x9000000E
+#define PMXEVCNTR_READ 0x9000000F
+#define PMXEVCNTR_WRITE 0x90000010
+#define PMINTENSET_READ 0x90000011
+#define PMINTENSET_WRITE 0x90000012
+#define PMINTENCLR_READ 0x90000013
+#define PMINTENCLR_WRITE 0x90000014
+#define HVC_SWITCH 0x90000100
+#define GET_COUNTERS_SIZE 0x90000200
+#define SYNC_PMU_COUNTERS 0x90000201
/*************************************************
* Virtual GIC defines
diff --git a/big-little/switcher/context/ns_context.c b/big-little/switcher/context/ns_context.c
index 1e193ac..bc2a1e0 100644
--- a/big-little/switcher/context/ns_context.c
+++ b/big-little/switcher/context/ns_context.c
@@ -35,6 +35,10 @@ extern void gic_enable_int(unsigned);
extern void SetupVGIC(unsigned);
extern unsigned hyp_timer_trigger;
+/* PMU if. */
+extern void save_pmu_context(unsigned cluster_id, unsigned cpu_id);
+extern void restore_pmu_context(unsigned cluster_id, unsigned cpu_id);
+
/* Bakery locks to serialize access to the tube. */
static bakery_t lock_tube0 __attribute__ ((section("BL_DV_PAGE"))) = {
0};
@@ -98,7 +102,6 @@ void save_context(unsigned first_cpu, unsigned op_type)
unsigned cpu_id = read_cpuid(), cluster_id = read_clusterid();
cpu_context *ns_cpu_ctx =
&switcher_context.cluster.core[cpu_id].ns_cpu_ctx;
- unsigned *pmon_context = ns_cpu_ctx->pmon_regs;
unsigned *gp_context = ns_cpu_ctx->banked_cpu_regs;
unsigned *vfp_context = ns_cpu_ctx->vfp_regs;
debug_context_t *debug_context = &ns_cpu_ctx->debug_ctx;
@@ -146,11 +149,11 @@ void save_context(unsigned first_cpu, unsigned op_type)
* Save cpu general purpose banked registers
* Save cp15 context
*/
- save_performance_monitors(pmon_context);
save_banked_registers(gp_context);
save_cp15(cp15_context->cp15_misc_regs);
save_control_registers(cp15_context->cp15_ctrl_regs, 0x0);
save_mmu(cp15_context->cp15_mmu_regs);
+ save_pmu_context(cluster_id, cpu_id);
save_fault_status((unsigned *)fault_ctx);
/*
@@ -182,6 +185,7 @@ void save_context(unsigned first_cpu, unsigned op_type)
* Disable the GIC CPU interface tp prevent interrupts from waking
* the core from wfi() subsequently.
*/
+
write32(GIC_IC_PHY_BASE + GICC_CTL, 0x0);
/*
@@ -226,7 +230,6 @@ void restore_context(unsigned first_cpu, unsigned op_type)
cpu_context *ns_cpu_ctx =
&switcher_context.cluster.core[cpu_id].ns_cpu_ctx;
global_context *gbl_context = &switcher_context.cluster.ns_cluster_ctx;
- unsigned *pmon_context = ns_cpu_ctx->pmon_regs;
unsigned *gp_context = ns_cpu_ctx->banked_cpu_regs;
unsigned *vfp_context = ns_cpu_ctx->vfp_regs;
debug_context_t *debug_context = &ns_cpu_ctx->debug_ctx;
@@ -295,7 +298,7 @@ void restore_context(unsigned first_cpu, unsigned op_type)
restore_control_registers(cp15_context->cp15_ctrl_regs, 0x0);
restore_cp15(cp15_context->cp15_misc_regs);
restore_banked_registers(gp_context);
- restore_performance_monitors(pmon_context);
+ restore_pmu_context(cluster_id, cpu_id);
restore_generic_timer((unsigned *)cp15_timer_ctx, 0x1);
}