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authorJens Wiklander <jens.wiklander@linaro.org>2014-09-04 10:23:27 +0200
committerJens Wiklander <jens.wiklander@linaro.org>2014-09-16 11:39:32 -0700
commitae213cee8c38af64ba82c1c9e94598d7efe46327 (patch)
tree80454bb25c54a250164b7af2d23e7086615516d4 /bl31
parent087b67a62b0a98b486e5ac332d979a6e5490fe8a (diff)
Initialize SCTLR_EL1 based on MODE_RW bit
Initializes SCTLR_EL1 based on MODE_RW bit in SPSR for the entry point. The RES1 bits for SCTLR_EL1 differs for Aarch64 and Aarch32 mode.
Diffstat (limited to 'bl31')
-rw-r--r--bl31/context_mgmt.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c
index 489d454..4dd297e 100644
--- a/bl31/context_mgmt.c
+++ b/bl31/context_mgmt.c
@@ -182,7 +182,10 @@ void cm_init_context(uint64_t mpidr, const entry_point_info_t *ep)
* against the CPU support, security state, endianess and pc
*/
sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
- sctlr_elx |= SCTLR_EL1_RES1;
+ if (GET_RW(ep->spsr) == MODE_RW_64)
+ sctlr_elx |= SCTLR_EL1_RES1;
+ else
+ sctlr_elx |= SCTLR_AARCH32_EL1_RES1;
write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
if ((GET_RW(ep->spsr) == MODE_RW_64