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authorAchin Gupta <achin.gupta@arm.com>2014-06-17 16:59:13 +0100
committerAchin Gupta <achin.gupta@arm.com>2014-06-17 16:59:13 +0100
commitcc8856432ebb790f045d34fa9296b24eea38c71c (patch)
tree71265f0f38aba94b02e779c103c7de05debed8dd
parente9e0b053ce756fa60afaedfa9eeb963a8aa87af3 (diff)
downloadarm-trusted-firmware-0.4-Juno-0.5.tar.gz
Add barriers to handle Secure Timer interrupts correctlyv0.4-Juno-0.5
This patch adds instruction synchronization barriers around the code which handles the timer interrupt in the TSP. This ensures that the interrupt is not acknowledged after or EOIed before it is deactivated at the peripheral. Change-Id: Ic691ab909bc671d8f0f43ffc443f46237c75536d
-rw-r--r--bl32/tsp/tsp_timer.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c
index 366640f..fd4a9c5 100644
--- a/bl32/tsp/tsp_timer.c
+++ b/bl32/tsp/tsp_timer.c
@@ -68,9 +68,14 @@ void tsp_generic_timer_handler()
/* Ensure that the timer did assert the interrupt */
assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
- /* Disable the timer and reprogram it */
+ /*
+ * Disable the timer and reprogram it. The barriers ensure that there is
+ * no reordering of instructions around the reprogramming code.
+ */
+ isb();
write_cntps_ctl_el1(0);
tsp_generic_timer_start();
+ isb();
}
/*******************************************************************************