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| author | Alex Zuepke <alexander.zuepke@hs-rm.de> | 2014-05-28 19:25:36 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:40 +0200 |
| commit | a721d390b302a383a99224e08d12caad2e97d7ab (patch) | |
| tree | 8a81b17e463ee4cc8d0c40e89d17716001125c01 /target-ppc/mmu_helper.c | |
| parent | 1b8eceee280d3fab11812271f4956f7b69287ef0 (diff) | |
PPC: e500: Fix MMUCSR0 emulation
A "mtspr SPRMMUCSR0, reg" always flushed TLB0,
because it passed the SPR number 0x3f4 to the flush routine.
But we want to flush either TLB0 or TBL1 depending on the GPR value.
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
[agraf: change subject line, fix TCGv size mismatch]
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/mmu_helper.c')
| -rw-r--r-- | target-ppc/mmu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index f029f4196..1e70536e3 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2886,7 +2886,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) tlb_flush(CPU(cpu), 1); } -void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) +void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type) { int flags = 0; |