diff options
| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-06-11 01:55:03 +0200 |
|---|---|---|
| committer | Greg Bellows <greg.bellows@linaro.org> | 2014-11-17 09:50:07 -0600 |
| commit | ec7ef8d74e5d17d00dd1efab6be659cd03a9b0a4 (patch) | |
| tree | 937cafa3b7ccf3059c8da9677d032740da66542c /target-arm/cpu.c | |
| parent | 56c538e8298023df384d23b1d084629133b0470d (diff) | |
target-arm: add SCTLR_EL3 and make SCTLR banked
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
v9 -> v10
- Fix SCTLR to use opc0 instead of cp
v8 -> v9
- Remove the v8 check in arm_cpu_reset when setting regs[15]
- Fix SCTLR definition component order
v5 -> v6
- Changed _el field variants to be array based
- Consolidate SCTLR and SCTLR_EL1 reginfo entries
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 5ce7350ce..fdb7b35f8 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -109,7 +109,7 @@ static void arm_cpu_reset(CPUState *s) #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ - env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; + env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; /* and to the FP/Neon instructions */ env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); #else @@ -167,7 +167,11 @@ static void arm_cpu_reset(CPUState *s) env->thumb = initial_pc & 1; } - if (env->cp15.c1_sys & SCTLR_V) { + /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently + * executing as AArch32 then check if highvecs are enabled and + * adjust the PC accordingly. + */ + if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { env->regs[15] = 0xFFFF0000; } |