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authorGuenter Roeck <linux@roeck-us.net>2014-04-25 08:39:48 -0700
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-13 09:12:40 +1000
commit7dfba6dfbf805cf99c4ae89f6194bc9205dfbefe (patch)
tree5bbfcd2f02f1a0b819a0b91a812f2ac45989ebb8
parent12f7fb60863f5aae44fa7a6c1f52cbecd29d4e9c (diff)
downloadqemu-tz-7dfba6dfbf805cf99c4ae89f6194bc9205dfbefe.tar.gz
xilinx_timer: Fix writes into TCSR register
The TCSR register has only 11 valid bits. This is now used by the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1 and later to hang when run under qemu-microblaze. Mask valid bits before writing the register to solve the problem. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-rw-r--r--hw/timer/xilinx_timer.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 6113b97..3ff1da9 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
if (value & TCSR_TINT)
value &= ~TCSR_TINT;
- xt->regs[addr] = value;
+ xt->regs[addr] = value & 0x7ff;
if (value & TCSR_ENT)
timer_enable(xt);
break;