Fix build issues from Samsung TZ mergesamsung_merge

Fix various build issues from merging Samsung TZ changes.

2 files changed, 6 insertions, 22 deletions

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 03c016b22..89a8d76e9 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -211,7 +211,7 @@ typedef struct CPUARMState {
         uint32_t c1_nsacr; /* Non-secure access control register. */
         uint64_t ttbr0_el1; /* MMU translation table base 0. */
         uint64_t ttbr1_el1; /* MMU translation table base 1. */
-        uint64_t c2_control; /* MMU translation table base control.  */
+        BANKED_CP_REG(uint64_t, c2_control); /* MMU x-lation tbl base cntrl.*/
         uint32_t c2_mask; /* MMU translation table base selection mask.  */
         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
         uint32_t c2_data; /* MPU data cachable bits.  */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b5259d397..0685a8dc1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1223,7 +1223,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         } else {
             BANKED_CP15_REG_SET(env, c7_par, ((ret & (10 << 1)) >> 5) |
                 ((ret & (1 << 12)) >> 6) |
-                ((ret & 0xf) << 1) | 1i);
+                ((ret & 0xf) << 1) | 1);
         }
         BANKED_CP15_REG_SET(env, c7_par_hi, 0);
     }
@@ -1924,7 +1924,7 @@ static void define_aarch64_debug_regs(ARMCPU *cpu)
 }
 
 #ifndef CONFIG_USER_ONLY
-static int scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 {
     if ((value & 1/*NS*/) && 
         (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_MON) {
@@ -1934,7 +1934,6 @@ static int scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     }
 
     env->cp15.c1_scr = value;
-    return 0;
 }
 
 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1949,11 +1948,10 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
     CPREG_FIELD32(env, ri) = value & ~0x1Ful;
 }
 
-static int nsacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+static void nsacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                       uint64_t value)
 {
     env->cp15.c1_nsacr = value & 0x3fff;
-    return 0;
 }
 #endif
 
@@ -1963,10 +1961,10 @@ static const ARMCPRegInfo tz_cp_reginfo[] = {
       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL3_RW, .type = ARM_CP_BANKED, .writefn = vbar_write,
       .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
-      .writefn = scr_write, .resetvalue = 0 },
+      .resetvalue = 0 },
     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
-      .resetvalue = 0, },
+      .writefn = scr_write, .resetvalue = 0, },
     { .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
       .access = PL3_RW, .resetvalue = 0, .writefn = vbar_write,
       .fieldoffset = offsetof(CPUARMState, cp15.c12_mvbar) },
@@ -2886,10 +2884,6 @@ void switch_cp15_regs(CPUARMState *env, int secure)
     i = arm_is_secure(env) ? 0 : 1;
     env->cp15.banked_c0_cssel[i] = env->cp15.c0_cssel;
     env->cp15.banked_c1_sys[i] = env->cp15.c1_sys;
-    env->cp15.banked_c2_base0[i] = env->cp15.c2_base0;
-    env->cp15.banked_c2_base0_hi[i] = env->cp15.c2_base0_hi;
-    env->cp15.banked_c2_base1[i] = env->cp15.c2_base1;
-    env->cp15.banked_c2_base1_hi[i] = env->cp15.c2_base1_hi;
     env->cp15.banked_c2_control[i] = env->cp15.c2_control;
     env->cp15.banked_c3[i] = env->cp15.c3;
     env->cp15.banked_c5_data[i] = env->cp15.c5_data;
@@ -2900,9 +2894,6 @@ void switch_cp15_regs(CPUARMState *env, int secure)
     env->cp15.banked_c7_par_hi[i] = env->cp15.c7_par_hi;
     env->cp15.banked_c13_context[i] = env->cp15.c13_context;
     env->cp15.banked_c13_fcse[i] = env->cp15.c13_fcse;
-    env->cp15.banked_c13_tls1[i] = env->cp15.c13_tls1;
-    env->cp15.banked_c13_tls2[i] = env->cp15.c13_tls2;
-    env->cp15.banked_c13_tls3[i] = env->cp15.c13_tls3;
 
     /* Restore new Security state registers */
     i = secure ? 0 : 1;
@@ -2910,10 +2901,6 @@ void switch_cp15_regs(CPUARMState *env, int secure)
     /* Maintain the value of common bits */
     env->cp15.c1_sys &= 0x8204000;
     env->cp15.c1_sys |= env->cp15.banked_c1_sys[i] & ~0x8204000;
-    env->cp15.c2_base0 = env->cp15.banked_c2_base0[i];
-    env->cp15.c2_base0_hi = env->cp15.banked_c2_base0_hi[i];
-    env->cp15.c2_base1 = env->cp15.banked_c2_base1[i];
-    env->cp15.c2_base1_hi = env->cp15.banked_c2_base1_hi[i];
     {
         int maskshift;
         env->cp15.c2_control = env->cp15.banked_c2_control[i];
@@ -2930,9 +2917,6 @@ void switch_cp15_regs(CPUARMState *env, int secure)
     env->cp15.c7_par_hi = env->cp15.banked_c7_par_hi[i];
     env->cp15.c13_context = env->cp15.banked_c13_context[i];
     env->cp15.c13_fcse = env->cp15.banked_c13_fcse[i];
-    env->cp15.c13_tls1 = env->cp15.banked_c13_tls1[i];
-    env->cp15.c13_tls2 = env->cp15.banked_c13_tls2[i];
-    env->cp15.c13_tls3 = env->cp15.banked_c13_tls3[i];
 }