diff options
| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-12-11 12:07:49 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-12-11 12:07:49 +0000 |
| commit | 770225764f831031d2e1453f69c365eb1b647d87 (patch) | |
| tree | 2c75e8f0e3889bbfb484846b1a9f2613f07a625b | |
| parent | de38d23b542efca54108ef28bcc0efe96f378d2e (diff) | |
target-arm: add NSACR register
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-11-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/cpu.h | 1 | ||||
| -rw-r--r-- | target-arm/helper.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 532f69858..2afe93a49 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 973b5a909..ace7ef928 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ + { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL3_W | PL1_R, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, REGINFO_SENTINEL }; |