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authorGreg Bellows <greg.bellows@linaro.org>2014-12-11 12:07:52 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-12-11 12:07:52 +0000
commitfb6c91ba2bb0b1c1b8662ceeeeb9474a025f9a6b (patch)
tree4a509631207009777757e0a3c443d0cfe7c2e4ec
parent01c097f7960b330c4bf038d34bae17ad6c1ba499 (diff)
downloadqemu-tz-fb6c91ba2bb0b1c1b8662ceeeeb9474a025f9a6b.tar.gz
target-arm: make VBAR banked
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) VBAR has a secure and a non-secure instance, which are mapped to VBAR_EL1 and VBAR_EL3. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-24-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/cpu.h10
-rw-r--r--target-arm/helper.c5
2 files changed, 12 insertions, 3 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2f8d607ff..fc6449750 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -297,7 +297,15 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
- uint64_t vbar_el[4]; /* vector base address register */
+ union { /* vector base address register */
+ struct {
+ uint64_t _unused_vbar;
+ uint64_t vbar_ns;
+ uint64_t hvbar;
+ uint64_t vbar_s;
+ };
+ uint64_t vbar_el[4];
+ };
uint32_t mvbar; /* (monitor) vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d2e765295..bc73c4fbb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -911,7 +911,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
- .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
+ offsetof(CPUARMState, cp15.vbar_ns) },
.resetvalue = 0 },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
@@ -4401,7 +4402,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
* This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
*/
- addr += env->cp15.vbar_el[1];
+ addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
}
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {