aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorFabian Aggeler <aggelerf@ethz.ch>2014-12-11 12:07:49 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-12-11 12:07:49 +0000
commitde38d23b542efca54108ef28bcc0efe96f378d2e (patch)
tree0200b535c25b5684cc7a8cddccfdaff1cc574f99
parent0f1a3b2470d798ad5335eb9d6236f02ff64e31a8 (diff)
downloadqemu-tz-de38d23b542efca54108ef28bcc0efe96f378d2e.tar.gz
target-arm: implement IRQ/FIQ routing to Monitor mode
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-10-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/helper.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d3180ddbc..973b5a909 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4233,12 +4233,21 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
+ if (env->cp15.scr_el3 & SCR_IRQ) {
+ /* IRQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ mask |= CPSR_F;
+ }
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
+ if (env->cp15.scr_el3 & SCR_FIQ) {
+ /* FIQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ }
offset = 4;
break;
case EXCP_SMC: