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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2017-07-05 00:02:12 +0200
committerLeif Lindholm <leif.lindholm@linaro.org>2017-07-07 15:40:48 +0100
commitefd798c1eb395fcf7ab18cf3d27666dcf5131fc5 (patch)
tree926e5cc31ec2b5c7e02ebe8ba2d2d78a0c91dfb3
parent09669445619a8ad6d445b72db6eb0ca3239520da (diff)
downloadOpenPlatformPkg-master.tar.gz
Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slaveHEADmaster
Add support for COMPHY_TYPE_SATA2 and COMPHY_TYPE_SATA3, which map to the SATA ports on the second CP110's AHCI controller. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
-rwxr-xr-xPlatforms/Marvell/Library/ComPhyLib/ComPhyCp110.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
index 6ef63a8..40a7b99 100755
--- a/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
+++ b/Platforms/Marvell/Library/ComPhyLib/ComPhyCp110.c
@@ -55,24 +55,26 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
/* Lane 0 */
{4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1},
- {COMPHY_TYPE_SATA1, 0x4}}},
+ {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}},
/* Lane 1 */
{4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
- {COMPHY_TYPE_SATA0, 0x4}}},
+ {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
/* Lane 2 */
{6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1},
{COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1},
- {COMPHY_TYPE_SATA0, 0x4}}},
+ {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}},
/* Lane 3 */
{8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1},
- {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}},
+ {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
+ {COMPHY_TYPE_SATA3, 0x4}}},
/* Lane 4 */
{7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2},
{COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2},
{COMPHY_TYPE_SGMII1, 0x1}}},
/* Lane 5 */
{6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1},
- {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4}}},
+ {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4},
+ {COMPHY_TYPE_SATA3, 0x4}}},
};
COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {