diff options
Diffstat (limited to 'sim/testsuite/sim/arm/xscale/miaxy.cgs')
-rw-r--r-- | sim/testsuite/sim/arm/xscale/miaxy.cgs | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/sim/testsuite/sim/arm/xscale/miaxy.cgs b/sim/testsuite/sim/arm/xscale/miaxy.cgs new file mode 100644 index 00000000000..624564ed176 --- /dev/null +++ b/sim/testsuite/sim/arm/xscale/miaxy.cgs @@ -0,0 +1,89 @@ +# XSCALE testcase for MIAxy +# mach: xscale +# as: -mcpu=xscale + + .include "testutils.inc" + + start + + .global miaXY +miaXY: + # Enable access to CoProcessors 0 & 1 before + # we attempt these instructions. + + mvi_h_gr r1, 3 + mcr p15, 0, r1, cr15, cr1, 0 + + # Test Bottom Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaBB acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x05f753c4 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Bottom Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaBT acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0xeeede364 + test_h_gr r1, 0x55667787 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Bottom Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaTB acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x0ec85c04 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + # Test Top Top Multilply Accumulate + + mvi_h_gr r0, 0x11223344 + mvi_h_gr r1, 0x55667788 + mvi_h_gr r2, 0x12345678 + mvi_h_gr r3, 0x9abcdef0 + + mar acc0, r0, r1 + + miaTT acc0, r2, r3 + + mra r0, r1, acc0 + + test_h_gr r0, 0x09eed974 + test_h_gr r1, 0x55667788 + test_h_gr r2, 0x12345678 + test_h_gr r3, 0x9abcdef0 + + pass |