1 files changed, 121 insertions, 0 deletions
diff --git a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs b/sim/testsuite/sim/arm/iwmmxt/wmac.cgs
new file mode 100644
index 00000000000..0857ef9ebcf
--- /dev/null
+++ b/sim/testsuite/sim/arm/iwmmxt/wmac.cgs
@@ -0,0 +1,121 @@
+# Intel(r) Wireless MMX(tm) technology testcase for WMAC
+# mach: xscale
+# as: -mcpu=xscale+iwmmxt
+
+	.include "testutils.inc"
+
+	start
+
+	.global wmac
+wmac:
+	# Enable access to CoProcessors 0 & 1 before
+        # we attempt these instructions.
+
+	mvi_h_gr   r1, 3
+	mcr        p15, 0, r1, cr15, cr1, 0
+
+	# Test Unsigned, Multiply Accumulate, Non-zeroing
+	
+	mvi_h_gr   r0, 0x12345678
+	mvi_h_gr   r1, 0x9abcdef0
+	mvi_h_gr   r2, 0x11111111
+	mvi_h_gr   r3, 0x22222222
+	mvi_h_gr   r4, 0x33333333
+	mvi_h_gr   r5, 0x44444444
+
+	tmcrr	   wr0, r0, r1
+	tmcrr	   wr1, r2, r3
+	tmcrr	   wr2, r4, r5
+
+	wmacu	   wr2, wr0, wr1
+	
+	tmrrc	   r0, r1, wr0
+	tmrrc	   r2, r3, wr1
+	tmrrc	   r4, r5, wr2
+	
+	test_h_gr  r0, 0x12345678
+	test_h_gr  r1, 0x9abcdef0
+	test_h_gr  r2, 0x11111111
+	test_h_gr  r3, 0x22222222
+	test_h_gr  r4, 0x6c889377
+	test_h_gr  r5, 0x44444444
+				
+	# Test Unsigned, Multiply Accumulate, Zeroing
+	
+	mvi_h_gr   r0, 0x12345678
+	mvi_h_gr   r1, 0x9abcdef0
+	mvi_h_gr   r2, 0x11111111
+	mvi_h_gr   r3, 0x22222222
+	mvi_h_gr   r4, 0x33333333
+	mvi_h_gr   r5, 0x44444444
+
+	tmcrr	   wr0, r0, r1
+	tmcrr	   wr1, r2, r3
+	tmcrr	   wr2, r4, r5
+
+	wmacuz	   wr2, wr0, wr1
+	
+	tmrrc	   r0, r1, wr0
+	tmrrc	   r2, r3, wr1
+	tmrrc	   r4, r5, wr2
+	
+	test_h_gr  r0, 0x12345678
+	test_h_gr  r1, 0x9abcdef0
+	test_h_gr  r2, 0x11111111
+	test_h_gr  r3, 0x22222222
+	test_h_gr  r4, 0x39556044
+	test_h_gr  r5, 0x00000000
+				
+	# Test Signed, Multiply Accumulate, Non-zeroing
+	
+	mvi_h_gr   r0, 0x12345678
+	mvi_h_gr   r1, 0x9abcdef0
+	mvi_h_gr   r2, 0x11111111
+	mvi_h_gr   r3, 0x22222222
+	mvi_h_gr   r4, 0x33333333
+	mvi_h_gr   r5, 0x44444444
+
+	tmcrr	   wr0, r0, r1
+	tmcrr	   wr1, r2, r3
+	tmcrr	   wr2, r4, r5
+
+	wmacs	   wr2, wr0, wr1
+	
+	tmrrc	   r0, r1, wr0
+	tmrrc	   r2, r3, wr1
+	tmrrc	   r4, r5, wr2
+	
+	test_h_gr  r0, 0x12345678
+	test_h_gr  r1, 0x9abcdef0
+	test_h_gr  r2, 0x11111111
+	test_h_gr  r3, 0x22222222
+	test_h_gr  r4, 0x28449377
+	test_h_gr  r5, 0x44444444
+				
+	# Test Signed, Multiply Accumulate, Zeroing
+	
+	mvi_h_gr   r0, 0x12345678
+	mvi_h_gr   r1, 0x9abcdef0
+	mvi_h_gr   r2, 0x11111111
+	mvi_h_gr   r3, 0x22222222
+	mvi_h_gr   r4, 0x33333333
+	mvi_h_gr   r5, 0x44444444
+
+	tmcrr	   wr0, r0, r1
+	tmcrr	   wr1, r2, r3
+	tmcrr	   wr2, r4, r5
+
+	wmacsz	   wr2, wr0, wr1
+	
+	tmrrc	   r0, r1, wr0
+	tmrrc	   r2, r3, wr1
+	tmrrc	   r4, r5, wr2
+	
+	test_h_gr  r0, 0x12345678
+	test_h_gr  r1, 0x9abcdef0
+	test_h_gr  r2, 0x11111111
+	test_h_gr  r3, 0x22222222
+	test_h_gr  r4, 0xf5116044
+	test_h_gr  r5, 0xffffffff
+				
+	pass