blob: 16b0aa72291d823ccb83856276b573982dcbda42 [file] [log] [blame]
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +04001/*
2 * Optimizations for Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2010 Samsung Electronics.
5 * Contributed by Kirill Batuzov <batuzovk@ispras.ru>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
Peter Maydell757e7252016-01-26 18:17:08 +000026#include "qemu/osdep.h"
Philippe Mathieu-Daudédcb32f12020-01-01 12:23:00 +010027#include "tcg/tcg-op.h"
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +040028
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +040029#define CASE_OP_32_64(x) \
30 glue(glue(case INDEX_op_, x), _i32): \
31 glue(glue(case INDEX_op_, x), _i64)
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +040032
Richard Henderson170ba882017-11-22 09:07:11 +010033#define CASE_OP_32_64_VEC(x) \
34 glue(glue(case INDEX_op_, x), _i32): \
35 glue(glue(case INDEX_op_, x), _i64): \
36 glue(glue(case INDEX_op_, x), _vec)
37
Richard Henderson6fcb98e2020-03-30 17:44:30 -070038typedef struct TempOptInfo {
Aurelien Jarnob41059d2015-07-27 12:41:44 +020039 bool is_const;
Richard Henderson63490392017-06-20 13:43:15 -070040 TCGTemp *prev_copy;
41 TCGTemp *next_copy;
Richard Henderson54795542020-09-06 16:21:32 -070042 uint64_t val;
43 uint64_t mask;
Richard Henderson6fcb98e2020-03-30 17:44:30 -070044} TempOptInfo;
Kirill Batuzov22613af2011-07-07 16:37:13 +040045
Richard Henderson6fcb98e2020-03-30 17:44:30 -070046static inline TempOptInfo *ts_info(TCGTemp *ts)
Aurelien Jarnod9c769c2015-07-27 12:41:44 +020047{
Richard Henderson63490392017-06-20 13:43:15 -070048 return ts->state_ptr;
Aurelien Jarnod9c769c2015-07-27 12:41:44 +020049}
50
Richard Henderson6fcb98e2020-03-30 17:44:30 -070051static inline TempOptInfo *arg_info(TCGArg arg)
Aurelien Jarnod9c769c2015-07-27 12:41:44 +020052{
Richard Henderson63490392017-06-20 13:43:15 -070053 return ts_info(arg_temp(arg));
54}
55
56static inline bool ts_is_const(TCGTemp *ts)
57{
58 return ts_info(ts)->is_const;
59}
60
61static inline bool arg_is_const(TCGArg arg)
62{
63 return ts_is_const(arg_temp(arg));
64}
65
66static inline bool ts_is_copy(TCGTemp *ts)
67{
68 return ts_info(ts)->next_copy != ts;
Aurelien Jarnod9c769c2015-07-27 12:41:44 +020069}
70
Aurelien Jarnob41059d2015-07-27 12:41:44 +020071/* Reset TEMP's state, possibly removing the temp for the list of copies. */
Richard Henderson63490392017-06-20 13:43:15 -070072static void reset_ts(TCGTemp *ts)
Kirill Batuzov22613af2011-07-07 16:37:13 +040073{
Richard Henderson6fcb98e2020-03-30 17:44:30 -070074 TempOptInfo *ti = ts_info(ts);
75 TempOptInfo *pi = ts_info(ti->prev_copy);
76 TempOptInfo *ni = ts_info(ti->next_copy);
Richard Henderson63490392017-06-20 13:43:15 -070077
78 ni->prev_copy = ti->prev_copy;
79 pi->next_copy = ti->next_copy;
80 ti->next_copy = ts;
81 ti->prev_copy = ts;
82 ti->is_const = false;
83 ti->mask = -1;
84}
85
86static void reset_temp(TCGArg arg)
87{
88 reset_ts(arg_temp(arg));
Kirill Batuzov22613af2011-07-07 16:37:13 +040089}
90
Aurelien Jarno1208d7d2015-07-27 12:41:44 +020091/* Initialize and activate a temporary. */
Richard Henderson6fcb98e2020-03-30 17:44:30 -070092static void init_ts_info(TempOptInfo *infos,
Emilio G. Cota34184b02017-07-19 14:32:24 -040093 TCGTempSet *temps_used, TCGTemp *ts)
Aurelien Jarno1208d7d2015-07-27 12:41:44 +020094{
Richard Henderson63490392017-06-20 13:43:15 -070095 size_t idx = temp_idx(ts);
Emilio G. Cota34184b02017-07-19 14:32:24 -040096 if (!test_bit(idx, temps_used->l)) {
Richard Henderson6fcb98e2020-03-30 17:44:30 -070097 TempOptInfo *ti = &infos[idx];
Richard Henderson63490392017-06-20 13:43:15 -070098
99 ts->state_ptr = ti;
100 ti->next_copy = ts;
101 ti->prev_copy = ts;
Richard Hendersonc0522132020-03-29 18:55:52 -0700102 if (ts->kind == TEMP_CONST) {
103 ti->is_const = true;
104 ti->val = ti->mask = ts->val;
105 if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
106 /* High bits of a 32-bit quantity are garbage. */
107 ti->mask |= ~0xffffffffull;
108 }
109 } else {
110 ti->is_const = false;
111 ti->mask = -1;
112 }
Emilio G. Cota34184b02017-07-19 14:32:24 -0400113 set_bit(idx, temps_used->l);
Aurelien Jarno1208d7d2015-07-27 12:41:44 +0200114 }
115}
116
Richard Henderson6fcb98e2020-03-30 17:44:30 -0700117static void init_arg_info(TempOptInfo *infos,
Emilio G. Cota34184b02017-07-19 14:32:24 -0400118 TCGTempSet *temps_used, TCGArg arg)
Richard Henderson63490392017-06-20 13:43:15 -0700119{
Emilio G. Cota34184b02017-07-19 14:32:24 -0400120 init_ts_info(infos, temps_used, arg_temp(arg));
Richard Henderson63490392017-06-20 13:43:15 -0700121}
122
Richard Henderson63490392017-06-20 13:43:15 -0700123static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200124{
Richard Henderson63490392017-06-20 13:43:15 -0700125 TCGTemp *i;
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200126
127 /* If this is already a global, we can't do better. */
Richard Hendersonee17db82020-03-29 10:11:56 -0700128 if (ts->kind >= TEMP_GLOBAL) {
Richard Henderson63490392017-06-20 13:43:15 -0700129 return ts;
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200130 }
131
132 /* Search for a global first. */
Richard Henderson63490392017-06-20 13:43:15 -0700133 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
Richard Hendersonee17db82020-03-29 10:11:56 -0700134 if (i->kind >= TEMP_GLOBAL) {
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200135 return i;
136 }
137 }
138
139 /* If it is a temp, search for a temp local. */
Richard Hendersonee17db82020-03-29 10:11:56 -0700140 if (ts->kind == TEMP_NORMAL) {
Richard Henderson63490392017-06-20 13:43:15 -0700141 for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
Richard Hendersonee17db82020-03-29 10:11:56 -0700142 if (i->kind >= TEMP_LOCAL) {
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200143 return i;
144 }
145 }
146 }
147
148 /* Failure to find a better representation, return the same temp. */
Richard Henderson63490392017-06-20 13:43:15 -0700149 return ts;
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200150}
151
Richard Henderson63490392017-06-20 13:43:15 -0700152static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2)
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200153{
Richard Henderson63490392017-06-20 13:43:15 -0700154 TCGTemp *i;
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200155
Richard Henderson63490392017-06-20 13:43:15 -0700156 if (ts1 == ts2) {
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200157 return true;
158 }
159
Richard Henderson63490392017-06-20 13:43:15 -0700160 if (!ts_is_copy(ts1) || !ts_is_copy(ts2)) {
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200161 return false;
162 }
163
Richard Henderson63490392017-06-20 13:43:15 -0700164 for (i = ts_info(ts1)->next_copy; i != ts1; i = ts_info(i)->next_copy) {
165 if (i == ts2) {
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200166 return true;
167 }
168 }
169
170 return false;
171}
172
Richard Henderson63490392017-06-20 13:43:15 -0700173static bool args_are_copies(TCGArg arg1, TCGArg arg2)
174{
175 return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
176}
177
Richard Henderson54795542020-09-06 16:21:32 -0700178static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val)
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200179{
Richard Henderson170ba882017-11-22 09:07:11 +0100180 const TCGOpDef *def;
181 TCGOpcode new_op;
Richard Henderson54795542020-09-06 16:21:32 -0700182 uint64_t mask;
Richard Henderson6fcb98e2020-03-30 17:44:30 -0700183 TempOptInfo *di = arg_info(dst);
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200184
Richard Henderson170ba882017-11-22 09:07:11 +0100185 def = &tcg_op_defs[op->opc];
186 if (def->flags & TCG_OPF_VECTOR) {
187 new_op = INDEX_op_dupi_vec;
188 } else if (def->flags & TCG_OPF_64BIT) {
189 new_op = INDEX_op_movi_i64;
190 } else {
191 new_op = INDEX_op_movi_i32;
192 }
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200193 op->opc = new_op;
Richard Henderson170ba882017-11-22 09:07:11 +0100194 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
195 op->args[0] = dst;
196 op->args[1] = val;
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200197
198 reset_temp(dst);
Richard Henderson63490392017-06-20 13:43:15 -0700199 di->is_const = true;
200 di->val = val;
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200201 mask = val;
Aurelien Jarno96152122015-07-10 18:03:30 +0200202 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) {
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200203 /* High bits of the destination are now garbage. */
204 mask |= ~0xffffffffull;
205 }
Richard Henderson63490392017-06-20 13:43:15 -0700206 di->mask = mask;
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200207}
208
Richard Hendersonacd93702016-12-08 12:28:42 -0800209static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
Kirill Batuzov22613af2011-07-07 16:37:13 +0400210{
Richard Henderson63490392017-06-20 13:43:15 -0700211 TCGTemp *dst_ts = arg_temp(dst);
212 TCGTemp *src_ts = arg_temp(src);
Richard Henderson170ba882017-11-22 09:07:11 +0100213 const TCGOpDef *def;
Richard Henderson6fcb98e2020-03-30 17:44:30 -0700214 TempOptInfo *di;
215 TempOptInfo *si;
Richard Henderson54795542020-09-06 16:21:32 -0700216 uint64_t mask;
Richard Henderson63490392017-06-20 13:43:15 -0700217 TCGOpcode new_op;
218
219 if (ts_are_copies(dst_ts, src_ts)) {
Aurelien Jarno53657182015-06-04 21:53:25 +0200220 tcg_op_remove(s, op);
221 return;
222 }
223
Richard Henderson63490392017-06-20 13:43:15 -0700224 reset_ts(dst_ts);
225 di = ts_info(dst_ts);
226 si = ts_info(src_ts);
Richard Henderson170ba882017-11-22 09:07:11 +0100227 def = &tcg_op_defs[op->opc];
228 if (def->flags & TCG_OPF_VECTOR) {
229 new_op = INDEX_op_mov_vec;
230 } else if (def->flags & TCG_OPF_64BIT) {
231 new_op = INDEX_op_mov_i64;
232 } else {
233 new_op = INDEX_op_mov_i32;
234 }
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700235 op->opc = new_op;
Richard Henderson170ba882017-11-22 09:07:11 +0100236 /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
Richard Henderson63490392017-06-20 13:43:15 -0700237 op->args[0] = dst;
238 op->args[1] = src;
Richard Hendersona62f6f52014-05-22 10:59:12 -0700239
Richard Henderson63490392017-06-20 13:43:15 -0700240 mask = si->mask;
Richard Henderson24666ba2014-05-22 11:14:10 -0700241 if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_mov_i32) {
242 /* High bits of the destination are now garbage. */
243 mask |= ~0xffffffffull;
244 }
Richard Henderson63490392017-06-20 13:43:15 -0700245 di->mask = mask;
Richard Henderson24666ba2014-05-22 11:14:10 -0700246
Richard Henderson63490392017-06-20 13:43:15 -0700247 if (src_ts->type == dst_ts->type) {
Richard Henderson6fcb98e2020-03-30 17:44:30 -0700248 TempOptInfo *ni = ts_info(si->next_copy);
Richard Henderson63490392017-06-20 13:43:15 -0700249
250 di->next_copy = si->next_copy;
251 di->prev_copy = src_ts;
252 ni->prev_copy = dst_ts;
253 si->next_copy = dst_ts;
254 di->is_const = si->is_const;
255 di->val = si->val;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800256 }
Kirill Batuzov22613af2011-07-07 16:37:13 +0400257}
258
Richard Henderson54795542020-09-06 16:21:32 -0700259static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400260{
Richard Henderson03271522013-08-14 14:35:56 -0700261 uint64_t l64, h64;
262
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400263 switch (op) {
264 CASE_OP_32_64(add):
265 return x + y;
266
267 CASE_OP_32_64(sub):
268 return x - y;
269
270 CASE_OP_32_64(mul):
271 return x * y;
272
Kirill Batuzov9a810902011-07-07 16:37:15 +0400273 CASE_OP_32_64(and):
274 return x & y;
275
276 CASE_OP_32_64(or):
277 return x | y;
278
279 CASE_OP_32_64(xor):
280 return x ^ y;
281
Kirill Batuzov55c09752011-07-07 16:37:16 +0400282 case INDEX_op_shl_i32:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700283 return (uint32_t)x << (y & 31);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400284
Kirill Batuzov55c09752011-07-07 16:37:16 +0400285 case INDEX_op_shl_i64:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700286 return (uint64_t)x << (y & 63);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400287
288 case INDEX_op_shr_i32:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700289 return (uint32_t)x >> (y & 31);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400290
Kirill Batuzov55c09752011-07-07 16:37:16 +0400291 case INDEX_op_shr_i64:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700292 return (uint64_t)x >> (y & 63);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400293
294 case INDEX_op_sar_i32:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700295 return (int32_t)x >> (y & 31);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400296
Kirill Batuzov55c09752011-07-07 16:37:16 +0400297 case INDEX_op_sar_i64:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700298 return (int64_t)x >> (y & 63);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400299
300 case INDEX_op_rotr_i32:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700301 return ror32(x, y & 31);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400302
Kirill Batuzov55c09752011-07-07 16:37:16 +0400303 case INDEX_op_rotr_i64:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700304 return ror64(x, y & 63);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400305
306 case INDEX_op_rotl_i32:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700307 return rol32(x, y & 31);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400308
Kirill Batuzov55c09752011-07-07 16:37:16 +0400309 case INDEX_op_rotl_i64:
Richard Henderson50c5c4d2014-03-18 07:45:39 -0700310 return rol64(x, y & 63);
Kirill Batuzov55c09752011-07-07 16:37:16 +0400311
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700312 CASE_OP_32_64(not):
Kirill Batuzova640f032011-07-07 16:37:17 +0400313 return ~x;
314
Richard Hendersoncb25c802011-08-17 14:11:47 -0700315 CASE_OP_32_64(neg):
316 return -x;
317
318 CASE_OP_32_64(andc):
319 return x & ~y;
320
321 CASE_OP_32_64(orc):
322 return x | ~y;
323
324 CASE_OP_32_64(eqv):
325 return ~(x ^ y);
326
327 CASE_OP_32_64(nand):
328 return ~(x & y);
329
330 CASE_OP_32_64(nor):
331 return ~(x | y);
332
Richard Henderson0e28d002016-11-16 09:23:28 +0100333 case INDEX_op_clz_i32:
334 return (uint32_t)x ? clz32(x) : y;
335
336 case INDEX_op_clz_i64:
337 return x ? clz64(x) : y;
338
339 case INDEX_op_ctz_i32:
340 return (uint32_t)x ? ctz32(x) : y;
341
342 case INDEX_op_ctz_i64:
343 return x ? ctz64(x) : y;
344
Richard Hendersona768e4e2016-11-21 11:13:39 +0100345 case INDEX_op_ctpop_i32:
346 return ctpop32(x);
347
348 case INDEX_op_ctpop_i64:
349 return ctpop64(x);
350
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700351 CASE_OP_32_64(ext8s):
Kirill Batuzova640f032011-07-07 16:37:17 +0400352 return (int8_t)x;
353
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700354 CASE_OP_32_64(ext16s):
Kirill Batuzova640f032011-07-07 16:37:17 +0400355 return (int16_t)x;
356
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700357 CASE_OP_32_64(ext8u):
Kirill Batuzova640f032011-07-07 16:37:17 +0400358 return (uint8_t)x;
359
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700360 CASE_OP_32_64(ext16u):
Kirill Batuzova640f032011-07-07 16:37:17 +0400361 return (uint16_t)x;
362
Richard Henderson64985942018-11-20 08:53:34 +0100363 CASE_OP_32_64(bswap16):
364 return bswap16(x);
365
366 CASE_OP_32_64(bswap32):
367 return bswap32(x);
368
369 case INDEX_op_bswap64_i64:
370 return bswap64(x);
371
Aurelien Jarno8bcb5c82015-07-27 12:41:45 +0200372 case INDEX_op_ext_i32_i64:
Kirill Batuzova640f032011-07-07 16:37:17 +0400373 case INDEX_op_ext32s_i64:
374 return (int32_t)x;
375
Aurelien Jarno8bcb5c82015-07-27 12:41:45 +0200376 case INDEX_op_extu_i32_i64:
Richard Henderson609ad702015-07-24 07:16:00 -0700377 case INDEX_op_extrl_i64_i32:
Kirill Batuzova640f032011-07-07 16:37:17 +0400378 case INDEX_op_ext32u_i64:
379 return (uint32_t)x;
Kirill Batuzova640f032011-07-07 16:37:17 +0400380
Richard Henderson609ad702015-07-24 07:16:00 -0700381 case INDEX_op_extrh_i64_i32:
382 return (uint64_t)x >> 32;
383
Richard Henderson03271522013-08-14 14:35:56 -0700384 case INDEX_op_muluh_i32:
385 return ((uint64_t)(uint32_t)x * (uint32_t)y) >> 32;
386 case INDEX_op_mulsh_i32:
387 return ((int64_t)(int32_t)x * (int32_t)y) >> 32;
388
389 case INDEX_op_muluh_i64:
390 mulu64(&l64, &h64, x, y);
391 return h64;
392 case INDEX_op_mulsh_i64:
393 muls64(&l64, &h64, x, y);
394 return h64;
395
Richard Henderson01547f72013-08-14 15:22:46 -0700396 case INDEX_op_div_i32:
397 /* Avoid crashing on divide by zero, otherwise undefined. */
398 return (int32_t)x / ((int32_t)y ? : 1);
399 case INDEX_op_divu_i32:
400 return (uint32_t)x / ((uint32_t)y ? : 1);
401 case INDEX_op_div_i64:
402 return (int64_t)x / ((int64_t)y ? : 1);
403 case INDEX_op_divu_i64:
404 return (uint64_t)x / ((uint64_t)y ? : 1);
405
406 case INDEX_op_rem_i32:
407 return (int32_t)x % ((int32_t)y ? : 1);
408 case INDEX_op_remu_i32:
409 return (uint32_t)x % ((uint32_t)y ? : 1);
410 case INDEX_op_rem_i64:
411 return (int64_t)x % ((int64_t)y ? : 1);
412 case INDEX_op_remu_i64:
413 return (uint64_t)x % ((uint64_t)y ? : 1);
414
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400415 default:
416 fprintf(stderr,
417 "Unrecognized operation %d in do_constant_folding.\n", op);
418 tcg_abort();
419 }
420}
421
Richard Henderson54795542020-09-06 16:21:32 -0700422static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y)
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400423{
Richard Henderson170ba882017-11-22 09:07:11 +0100424 const TCGOpDef *def = &tcg_op_defs[op];
Richard Henderson54795542020-09-06 16:21:32 -0700425 uint64_t res = do_constant_folding_2(op, x, y);
Richard Henderson170ba882017-11-22 09:07:11 +0100426 if (!(def->flags & TCG_OPF_64BIT)) {
Aurelien Jarno29f3ff82015-07-10 18:03:31 +0200427 res = (int32_t)res;
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400428 }
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400429 return res;
430}
431
Richard Henderson9519da72012-10-02 11:32:26 -0700432static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c)
433{
434 switch (c) {
435 case TCG_COND_EQ:
436 return x == y;
437 case TCG_COND_NE:
438 return x != y;
439 case TCG_COND_LT:
440 return (int32_t)x < (int32_t)y;
441 case TCG_COND_GE:
442 return (int32_t)x >= (int32_t)y;
443 case TCG_COND_LE:
444 return (int32_t)x <= (int32_t)y;
445 case TCG_COND_GT:
446 return (int32_t)x > (int32_t)y;
447 case TCG_COND_LTU:
448 return x < y;
449 case TCG_COND_GEU:
450 return x >= y;
451 case TCG_COND_LEU:
452 return x <= y;
453 case TCG_COND_GTU:
454 return x > y;
455 default:
456 tcg_abort();
457 }
458}
459
460static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c)
461{
462 switch (c) {
463 case TCG_COND_EQ:
464 return x == y;
465 case TCG_COND_NE:
466 return x != y;
467 case TCG_COND_LT:
468 return (int64_t)x < (int64_t)y;
469 case TCG_COND_GE:
470 return (int64_t)x >= (int64_t)y;
471 case TCG_COND_LE:
472 return (int64_t)x <= (int64_t)y;
473 case TCG_COND_GT:
474 return (int64_t)x > (int64_t)y;
475 case TCG_COND_LTU:
476 return x < y;
477 case TCG_COND_GEU:
478 return x >= y;
479 case TCG_COND_LEU:
480 return x <= y;
481 case TCG_COND_GTU:
482 return x > y;
483 default:
484 tcg_abort();
485 }
486}
487
488static bool do_constant_folding_cond_eq(TCGCond c)
489{
490 switch (c) {
491 case TCG_COND_GT:
492 case TCG_COND_LTU:
493 case TCG_COND_LT:
494 case TCG_COND_GTU:
495 case TCG_COND_NE:
496 return 0;
497 case TCG_COND_GE:
498 case TCG_COND_GEU:
499 case TCG_COND_LE:
500 case TCG_COND_LEU:
501 case TCG_COND_EQ:
502 return 1;
503 default:
504 tcg_abort();
505 }
506}
507
Aurelien Jarnob336ceb2012-09-18 19:37:00 +0200508/* Return 2 if the condition can't be simplified, and the result
509 of the condition (0 or 1) if it can */
Aurelien Jarnof8dd19e2012-09-06 16:47:14 +0200510static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
511 TCGArg y, TCGCond c)
512{
Richard Henderson54795542020-09-06 16:21:32 -0700513 uint64_t xv = arg_info(x)->val;
514 uint64_t yv = arg_info(y)->val;
515
Richard Henderson63490392017-06-20 13:43:15 -0700516 if (arg_is_const(x) && arg_is_const(y)) {
Richard Henderson170ba882017-11-22 09:07:11 +0100517 const TCGOpDef *def = &tcg_op_defs[op];
518 tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
519 if (def->flags & TCG_OPF_64BIT) {
Richard Henderson63490392017-06-20 13:43:15 -0700520 return do_constant_folding_cond_64(xv, yv, c);
Richard Henderson170ba882017-11-22 09:07:11 +0100521 } else {
522 return do_constant_folding_cond_32(xv, yv, c);
Aurelien Jarnof8dd19e2012-09-06 16:47:14 +0200523 }
Richard Henderson63490392017-06-20 13:43:15 -0700524 } else if (args_are_copies(x, y)) {
Richard Henderson9519da72012-10-02 11:32:26 -0700525 return do_constant_folding_cond_eq(c);
Richard Henderson63490392017-06-20 13:43:15 -0700526 } else if (arg_is_const(y) && yv == 0) {
Aurelien Jarnob336ceb2012-09-18 19:37:00 +0200527 switch (c) {
528 case TCG_COND_LTU:
529 return 0;
530 case TCG_COND_GEU:
531 return 1;
532 default:
533 return 2;
534 }
Aurelien Jarnof8dd19e2012-09-06 16:47:14 +0200535 }
Alex Bennée550276a2016-09-30 22:30:55 +0100536 return 2;
Aurelien Jarnof8dd19e2012-09-06 16:47:14 +0200537}
538
Richard Henderson6c4382f2012-10-02 11:32:27 -0700539/* Return 2 if the condition can't be simplified, and the result
540 of the condition (0 or 1) if it can */
541static TCGArg do_constant_folding_cond2(TCGArg *p1, TCGArg *p2, TCGCond c)
542{
543 TCGArg al = p1[0], ah = p1[1];
544 TCGArg bl = p2[0], bh = p2[1];
545
Richard Henderson63490392017-06-20 13:43:15 -0700546 if (arg_is_const(bl) && arg_is_const(bh)) {
547 tcg_target_ulong blv = arg_info(bl)->val;
548 tcg_target_ulong bhv = arg_info(bh)->val;
549 uint64_t b = deposit64(blv, 32, 32, bhv);
Richard Henderson6c4382f2012-10-02 11:32:27 -0700550
Richard Henderson63490392017-06-20 13:43:15 -0700551 if (arg_is_const(al) && arg_is_const(ah)) {
552 tcg_target_ulong alv = arg_info(al)->val;
553 tcg_target_ulong ahv = arg_info(ah)->val;
554 uint64_t a = deposit64(alv, 32, 32, ahv);
Richard Henderson6c4382f2012-10-02 11:32:27 -0700555 return do_constant_folding_cond_64(a, b, c);
556 }
557 if (b == 0) {
558 switch (c) {
559 case TCG_COND_LTU:
560 return 0;
561 case TCG_COND_GEU:
562 return 1;
563 default:
564 break;
565 }
566 }
567 }
Richard Henderson63490392017-06-20 13:43:15 -0700568 if (args_are_copies(al, bl) && args_are_copies(ah, bh)) {
Richard Henderson6c4382f2012-10-02 11:32:27 -0700569 return do_constant_folding_cond_eq(c);
570 }
571 return 2;
572}
573
Richard Henderson24c9ae42012-10-02 11:32:21 -0700574static bool swap_commutative(TCGArg dest, TCGArg *p1, TCGArg *p2)
575{
576 TCGArg a1 = *p1, a2 = *p2;
577 int sum = 0;
Richard Henderson63490392017-06-20 13:43:15 -0700578 sum += arg_is_const(a1);
579 sum -= arg_is_const(a2);
Richard Henderson24c9ae42012-10-02 11:32:21 -0700580
581 /* Prefer the constant in second argument, and then the form
582 op a, a, b, which is better handled on non-RISC hosts. */
583 if (sum > 0 || (sum == 0 && dest == a2)) {
584 *p1 = a2;
585 *p2 = a1;
586 return true;
587 }
588 return false;
589}
590
Richard Henderson0bfcb862012-10-02 11:32:23 -0700591static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
592{
593 int sum = 0;
Richard Henderson63490392017-06-20 13:43:15 -0700594 sum += arg_is_const(p1[0]);
595 sum += arg_is_const(p1[1]);
596 sum -= arg_is_const(p2[0]);
597 sum -= arg_is_const(p2[1]);
Richard Henderson0bfcb862012-10-02 11:32:23 -0700598 if (sum > 0) {
599 TCGArg t;
600 t = p1[0], p1[0] = p2[0], p2[0] = t;
601 t = p1[1], p1[1] = p2[1], p2[1] = t;
602 return true;
603 }
604 return false;
605}
606
Kirill Batuzov22613af2011-07-07 16:37:13 +0400607/* Propagate constants and copies, fold constant expressions. */
Aurelien Jarno36e60ef2015-06-04 21:53:27 +0200608void tcg_optimize(TCGContext *s)
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +0400609{
Richard Henderson15fa08f2017-11-02 15:19:14 +0100610 int nb_temps, nb_globals;
611 TCGOp *op, *op_next, *prev_mb = NULL;
Richard Henderson6fcb98e2020-03-30 17:44:30 -0700612 TempOptInfo *infos;
Emilio G. Cota34184b02017-07-19 14:32:24 -0400613 TCGTempSet temps_used;
Richard Henderson5d8f5362012-09-21 10:13:38 -0700614
Kirill Batuzov22613af2011-07-07 16:37:13 +0400615 /* Array VALS has an element for each temp.
616 If this temp holds a constant then its value is kept in VALS' element.
Aurelien Jarnoe590d4e2012-09-11 12:31:21 +0200617 If this temp is a copy of other ones then the other copies are
618 available through the doubly linked circular list. */
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +0400619
620 nb_temps = s->nb_temps;
621 nb_globals = s->nb_globals;
Emilio G. Cota34184b02017-07-19 14:32:24 -0400622 bitmap_zero(temps_used.l, nb_temps);
Richard Henderson6fcb98e2020-03-30 17:44:30 -0700623 infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps);
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +0400624
Richard Henderson15fa08f2017-11-02 15:19:14 +0100625 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
Richard Henderson54795542020-09-06 16:21:32 -0700626 uint64_t mask, partmask, affected, tmp;
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700627 int nb_oargs, nb_iargs, i;
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700628 TCGOpcode opc = op->opc;
629 const TCGOpDef *def = &tcg_op_defs[opc];
630
Aurelien Jarno1208d7d2015-07-27 12:41:44 +0200631 /* Count the arguments, and initialize the temps that are
632 going to be used */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700633 if (opc == INDEX_op_call) {
Richard Hendersoncd9090a2017-11-14 13:02:51 +0100634 nb_oargs = TCGOP_CALLO(op);
635 nb_iargs = TCGOP_CALLI(op);
Aurelien Jarno1208d7d2015-07-27 12:41:44 +0200636 for (i = 0; i < nb_oargs + nb_iargs; i++) {
Richard Henderson63490392017-06-20 13:43:15 -0700637 TCGTemp *ts = arg_temp(op->args[i]);
638 if (ts) {
Emilio G. Cota34184b02017-07-19 14:32:24 -0400639 init_ts_info(infos, &temps_used, ts);
Aurelien Jarno1208d7d2015-07-27 12:41:44 +0200640 }
641 }
Aurelien Jarno1ff8c542012-09-11 16:18:49 +0200642 } else {
Richard Hendersoncf066672014-03-22 20:06:52 -0700643 nb_oargs = def->nb_oargs;
644 nb_iargs = def->nb_iargs;
Aurelien Jarno1208d7d2015-07-27 12:41:44 +0200645 for (i = 0; i < nb_oargs + nb_iargs; i++) {
Emilio G. Cota34184b02017-07-19 14:32:24 -0400646 init_arg_info(infos, &temps_used, op->args[i]);
Aurelien Jarno1208d7d2015-07-27 12:41:44 +0200647 }
Richard Hendersoncf066672014-03-22 20:06:52 -0700648 }
649
650 /* Do copy propagation */
651 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
Richard Henderson63490392017-06-20 13:43:15 -0700652 TCGTemp *ts = arg_temp(op->args[i]);
653 if (ts && ts_is_copy(ts)) {
654 op->args[i] = temp_arg(find_better_copy(s, ts));
Kirill Batuzov22613af2011-07-07 16:37:13 +0400655 }
656 }
657
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400658 /* For commutative operations make constant second argument */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700659 switch (opc) {
Richard Henderson170ba882017-11-22 09:07:11 +0100660 CASE_OP_32_64_VEC(add):
661 CASE_OP_32_64_VEC(mul):
662 CASE_OP_32_64_VEC(and):
663 CASE_OP_32_64_VEC(or):
664 CASE_OP_32_64_VEC(xor):
Richard Hendersoncb25c802011-08-17 14:11:47 -0700665 CASE_OP_32_64(eqv):
666 CASE_OP_32_64(nand):
667 CASE_OP_32_64(nor):
Richard Henderson03271522013-08-14 14:35:56 -0700668 CASE_OP_32_64(muluh):
669 CASE_OP_32_64(mulsh):
Richard Hendersonacd93702016-12-08 12:28:42 -0800670 swap_commutative(op->args[0], &op->args[1], &op->args[2]);
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400671 break;
Aurelien Jarno65a7cce2012-09-06 16:47:14 +0200672 CASE_OP_32_64(brcond):
Richard Hendersonacd93702016-12-08 12:28:42 -0800673 if (swap_commutative(-1, &op->args[0], &op->args[1])) {
674 op->args[2] = tcg_swap_cond(op->args[2]);
Aurelien Jarno65a7cce2012-09-06 16:47:14 +0200675 }
676 break;
677 CASE_OP_32_64(setcond):
Richard Hendersonacd93702016-12-08 12:28:42 -0800678 if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) {
679 op->args[3] = tcg_swap_cond(op->args[3]);
Aurelien Jarno65a7cce2012-09-06 16:47:14 +0200680 }
681 break;
Richard Hendersonfa01a202012-09-21 10:13:37 -0700682 CASE_OP_32_64(movcond):
Richard Hendersonacd93702016-12-08 12:28:42 -0800683 if (swap_commutative(-1, &op->args[1], &op->args[2])) {
684 op->args[5] = tcg_swap_cond(op->args[5]);
Richard Hendersonfa01a202012-09-21 10:13:37 -0700685 }
Richard Henderson5d8f5362012-09-21 10:13:38 -0700686 /* For movcond, we canonicalize the "false" input reg to match
687 the destination reg so that the tcg backend can implement
688 a "move if true" operation. */
Richard Hendersonacd93702016-12-08 12:28:42 -0800689 if (swap_commutative(op->args[0], &op->args[4], &op->args[3])) {
690 op->args[5] = tcg_invert_cond(op->args[5]);
Richard Henderson5d8f5362012-09-21 10:13:38 -0700691 }
Richard Henderson1e484e62012-10-02 11:32:22 -0700692 break;
Richard Hendersond7156f72013-02-19 23:51:52 -0800693 CASE_OP_32_64(add2):
Richard Hendersonacd93702016-12-08 12:28:42 -0800694 swap_commutative(op->args[0], &op->args[2], &op->args[4]);
695 swap_commutative(op->args[1], &op->args[3], &op->args[5]);
Richard Henderson1e484e62012-10-02 11:32:22 -0700696 break;
Richard Hendersond7156f72013-02-19 23:51:52 -0800697 CASE_OP_32_64(mulu2):
Richard Henderson4d3203f2013-02-19 23:51:53 -0800698 CASE_OP_32_64(muls2):
Richard Hendersonacd93702016-12-08 12:28:42 -0800699 swap_commutative(op->args[0], &op->args[2], &op->args[3]);
Richard Henderson14149682012-10-02 11:32:30 -0700700 break;
Richard Henderson0bfcb862012-10-02 11:32:23 -0700701 case INDEX_op_brcond2_i32:
Richard Hendersonacd93702016-12-08 12:28:42 -0800702 if (swap_commutative2(&op->args[0], &op->args[2])) {
703 op->args[4] = tcg_swap_cond(op->args[4]);
Richard Henderson0bfcb862012-10-02 11:32:23 -0700704 }
705 break;
706 case INDEX_op_setcond2_i32:
Richard Hendersonacd93702016-12-08 12:28:42 -0800707 if (swap_commutative2(&op->args[1], &op->args[3])) {
708 op->args[5] = tcg_swap_cond(op->args[5]);
Richard Henderson0bfcb862012-10-02 11:32:23 -0700709 }
710 break;
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400711 default:
712 break;
713 }
714
Richard Henderson2d497542013-03-21 09:13:33 -0700715 /* Simplify expressions for "shift/rot r, 0, a => movi r, 0",
716 and "sub r, 0, a => neg r, a" case. */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700717 switch (opc) {
Aurelien Jarno01ee5282012-09-06 16:47:14 +0200718 CASE_OP_32_64(shl):
719 CASE_OP_32_64(shr):
720 CASE_OP_32_64(sar):
721 CASE_OP_32_64(rotl):
722 CASE_OP_32_64(rotr):
Richard Henderson63490392017-06-20 13:43:15 -0700723 if (arg_is_const(op->args[1])
724 && arg_info(op->args[1])->val == 0) {
Richard Hendersonacd93702016-12-08 12:28:42 -0800725 tcg_opt_gen_movi(s, op, op->args[0], 0);
Aurelien Jarno01ee5282012-09-06 16:47:14 +0200726 continue;
727 }
728 break;
Richard Henderson170ba882017-11-22 09:07:11 +0100729 CASE_OP_32_64_VEC(sub):
Richard Henderson2d497542013-03-21 09:13:33 -0700730 {
731 TCGOpcode neg_op;
732 bool have_neg;
733
Richard Henderson63490392017-06-20 13:43:15 -0700734 if (arg_is_const(op->args[2])) {
Richard Henderson2d497542013-03-21 09:13:33 -0700735 /* Proceed with possible constant folding. */
736 break;
737 }
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700738 if (opc == INDEX_op_sub_i32) {
Richard Henderson2d497542013-03-21 09:13:33 -0700739 neg_op = INDEX_op_neg_i32;
740 have_neg = TCG_TARGET_HAS_neg_i32;
Richard Henderson170ba882017-11-22 09:07:11 +0100741 } else if (opc == INDEX_op_sub_i64) {
Richard Henderson2d497542013-03-21 09:13:33 -0700742 neg_op = INDEX_op_neg_i64;
743 have_neg = TCG_TARGET_HAS_neg_i64;
Richard Hendersonac383dde2019-04-20 00:27:24 +0000744 } else if (TCG_TARGET_HAS_neg_vec) {
745 TCGType type = TCGOP_VECL(op) + TCG_TYPE_V64;
746 unsigned vece = TCGOP_VECE(op);
Richard Henderson170ba882017-11-22 09:07:11 +0100747 neg_op = INDEX_op_neg_vec;
Richard Hendersonac383dde2019-04-20 00:27:24 +0000748 have_neg = tcg_can_emit_vec_op(neg_op, type, vece) > 0;
749 } else {
750 break;
Richard Henderson2d497542013-03-21 09:13:33 -0700751 }
752 if (!have_neg) {
753 break;
754 }
Richard Henderson63490392017-06-20 13:43:15 -0700755 if (arg_is_const(op->args[1])
756 && arg_info(op->args[1])->val == 0) {
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700757 op->opc = neg_op;
Richard Hendersonacd93702016-12-08 12:28:42 -0800758 reset_temp(op->args[0]);
759 op->args[1] = op->args[2];
Richard Henderson2d497542013-03-21 09:13:33 -0700760 continue;
761 }
762 }
763 break;
Richard Henderson170ba882017-11-22 09:07:11 +0100764 CASE_OP_32_64_VEC(xor):
Richard Hendersone201b562014-01-28 13:15:38 -0800765 CASE_OP_32_64(nand):
Richard Henderson63490392017-06-20 13:43:15 -0700766 if (!arg_is_const(op->args[1])
767 && arg_is_const(op->args[2])
768 && arg_info(op->args[2])->val == -1) {
Richard Hendersone201b562014-01-28 13:15:38 -0800769 i = 1;
770 goto try_not;
771 }
772 break;
773 CASE_OP_32_64(nor):
Richard Henderson63490392017-06-20 13:43:15 -0700774 if (!arg_is_const(op->args[1])
775 && arg_is_const(op->args[2])
776 && arg_info(op->args[2])->val == 0) {
Richard Hendersone201b562014-01-28 13:15:38 -0800777 i = 1;
778 goto try_not;
779 }
780 break;
Richard Henderson170ba882017-11-22 09:07:11 +0100781 CASE_OP_32_64_VEC(andc):
Richard Henderson63490392017-06-20 13:43:15 -0700782 if (!arg_is_const(op->args[2])
783 && arg_is_const(op->args[1])
784 && arg_info(op->args[1])->val == -1) {
Richard Hendersone201b562014-01-28 13:15:38 -0800785 i = 2;
786 goto try_not;
787 }
788 break;
Richard Henderson170ba882017-11-22 09:07:11 +0100789 CASE_OP_32_64_VEC(orc):
Richard Hendersone201b562014-01-28 13:15:38 -0800790 CASE_OP_32_64(eqv):
Richard Henderson63490392017-06-20 13:43:15 -0700791 if (!arg_is_const(op->args[2])
792 && arg_is_const(op->args[1])
793 && arg_info(op->args[1])->val == 0) {
Richard Hendersone201b562014-01-28 13:15:38 -0800794 i = 2;
795 goto try_not;
796 }
797 break;
798 try_not:
799 {
800 TCGOpcode not_op;
801 bool have_not;
802
Richard Henderson170ba882017-11-22 09:07:11 +0100803 if (def->flags & TCG_OPF_VECTOR) {
804 not_op = INDEX_op_not_vec;
805 have_not = TCG_TARGET_HAS_not_vec;
806 } else if (def->flags & TCG_OPF_64BIT) {
Richard Hendersone201b562014-01-28 13:15:38 -0800807 not_op = INDEX_op_not_i64;
808 have_not = TCG_TARGET_HAS_not_i64;
809 } else {
810 not_op = INDEX_op_not_i32;
811 have_not = TCG_TARGET_HAS_not_i32;
812 }
813 if (!have_not) {
814 break;
815 }
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700816 op->opc = not_op;
Richard Hendersonacd93702016-12-08 12:28:42 -0800817 reset_temp(op->args[0]);
818 op->args[1] = op->args[i];
Richard Hendersone201b562014-01-28 13:15:38 -0800819 continue;
820 }
Aurelien Jarno01ee5282012-09-06 16:47:14 +0200821 default:
822 break;
823 }
824
Richard Henderson464a1442014-01-31 07:42:11 -0600825 /* Simplify expression for "op r, a, const => mov r, a" cases */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700826 switch (opc) {
Richard Henderson170ba882017-11-22 09:07:11 +0100827 CASE_OP_32_64_VEC(add):
828 CASE_OP_32_64_VEC(sub):
829 CASE_OP_32_64_VEC(or):
830 CASE_OP_32_64_VEC(xor):
831 CASE_OP_32_64_VEC(andc):
Kirill Batuzov55c09752011-07-07 16:37:16 +0400832 CASE_OP_32_64(shl):
833 CASE_OP_32_64(shr):
834 CASE_OP_32_64(sar):
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700835 CASE_OP_32_64(rotl):
836 CASE_OP_32_64(rotr):
Richard Henderson63490392017-06-20 13:43:15 -0700837 if (!arg_is_const(op->args[1])
838 && arg_is_const(op->args[2])
839 && arg_info(op->args[2])->val == 0) {
Richard Hendersonacd93702016-12-08 12:28:42 -0800840 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200841 continue;
Kirill Batuzov53108fb2011-07-07 16:37:14 +0400842 }
843 break;
Richard Henderson170ba882017-11-22 09:07:11 +0100844 CASE_OP_32_64_VEC(and):
845 CASE_OP_32_64_VEC(orc):
Richard Henderson464a1442014-01-31 07:42:11 -0600846 CASE_OP_32_64(eqv):
Richard Henderson63490392017-06-20 13:43:15 -0700847 if (!arg_is_const(op->args[1])
848 && arg_is_const(op->args[2])
849 && arg_info(op->args[2])->val == -1) {
Richard Hendersonacd93702016-12-08 12:28:42 -0800850 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
Aurelien Jarno97a79eb2015-06-05 11:19:18 +0200851 continue;
Richard Henderson464a1442014-01-31 07:42:11 -0600852 }
853 break;
Aurelien Jarno56e49432012-09-06 16:47:13 +0200854 default:
855 break;
856 }
857
Aurelien Jarno30312442013-09-03 08:27:38 +0200858 /* Simplify using known-zero bits. Currently only ops with a single
859 output argument is supported. */
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800860 mask = -1;
Paolo Bonzini633f6502013-01-11 15:42:53 -0800861 affected = -1;
Richard Hendersonc45cb8b2014-09-19 13:49:15 -0700862 switch (opc) {
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800863 CASE_OP_32_64(ext8s):
Richard Henderson63490392017-06-20 13:43:15 -0700864 if ((arg_info(op->args[1])->mask & 0x80) != 0) {
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800865 break;
866 }
Thomas Huthd84568b2020-12-11 16:24:24 +0100867 QEMU_FALLTHROUGH;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800868 CASE_OP_32_64(ext8u):
869 mask = 0xff;
870 goto and_const;
871 CASE_OP_32_64(ext16s):
Richard Henderson63490392017-06-20 13:43:15 -0700872 if ((arg_info(op->args[1])->mask & 0x8000) != 0) {
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800873 break;
874 }
Thomas Huthd84568b2020-12-11 16:24:24 +0100875 QEMU_FALLTHROUGH;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800876 CASE_OP_32_64(ext16u):
877 mask = 0xffff;
878 goto and_const;
879 case INDEX_op_ext32s_i64:
Richard Henderson63490392017-06-20 13:43:15 -0700880 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800881 break;
882 }
Thomas Huthd84568b2020-12-11 16:24:24 +0100883 QEMU_FALLTHROUGH;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800884 case INDEX_op_ext32u_i64:
885 mask = 0xffffffffU;
886 goto and_const;
887
888 CASE_OP_32_64(and):
Richard Henderson63490392017-06-20 13:43:15 -0700889 mask = arg_info(op->args[2])->mask;
890 if (arg_is_const(op->args[2])) {
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800891 and_const:
Richard Henderson63490392017-06-20 13:43:15 -0700892 affected = arg_info(op->args[1])->mask & ~mask;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800893 }
Richard Henderson63490392017-06-20 13:43:15 -0700894 mask = arg_info(op->args[1])->mask & mask;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800895 break;
896
Aurelien Jarno8bcb5c82015-07-27 12:41:45 +0200897 case INDEX_op_ext_i32_i64:
Richard Henderson63490392017-06-20 13:43:15 -0700898 if ((arg_info(op->args[1])->mask & 0x80000000) != 0) {
Aurelien Jarno8bcb5c82015-07-27 12:41:45 +0200899 break;
900 }
Thomas Huthd84568b2020-12-11 16:24:24 +0100901 QEMU_FALLTHROUGH;
Aurelien Jarno8bcb5c82015-07-27 12:41:45 +0200902 case INDEX_op_extu_i32_i64:
903 /* We do not compute affected as it is a size changing op. */
Richard Henderson63490392017-06-20 13:43:15 -0700904 mask = (uint32_t)arg_info(op->args[1])->mask;
Aurelien Jarno8bcb5c82015-07-27 12:41:45 +0200905 break;
906
Richard Henderson23ec69ed2014-01-28 12:03:24 -0800907 CASE_OP_32_64(andc):
908 /* Known-zeros does not imply known-ones. Therefore unless
Richard Hendersonacd93702016-12-08 12:28:42 -0800909 op->args[2] is constant, we can't infer anything from it. */
Richard Henderson63490392017-06-20 13:43:15 -0700910 if (arg_is_const(op->args[2])) {
911 mask = ~arg_info(op->args[2])->mask;
Richard Henderson23ec69ed2014-01-28 12:03:24 -0800912 goto and_const;
913 }
Richard Henderson63490392017-06-20 13:43:15 -0700914 /* But we certainly know nothing outside args[1] may be set. */
915 mask = arg_info(op->args[1])->mask;
Richard Henderson23ec69ed2014-01-28 12:03:24 -0800916 break;
917
Aurelien Jarnoe46b2252013-09-03 08:27:38 +0200918 case INDEX_op_sar_i32:
Richard Henderson63490392017-06-20 13:43:15 -0700919 if (arg_is_const(op->args[2])) {
920 tmp = arg_info(op->args[2])->val & 31;
921 mask = (int32_t)arg_info(op->args[1])->mask >> tmp;
Aurelien Jarnoe46b2252013-09-03 08:27:38 +0200922 }
923 break;
924 case INDEX_op_sar_i64:
Richard Henderson63490392017-06-20 13:43:15 -0700925 if (arg_is_const(op->args[2])) {
926 tmp = arg_info(op->args[2])->val & 63;
927 mask = (int64_t)arg_info(op->args[1])->mask >> tmp;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800928 }
929 break;
930
Aurelien Jarnoe46b2252013-09-03 08:27:38 +0200931 case INDEX_op_shr_i32:
Richard Henderson63490392017-06-20 13:43:15 -0700932 if (arg_is_const(op->args[2])) {
933 tmp = arg_info(op->args[2])->val & 31;
934 mask = (uint32_t)arg_info(op->args[1])->mask >> tmp;
Aurelien Jarnoe46b2252013-09-03 08:27:38 +0200935 }
936 break;
937 case INDEX_op_shr_i64:
Richard Henderson63490392017-06-20 13:43:15 -0700938 if (arg_is_const(op->args[2])) {
939 tmp = arg_info(op->args[2])->val & 63;
940 mask = (uint64_t)arg_info(op->args[1])->mask >> tmp;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800941 }
942 break;
943
Richard Henderson609ad702015-07-24 07:16:00 -0700944 case INDEX_op_extrl_i64_i32:
Richard Henderson63490392017-06-20 13:43:15 -0700945 mask = (uint32_t)arg_info(op->args[1])->mask;
Richard Henderson609ad702015-07-24 07:16:00 -0700946 break;
947 case INDEX_op_extrh_i64_i32:
Richard Henderson63490392017-06-20 13:43:15 -0700948 mask = (uint64_t)arg_info(op->args[1])->mask >> 32;
Richard Henderson4bb7a412013-09-09 17:03:24 -0700949 break;
950
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800951 CASE_OP_32_64(shl):
Richard Henderson63490392017-06-20 13:43:15 -0700952 if (arg_is_const(op->args[2])) {
953 tmp = arg_info(op->args[2])->val & (TCG_TARGET_REG_BITS - 1);
954 mask = arg_info(op->args[1])->mask << tmp;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800955 }
956 break;
957
958 CASE_OP_32_64(neg):
959 /* Set to 1 all bits to the left of the rightmost. */
Richard Henderson63490392017-06-20 13:43:15 -0700960 mask = -(arg_info(op->args[1])->mask
961 & -arg_info(op->args[1])->mask);
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800962 break;
963
964 CASE_OP_32_64(deposit):
Richard Henderson63490392017-06-20 13:43:15 -0700965 mask = deposit64(arg_info(op->args[1])->mask,
966 op->args[3], op->args[4],
967 arg_info(op->args[2])->mask);
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800968 break;
969
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500970 CASE_OP_32_64(extract):
Richard Henderson63490392017-06-20 13:43:15 -0700971 mask = extract64(arg_info(op->args[1])->mask,
972 op->args[2], op->args[3]);
Richard Hendersonacd93702016-12-08 12:28:42 -0800973 if (op->args[2] == 0) {
Richard Henderson63490392017-06-20 13:43:15 -0700974 affected = arg_info(op->args[1])->mask & ~mask;
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500975 }
976 break;
977 CASE_OP_32_64(sextract):
Richard Henderson63490392017-06-20 13:43:15 -0700978 mask = sextract64(arg_info(op->args[1])->mask,
Richard Hendersonacd93702016-12-08 12:28:42 -0800979 op->args[2], op->args[3]);
980 if (op->args[2] == 0 && (tcg_target_long)mask >= 0) {
Richard Henderson63490392017-06-20 13:43:15 -0700981 affected = arg_info(op->args[1])->mask & ~mask;
Richard Henderson7ec8bab2016-10-14 12:04:32 -0500982 }
983 break;
984
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800985 CASE_OP_32_64(or):
986 CASE_OP_32_64(xor):
Richard Henderson63490392017-06-20 13:43:15 -0700987 mask = arg_info(op->args[1])->mask | arg_info(op->args[2])->mask;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -0800988 break;
989
Richard Henderson0e28d002016-11-16 09:23:28 +0100990 case INDEX_op_clz_i32:
991 case INDEX_op_ctz_i32:
Richard Henderson63490392017-06-20 13:43:15 -0700992 mask = arg_info(op->args[2])->mask | 31;
Richard Henderson0e28d002016-11-16 09:23:28 +0100993 break;
994
995 case INDEX_op_clz_i64:
996 case INDEX_op_ctz_i64:
Richard Henderson63490392017-06-20 13:43:15 -0700997 mask = arg_info(op->args[2])->mask | 63;
Richard Henderson0e28d002016-11-16 09:23:28 +0100998 break;
999
Richard Hendersona768e4e2016-11-21 11:13:39 +01001000 case INDEX_op_ctpop_i32:
1001 mask = 32 | 31;
1002 break;
1003 case INDEX_op_ctpop_i64:
1004 mask = 64 | 63;
1005 break;
1006
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -08001007 CASE_OP_32_64(setcond):
Richard Hendersona7635512014-04-23 22:18:30 -07001008 case INDEX_op_setcond2_i32:
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -08001009 mask = 1;
1010 break;
1011
1012 CASE_OP_32_64(movcond):
Richard Henderson63490392017-06-20 13:43:15 -07001013 mask = arg_info(op->args[3])->mask | arg_info(op->args[4])->mask;
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -08001014 break;
1015
Aurelien Jarnoc8d70272013-09-03 08:27:39 +02001016 CASE_OP_32_64(ld8u):
Aurelien Jarnoc8d70272013-09-03 08:27:39 +02001017 mask = 0xff;
1018 break;
1019 CASE_OP_32_64(ld16u):
Aurelien Jarnoc8d70272013-09-03 08:27:39 +02001020 mask = 0xffff;
1021 break;
1022 case INDEX_op_ld32u_i64:
Aurelien Jarnoc8d70272013-09-03 08:27:39 +02001023 mask = 0xffffffffu;
1024 break;
1025
1026 CASE_OP_32_64(qemu_ld):
1027 {
Richard Hendersonacd93702016-12-08 12:28:42 -08001028 TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
Tony Nguyen14776ab2019-08-24 04:10:58 +10001029 MemOp mop = get_memop(oi);
Aurelien Jarnoc8d70272013-09-03 08:27:39 +02001030 if (!(mop & MO_SIGN)) {
1031 mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
1032 }
1033 }
1034 break;
1035
Paolo Bonzini3a9d8b12013-01-11 15:42:52 -08001036 default:
1037 break;
1038 }
1039
Richard Hendersonbc8d6882014-06-08 18:24:14 -07001040 /* 32-bit ops generate 32-bit results. For the result is zero test
1041 below, we can ignore high bits, but for further optimizations we
1042 need to record that the high bits contain garbage. */
Richard Henderson24666ba2014-05-22 11:14:10 -07001043 partmask = mask;
Richard Hendersonbc8d6882014-06-08 18:24:14 -07001044 if (!(def->flags & TCG_OPF_64BIT)) {
Richard Henderson24666ba2014-05-22 11:14:10 -07001045 mask |= ~(tcg_target_ulong)0xffffffffu;
1046 partmask &= 0xffffffffu;
1047 affected &= 0xffffffffu;
Aurelien Jarnof096dc92013-09-03 08:27:38 +02001048 }
1049
Richard Henderson24666ba2014-05-22 11:14:10 -07001050 if (partmask == 0) {
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +02001051 tcg_debug_assert(nb_oargs == 1);
Richard Hendersonacd93702016-12-08 12:28:42 -08001052 tcg_opt_gen_movi(s, op, op->args[0], 0);
Paolo Bonzini633f6502013-01-11 15:42:53 -08001053 continue;
1054 }
1055 if (affected == 0) {
Aurelien Jarnoeabb7b92016-04-21 10:48:49 +02001056 tcg_debug_assert(nb_oargs == 1);
Richard Hendersonacd93702016-12-08 12:28:42 -08001057 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
Paolo Bonzini633f6502013-01-11 15:42:53 -08001058 continue;
1059 }
1060
Aurelien Jarno56e49432012-09-06 16:47:13 +02001061 /* Simplify expression for "op r, a, 0 => movi r, 0" cases */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001062 switch (opc) {
Richard Henderson170ba882017-11-22 09:07:11 +01001063 CASE_OP_32_64_VEC(and):
1064 CASE_OP_32_64_VEC(mul):
Richard Henderson03271522013-08-14 14:35:56 -07001065 CASE_OP_32_64(muluh):
1066 CASE_OP_32_64(mulsh):
Richard Henderson63490392017-06-20 13:43:15 -07001067 if (arg_is_const(op->args[2])
1068 && arg_info(op->args[2])->val == 0) {
Richard Hendersonacd93702016-12-08 12:28:42 -08001069 tcg_opt_gen_movi(s, op, op->args[0], 0);
Kirill Batuzov53108fb2011-07-07 16:37:14 +04001070 continue;
1071 }
1072 break;
Aurelien Jarno56e49432012-09-06 16:47:13 +02001073 default:
1074 break;
1075 }
1076
1077 /* Simplify expression for "op r, a, a => mov r, a" cases */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001078 switch (opc) {
Richard Henderson170ba882017-11-22 09:07:11 +01001079 CASE_OP_32_64_VEC(or):
1080 CASE_OP_32_64_VEC(and):
Richard Henderson63490392017-06-20 13:43:15 -07001081 if (args_are_copies(op->args[1], op->args[2])) {
Richard Hendersonacd93702016-12-08 12:28:42 -08001082 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
Kirill Batuzov9a810902011-07-07 16:37:15 +04001083 continue;
1084 }
1085 break;
Blue Swirlfe0de7a2011-07-30 19:18:32 +00001086 default:
1087 break;
Kirill Batuzov53108fb2011-07-07 16:37:14 +04001088 }
1089
Aurelien Jarno3c941932012-09-18 19:12:36 +02001090 /* Simplify expression for "op r, a, a => movi r, 0" cases */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001091 switch (opc) {
Richard Henderson170ba882017-11-22 09:07:11 +01001092 CASE_OP_32_64_VEC(andc):
1093 CASE_OP_32_64_VEC(sub):
1094 CASE_OP_32_64_VEC(xor):
Richard Henderson63490392017-06-20 13:43:15 -07001095 if (args_are_copies(op->args[1], op->args[2])) {
Richard Hendersonacd93702016-12-08 12:28:42 -08001096 tcg_opt_gen_movi(s, op, op->args[0], 0);
Aurelien Jarno3c941932012-09-18 19:12:36 +02001097 continue;
1098 }
1099 break;
1100 default:
1101 break;
1102 }
1103
Kirill Batuzov22613af2011-07-07 16:37:13 +04001104 /* Propagate constants through copy operations and do constant
1105 folding. Constants will be substituted to arguments by register
1106 allocator where needed and possible. Also detect copies. */
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001107 switch (opc) {
Richard Henderson170ba882017-11-22 09:07:11 +01001108 CASE_OP_32_64_VEC(mov):
Richard Hendersonacd93702016-12-08 12:28:42 -08001109 tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
Aurelien Jarno97a79eb2015-06-05 11:19:18 +02001110 break;
Kirill Batuzov22613af2011-07-07 16:37:13 +04001111 CASE_OP_32_64(movi):
Richard Henderson170ba882017-11-22 09:07:11 +01001112 case INDEX_op_dupi_vec:
Richard Hendersonacd93702016-12-08 12:28:42 -08001113 tcg_opt_gen_movi(s, op, op->args[0], op->args[1]);
Kirill Batuzov22613af2011-07-07 16:37:13 +04001114 break;
Richard Henderson6e14e912012-10-02 11:32:24 -07001115
Richard Henderson170ba882017-11-22 09:07:11 +01001116 case INDEX_op_dup_vec:
1117 if (arg_is_const(op->args[1])) {
1118 tmp = arg_info(op->args[1])->val;
1119 tmp = dup_const(TCGOP_VECE(op), tmp);
1120 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson1fb57da72018-08-05 16:32:58 -07001121 break;
Richard Henderson170ba882017-11-22 09:07:11 +01001122 }
Richard Henderson1fb57da72018-08-05 16:32:58 -07001123 goto do_default;
Richard Henderson170ba882017-11-22 09:07:11 +01001124
Richard Henderson1dc4fe72020-09-05 17:03:35 -07001125 case INDEX_op_dup2_vec:
1126 assert(TCG_TARGET_REG_BITS == 32);
1127 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1128 tmp = arg_info(op->args[1])->val;
1129 if (tmp == arg_info(op->args[2])->val) {
1130 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1131 break;
1132 }
1133 } else if (args_are_copies(op->args[1], op->args[2])) {
1134 op->opc = INDEX_op_dup_vec;
1135 TCGOP_VECE(op) = MO_32;
1136 nb_iargs = 1;
1137 }
1138 goto do_default;
1139
Kirill Batuzova640f032011-07-07 16:37:17 +04001140 CASE_OP_32_64(not):
Richard Hendersoncb25c802011-08-17 14:11:47 -07001141 CASE_OP_32_64(neg):
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001142 CASE_OP_32_64(ext8s):
1143 CASE_OP_32_64(ext8u):
1144 CASE_OP_32_64(ext16s):
1145 CASE_OP_32_64(ext16u):
Richard Hendersona768e4e2016-11-21 11:13:39 +01001146 CASE_OP_32_64(ctpop):
Richard Henderson64985942018-11-20 08:53:34 +01001147 CASE_OP_32_64(bswap16):
1148 CASE_OP_32_64(bswap32):
1149 case INDEX_op_bswap64_i64:
Kirill Batuzova640f032011-07-07 16:37:17 +04001150 case INDEX_op_ext32s_i64:
1151 case INDEX_op_ext32u_i64:
Aurelien Jarno8bcb5c82015-07-27 12:41:45 +02001152 case INDEX_op_ext_i32_i64:
1153 case INDEX_op_extu_i32_i64:
Richard Henderson609ad702015-07-24 07:16:00 -07001154 case INDEX_op_extrl_i64_i32:
1155 case INDEX_op_extrh_i64_i32:
Richard Henderson63490392017-06-20 13:43:15 -07001156 if (arg_is_const(op->args[1])) {
1157 tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
Richard Hendersonacd93702016-12-08 12:28:42 -08001158 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson6e14e912012-10-02 11:32:24 -07001159 break;
Kirill Batuzova640f032011-07-07 16:37:17 +04001160 }
Richard Henderson6e14e912012-10-02 11:32:24 -07001161 goto do_default;
1162
Kirill Batuzov53108fb2011-07-07 16:37:14 +04001163 CASE_OP_32_64(add):
1164 CASE_OP_32_64(sub):
1165 CASE_OP_32_64(mul):
Kirill Batuzov9a810902011-07-07 16:37:15 +04001166 CASE_OP_32_64(or):
1167 CASE_OP_32_64(and):
1168 CASE_OP_32_64(xor):
Kirill Batuzov55c09752011-07-07 16:37:16 +04001169 CASE_OP_32_64(shl):
1170 CASE_OP_32_64(shr):
1171 CASE_OP_32_64(sar):
Richard Henderson25c4d9c2011-08-17 14:11:46 -07001172 CASE_OP_32_64(rotl):
1173 CASE_OP_32_64(rotr):
Richard Hendersoncb25c802011-08-17 14:11:47 -07001174 CASE_OP_32_64(andc):
1175 CASE_OP_32_64(orc):
1176 CASE_OP_32_64(eqv):
1177 CASE_OP_32_64(nand):
1178 CASE_OP_32_64(nor):
Richard Henderson03271522013-08-14 14:35:56 -07001179 CASE_OP_32_64(muluh):
1180 CASE_OP_32_64(mulsh):
Richard Henderson01547f72013-08-14 15:22:46 -07001181 CASE_OP_32_64(div):
1182 CASE_OP_32_64(divu):
1183 CASE_OP_32_64(rem):
1184 CASE_OP_32_64(remu):
Richard Henderson63490392017-06-20 13:43:15 -07001185 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1186 tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
1187 arg_info(op->args[2])->val);
Richard Hendersonacd93702016-12-08 12:28:42 -08001188 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson6e14e912012-10-02 11:32:24 -07001189 break;
Kirill Batuzov53108fb2011-07-07 16:37:14 +04001190 }
Richard Henderson6e14e912012-10-02 11:32:24 -07001191 goto do_default;
1192
Richard Henderson0e28d002016-11-16 09:23:28 +01001193 CASE_OP_32_64(clz):
1194 CASE_OP_32_64(ctz):
Richard Henderson63490392017-06-20 13:43:15 -07001195 if (arg_is_const(op->args[1])) {
1196 TCGArg v = arg_info(op->args[1])->val;
Richard Henderson0e28d002016-11-16 09:23:28 +01001197 if (v != 0) {
1198 tmp = do_constant_folding(opc, v, 0);
Richard Hendersonacd93702016-12-08 12:28:42 -08001199 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson0e28d002016-11-16 09:23:28 +01001200 } else {
Richard Hendersonacd93702016-12-08 12:28:42 -08001201 tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
Richard Henderson0e28d002016-11-16 09:23:28 +01001202 }
1203 break;
1204 }
1205 goto do_default;
1206
Aurelien Jarno7ef55fc2012-09-21 11:07:29 +02001207 CASE_OP_32_64(deposit):
Richard Henderson63490392017-06-20 13:43:15 -07001208 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
1209 tmp = deposit64(arg_info(op->args[1])->val,
1210 op->args[3], op->args[4],
1211 arg_info(op->args[2])->val);
Richard Hendersonacd93702016-12-08 12:28:42 -08001212 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson6e14e912012-10-02 11:32:24 -07001213 break;
Aurelien Jarno7ef55fc2012-09-21 11:07:29 +02001214 }
Richard Henderson6e14e912012-10-02 11:32:24 -07001215 goto do_default;
1216
Richard Henderson7ec8bab2016-10-14 12:04:32 -05001217 CASE_OP_32_64(extract):
Richard Henderson63490392017-06-20 13:43:15 -07001218 if (arg_is_const(op->args[1])) {
1219 tmp = extract64(arg_info(op->args[1])->val,
Richard Hendersonacd93702016-12-08 12:28:42 -08001220 op->args[2], op->args[3]);
1221 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson7ec8bab2016-10-14 12:04:32 -05001222 break;
1223 }
1224 goto do_default;
1225
1226 CASE_OP_32_64(sextract):
Richard Henderson63490392017-06-20 13:43:15 -07001227 if (arg_is_const(op->args[1])) {
1228 tmp = sextract64(arg_info(op->args[1])->val,
Richard Hendersonacd93702016-12-08 12:28:42 -08001229 op->args[2], op->args[3]);
1230 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson7ec8bab2016-10-14 12:04:32 -05001231 break;
1232 }
1233 goto do_default;
1234
Richard Hendersonfce12962019-02-25 10:29:25 -08001235 CASE_OP_32_64(extract2):
1236 if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
Richard Henderson54795542020-09-06 16:21:32 -07001237 uint64_t v1 = arg_info(op->args[1])->val;
1238 uint64_t v2 = arg_info(op->args[2])->val;
1239 int shr = op->args[3];
Richard Hendersonfce12962019-02-25 10:29:25 -08001240
1241 if (opc == INDEX_op_extract2_i64) {
Richard Henderson54795542020-09-06 16:21:32 -07001242 tmp = (v1 >> shr) | (v2 << (64 - shr));
Richard Hendersonfce12962019-02-25 10:29:25 -08001243 } else {
Richard Henderson54795542020-09-06 16:21:32 -07001244 tmp = (int32_t)(((uint32_t)v1 >> shr) |
1245 ((uint32_t)v2 << (32 - shr)));
Richard Hendersonfce12962019-02-25 10:29:25 -08001246 }
1247 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1248 break;
1249 }
1250 goto do_default;
1251
Aurelien Jarnof8dd19e2012-09-06 16:47:14 +02001252 CASE_OP_32_64(setcond):
Richard Hendersonacd93702016-12-08 12:28:42 -08001253 tmp = do_constant_folding_cond(opc, op->args[1],
1254 op->args[2], op->args[3]);
Aurelien Jarnob336ceb2012-09-18 19:37:00 +02001255 if (tmp != 2) {
Richard Hendersonacd93702016-12-08 12:28:42 -08001256 tcg_opt_gen_movi(s, op, op->args[0], tmp);
Richard Henderson6e14e912012-10-02 11:32:24 -07001257 break;
Aurelien Jarnof8dd19e2012-09-06 16:47:14 +02001258 }
Richard Henderson6e14e912012-10-02 11:32:24 -07001259 goto do_default;
1260
Aurelien Jarnofbeaa262012-09-06 16:47:14 +02001261 CASE_OP_32_64(brcond):
Richard Hendersonacd93702016-12-08 12:28:42 -08001262 tmp = do_constant_folding_cond(opc, op->args[0],
1263 op->args[1], op->args[2]);
Aurelien Jarnob336ceb2012-09-18 19:37:00 +02001264 if (tmp != 2) {
1265 if (tmp) {
Emilio G. Cota34184b02017-07-19 14:32:24 -04001266 bitmap_zero(temps_used.l, nb_temps);
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001267 op->opc = INDEX_op_br;
Richard Hendersonacd93702016-12-08 12:28:42 -08001268 op->args[0] = op->args[3];
Aurelien Jarnofbeaa262012-09-06 16:47:14 +02001269 } else {
Richard Henderson0c627cd2014-03-30 16:51:54 -07001270 tcg_op_remove(s, op);
Aurelien Jarnofbeaa262012-09-06 16:47:14 +02001271 }
Richard Henderson6e14e912012-10-02 11:32:24 -07001272 break;
Aurelien Jarnofbeaa262012-09-06 16:47:14 +02001273 }
Richard Henderson6e14e912012-10-02 11:32:24 -07001274 goto do_default;
1275
Richard Hendersonfa01a202012-09-21 10:13:37 -07001276 CASE_OP_32_64(movcond):
Richard Hendersonacd93702016-12-08 12:28:42 -08001277 tmp = do_constant_folding_cond(opc, op->args[1],
1278 op->args[2], op->args[5]);
Aurelien Jarnob336ceb2012-09-18 19:37:00 +02001279 if (tmp != 2) {
Richard Hendersonacd93702016-12-08 12:28:42 -08001280 tcg_opt_gen_mov(s, op, op->args[0], op->args[4-tmp]);
Richard Henderson6e14e912012-10-02 11:32:24 -07001281 break;
Richard Hendersonfa01a202012-09-21 10:13:37 -07001282 }
Richard Henderson63490392017-06-20 13:43:15 -07001283 if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
Richard Henderson54795542020-09-06 16:21:32 -07001284 uint64_t tv = arg_info(op->args[3])->val;
1285 uint64_t fv = arg_info(op->args[4])->val;
Richard Hendersonacd93702016-12-08 12:28:42 -08001286 TCGCond cond = op->args[5];
Richard Henderson54795542020-09-06 16:21:32 -07001287
Richard Henderson333b21b2016-10-23 20:44:32 -07001288 if (fv == 1 && tv == 0) {
1289 cond = tcg_invert_cond(cond);
1290 } else if (!(tv == 1 && fv == 0)) {
1291 goto do_default;
1292 }
Richard Hendersonacd93702016-12-08 12:28:42 -08001293 op->args[3] = cond;
Richard Henderson333b21b2016-10-23 20:44:32 -07001294 op->opc = opc = (opc == INDEX_op_movcond_i32
1295 ? INDEX_op_setcond_i32
1296 : INDEX_op_setcond_i64);
1297 nb_iargs = 2;
1298 }
Richard Henderson6e14e912012-10-02 11:32:24 -07001299 goto do_default;
1300
Richard Henderson212c3282012-10-02 11:32:28 -07001301 case INDEX_op_add2_i32:
1302 case INDEX_op_sub2_i32:
Richard Henderson63490392017-06-20 13:43:15 -07001303 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])
1304 && arg_is_const(op->args[4]) && arg_is_const(op->args[5])) {
1305 uint32_t al = arg_info(op->args[2])->val;
1306 uint32_t ah = arg_info(op->args[3])->val;
1307 uint32_t bl = arg_info(op->args[4])->val;
1308 uint32_t bh = arg_info(op->args[5])->val;
Richard Henderson212c3282012-10-02 11:32:28 -07001309 uint64_t a = ((uint64_t)ah << 32) | al;
1310 uint64_t b = ((uint64_t)bh << 32) | bl;
1311 TCGArg rl, rh;
Emilio G. Cotaac1043f2018-12-09 14:37:19 -05001312 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
Richard Henderson212c3282012-10-02 11:32:28 -07001313
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001314 if (opc == INDEX_op_add2_i32) {
Richard Henderson212c3282012-10-02 11:32:28 -07001315 a += b;
1316 } else {
1317 a -= b;
1318 }
1319
Richard Hendersonacd93702016-12-08 12:28:42 -08001320 rl = op->args[0];
1321 rh = op->args[1];
1322 tcg_opt_gen_movi(s, op, rl, (int32_t)a);
1323 tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32));
Richard Henderson212c3282012-10-02 11:32:28 -07001324 break;
1325 }
1326 goto do_default;
1327
Richard Henderson14149682012-10-02 11:32:30 -07001328 case INDEX_op_mulu2_i32:
Richard Henderson63490392017-06-20 13:43:15 -07001329 if (arg_is_const(op->args[2]) && arg_is_const(op->args[3])) {
1330 uint32_t a = arg_info(op->args[2])->val;
1331 uint32_t b = arg_info(op->args[3])->val;
Richard Henderson14149682012-10-02 11:32:30 -07001332 uint64_t r = (uint64_t)a * b;
1333 TCGArg rl, rh;
Emilio G. Cotaac1043f2018-12-09 14:37:19 -05001334 TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
Richard Henderson14149682012-10-02 11:32:30 -07001335
Richard Hendersonacd93702016-12-08 12:28:42 -08001336 rl = op->args[0];
1337 rh = op->args[1];
1338 tcg_opt_gen_movi(s, op, rl, (int32_t)r);
1339 tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32));
Richard Henderson14149682012-10-02 11:32:30 -07001340 break;
1341 }
1342 goto do_default;
1343
Richard Hendersonbc1473e2012-10-02 11:32:25 -07001344 case INDEX_op_brcond2_i32:
Richard Hendersonacd93702016-12-08 12:28:42 -08001345 tmp = do_constant_folding_cond2(&op->args[0], &op->args[2],
1346 op->args[4]);
Richard Henderson6c4382f2012-10-02 11:32:27 -07001347 if (tmp != 2) {
1348 if (tmp) {
Richard Hendersona7635512014-04-23 22:18:30 -07001349 do_brcond_true:
Emilio G. Cota34184b02017-07-19 14:32:24 -04001350 bitmap_zero(temps_used.l, nb_temps);
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001351 op->opc = INDEX_op_br;
Richard Hendersonacd93702016-12-08 12:28:42 -08001352 op->args[0] = op->args[5];
Richard Henderson6c4382f2012-10-02 11:32:27 -07001353 } else {
Richard Hendersona7635512014-04-23 22:18:30 -07001354 do_brcond_false:
Richard Henderson0c627cd2014-03-30 16:51:54 -07001355 tcg_op_remove(s, op);
Richard Henderson6c4382f2012-10-02 11:32:27 -07001356 }
Richard Hendersonacd93702016-12-08 12:28:42 -08001357 } else if ((op->args[4] == TCG_COND_LT
1358 || op->args[4] == TCG_COND_GE)
Richard Henderson63490392017-06-20 13:43:15 -07001359 && arg_is_const(op->args[2])
1360 && arg_info(op->args[2])->val == 0
1361 && arg_is_const(op->args[3])
1362 && arg_info(op->args[3])->val == 0) {
Richard Henderson6c4382f2012-10-02 11:32:27 -07001363 /* Simplify LT/GE comparisons vs zero to a single compare
1364 vs the high word of the input. */
Richard Hendersona7635512014-04-23 22:18:30 -07001365 do_brcond_high:
Emilio G. Cota34184b02017-07-19 14:32:24 -04001366 bitmap_zero(temps_used.l, nb_temps);
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001367 op->opc = INDEX_op_brcond_i32;
Richard Hendersonacd93702016-12-08 12:28:42 -08001368 op->args[0] = op->args[1];
1369 op->args[1] = op->args[3];
1370 op->args[2] = op->args[4];
1371 op->args[3] = op->args[5];
1372 } else if (op->args[4] == TCG_COND_EQ) {
Richard Hendersona7635512014-04-23 22:18:30 -07001373 /* Simplify EQ comparisons where one of the pairs
1374 can be simplified. */
1375 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001376 op->args[0], op->args[2],
1377 TCG_COND_EQ);
Richard Hendersona7635512014-04-23 22:18:30 -07001378 if (tmp == 0) {
1379 goto do_brcond_false;
1380 } else if (tmp == 1) {
1381 goto do_brcond_high;
1382 }
1383 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001384 op->args[1], op->args[3],
1385 TCG_COND_EQ);
Richard Hendersona7635512014-04-23 22:18:30 -07001386 if (tmp == 0) {
1387 goto do_brcond_false;
1388 } else if (tmp != 1) {
1389 goto do_default;
1390 }
1391 do_brcond_low:
Emilio G. Cota34184b02017-07-19 14:32:24 -04001392 bitmap_zero(temps_used.l, nb_temps);
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001393 op->opc = INDEX_op_brcond_i32;
Richard Hendersonacd93702016-12-08 12:28:42 -08001394 op->args[1] = op->args[2];
1395 op->args[2] = op->args[4];
1396 op->args[3] = op->args[5];
1397 } else if (op->args[4] == TCG_COND_NE) {
Richard Hendersona7635512014-04-23 22:18:30 -07001398 /* Simplify NE comparisons where one of the pairs
1399 can be simplified. */
1400 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001401 op->args[0], op->args[2],
1402 TCG_COND_NE);
Richard Hendersona7635512014-04-23 22:18:30 -07001403 if (tmp == 0) {
1404 goto do_brcond_high;
1405 } else if (tmp == 1) {
1406 goto do_brcond_true;
1407 }
1408 tmp = do_constant_folding_cond(INDEX_op_brcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001409 op->args[1], op->args[3],
1410 TCG_COND_NE);
Richard Hendersona7635512014-04-23 22:18:30 -07001411 if (tmp == 0) {
1412 goto do_brcond_low;
1413 } else if (tmp == 1) {
1414 goto do_brcond_true;
1415 }
1416 goto do_default;
Richard Henderson6c4382f2012-10-02 11:32:27 -07001417 } else {
1418 goto do_default;
Richard Hendersonbc1473e2012-10-02 11:32:25 -07001419 }
Richard Henderson6c4382f2012-10-02 11:32:27 -07001420 break;
Richard Hendersonbc1473e2012-10-02 11:32:25 -07001421
1422 case INDEX_op_setcond2_i32:
Richard Hendersonacd93702016-12-08 12:28:42 -08001423 tmp = do_constant_folding_cond2(&op->args[1], &op->args[3],
1424 op->args[5]);
Richard Henderson6c4382f2012-10-02 11:32:27 -07001425 if (tmp != 2) {
Richard Hendersona7635512014-04-23 22:18:30 -07001426 do_setcond_const:
Richard Hendersonacd93702016-12-08 12:28:42 -08001427 tcg_opt_gen_movi(s, op, op->args[0], tmp);
1428 } else if ((op->args[5] == TCG_COND_LT
1429 || op->args[5] == TCG_COND_GE)
Richard Henderson63490392017-06-20 13:43:15 -07001430 && arg_is_const(op->args[3])
1431 && arg_info(op->args[3])->val == 0
1432 && arg_is_const(op->args[4])
1433 && arg_info(op->args[4])->val == 0) {
Richard Henderson6c4382f2012-10-02 11:32:27 -07001434 /* Simplify LT/GE comparisons vs zero to a single compare
1435 vs the high word of the input. */
Richard Hendersona7635512014-04-23 22:18:30 -07001436 do_setcond_high:
Richard Hendersonacd93702016-12-08 12:28:42 -08001437 reset_temp(op->args[0]);
Richard Henderson63490392017-06-20 13:43:15 -07001438 arg_info(op->args[0])->mask = 1;
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001439 op->opc = INDEX_op_setcond_i32;
Richard Hendersonacd93702016-12-08 12:28:42 -08001440 op->args[1] = op->args[2];
1441 op->args[2] = op->args[4];
1442 op->args[3] = op->args[5];
1443 } else if (op->args[5] == TCG_COND_EQ) {
Richard Hendersona7635512014-04-23 22:18:30 -07001444 /* Simplify EQ comparisons where one of the pairs
1445 can be simplified. */
1446 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001447 op->args[1], op->args[3],
1448 TCG_COND_EQ);
Richard Hendersona7635512014-04-23 22:18:30 -07001449 if (tmp == 0) {
1450 goto do_setcond_const;
1451 } else if (tmp == 1) {
1452 goto do_setcond_high;
1453 }
1454 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001455 op->args[2], op->args[4],
1456 TCG_COND_EQ);
Richard Hendersona7635512014-04-23 22:18:30 -07001457 if (tmp == 0) {
1458 goto do_setcond_high;
1459 } else if (tmp != 1) {
1460 goto do_default;
1461 }
1462 do_setcond_low:
Richard Hendersonacd93702016-12-08 12:28:42 -08001463 reset_temp(op->args[0]);
Richard Henderson63490392017-06-20 13:43:15 -07001464 arg_info(op->args[0])->mask = 1;
Richard Hendersonc45cb8b2014-09-19 13:49:15 -07001465 op->opc = INDEX_op_setcond_i32;
Richard Hendersonacd93702016-12-08 12:28:42 -08001466 op->args[2] = op->args[3];
1467 op->args[3] = op->args[5];
1468 } else if (op->args[5] == TCG_COND_NE) {
Richard Hendersona7635512014-04-23 22:18:30 -07001469 /* Simplify NE comparisons where one of the pairs
1470 can be simplified. */
1471 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001472 op->args[1], op->args[3],
1473 TCG_COND_NE);
Richard Hendersona7635512014-04-23 22:18:30 -07001474 if (tmp == 0) {
1475 goto do_setcond_high;
1476 } else if (tmp == 1) {
1477 goto do_setcond_const;
1478 }
1479 tmp = do_constant_folding_cond(INDEX_op_setcond_i32,
Richard Hendersonacd93702016-12-08 12:28:42 -08001480 op->args[2], op->args[4],
1481 TCG_COND_NE);
Richard Hendersona7635512014-04-23 22:18:30 -07001482 if (tmp == 0) {
1483 goto do_setcond_low;
1484 } else if (tmp == 1) {
1485 goto do_setcond_const;
1486 }
1487 goto do_default;
Richard Henderson6c4382f2012-10-02 11:32:27 -07001488 } else {
1489 goto do_default;
Richard Hendersonbc1473e2012-10-02 11:32:25 -07001490 }
Richard Henderson6c4382f2012-10-02 11:32:27 -07001491 break;
Richard Hendersonbc1473e2012-10-02 11:32:25 -07001492
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +04001493 case INDEX_op_call:
Richard Hendersonacd93702016-12-08 12:28:42 -08001494 if (!(op->args[nb_oargs + nb_iargs + 1]
Richard Hendersoncf066672014-03-22 20:06:52 -07001495 & (TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_WRITE_GLOBALS))) {
Kirill Batuzov22613af2011-07-07 16:37:13 +04001496 for (i = 0; i < nb_globals; i++) {
Aurelien Jarno1208d7d2015-07-27 12:41:44 +02001497 if (test_bit(i, temps_used.l)) {
Richard Henderson63490392017-06-20 13:43:15 -07001498 reset_ts(&s->temps[i]);
Aurelien Jarno1208d7d2015-07-27 12:41:44 +02001499 }
Kirill Batuzov22613af2011-07-07 16:37:13 +04001500 }
1501 }
Richard Hendersonc56caea2020-11-03 13:20:21 -08001502 goto do_reset_output;
Richard Henderson6e14e912012-10-02 11:32:24 -07001503
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +04001504 default:
Richard Henderson6e14e912012-10-02 11:32:24 -07001505 do_default:
Richard Hendersonc56caea2020-11-03 13:20:21 -08001506 /* Default case: we know nothing about operation (or were unable
1507 to compute the operation result) so no propagation is done.
1508 We trash everything if the operation is the end of a basic
1509 block, otherwise we only trash the output args. "mask" is
1510 the non-zero bits mask for the first output arg. */
1511 if (def->flags & TCG_OPF_BB_END) {
1512 bitmap_zero(temps_used.l, nb_temps);
1513 } else {
1514 do_reset_output:
1515 for (i = 0; i < nb_oargs; i++) {
1516 reset_temp(op->args[i]);
1517 /* Save the corresponding known-zero bits mask for the
1518 first output argument (only one supported so far). */
1519 if (i == 0) {
1520 arg_info(op->args[i])->mask = mask;
1521 }
Aurelien Jarnoa2550662012-09-19 21:40:30 +02001522 }
Kirill Batuzov22613af2011-07-07 16:37:13 +04001523 }
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +04001524 break;
1525 }
Pranith Kumar34f93922016-08-23 09:48:25 -04001526
1527 /* Eliminate duplicate and redundant fence instructions. */
Richard Hendersonacd93702016-12-08 12:28:42 -08001528 if (prev_mb) {
Pranith Kumar34f93922016-08-23 09:48:25 -04001529 switch (opc) {
1530 case INDEX_op_mb:
1531 /* Merge two barriers of the same type into one,
1532 * or a weaker barrier into a stronger one,
1533 * or two weaker barriers into a stronger one.
1534 * mb X; mb Y => mb X|Y
1535 * mb; strl => mb; st
1536 * ldaq; mb => ld; mb
1537 * ldaq; strl => ld; mb; st
1538 * Other combinations are also merged into a strong
1539 * barrier. This is stricter than specified but for
1540 * the purposes of TCG is better than not optimizing.
1541 */
Richard Hendersonacd93702016-12-08 12:28:42 -08001542 prev_mb->args[0] |= op->args[0];
Pranith Kumar34f93922016-08-23 09:48:25 -04001543 tcg_op_remove(s, op);
1544 break;
1545
1546 default:
1547 /* Opcodes that end the block stop the optimization. */
1548 if ((def->flags & TCG_OPF_BB_END) == 0) {
1549 break;
1550 }
1551 /* fallthru */
1552 case INDEX_op_qemu_ld_i32:
1553 case INDEX_op_qemu_ld_i64:
1554 case INDEX_op_qemu_st_i32:
Richard Henderson07ce0b02020-12-09 13:58:39 -06001555 case INDEX_op_qemu_st8_i32:
Pranith Kumar34f93922016-08-23 09:48:25 -04001556 case INDEX_op_qemu_st_i64:
1557 case INDEX_op_call:
1558 /* Opcodes that touch guest memory stop the optimization. */
Richard Hendersonacd93702016-12-08 12:28:42 -08001559 prev_mb = NULL;
Pranith Kumar34f93922016-08-23 09:48:25 -04001560 break;
1561 }
1562 } else if (opc == INDEX_op_mb) {
Richard Hendersonacd93702016-12-08 12:28:42 -08001563 prev_mb = op;
Pranith Kumar34f93922016-08-23 09:48:25 -04001564 }
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +04001565 }
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +04001566}