target-arm: Support save/load for 64 bit CPUs
hack for the moment. this kinda suggests we need to
merge cpsr and pstate better than we do currently.
diff --git a/target-arm/machine.c b/target-arm/machine.c
index b967223..09fb34a 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -130,6 +130,12 @@
CPUARMState *env = &cpu->env;
uint32_t val = qemu_get_be32(f);
+ if (arm_feature(env, ARM_FEATURE_AARCH64)
+ && !(val & PSTATE_nRW)) {
+ pstate_write(env, val);
+ return 0;
+ }
+ env->aarch64 = 0;
/* Avoid mode switch when restoring CPSR */
env->uncached_cpsr = val & CPSR_M;
cpsr_write(env, val, 0xffffffff);
@@ -140,8 +146,16 @@
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
+ uint32_t val;
- qemu_put_be32(f, cpsr_read(env));
+ if (arm_feature(env, ARM_FEATURE_AARCH64)
+ && is_a64(env)) {
+ val = pstate_read(env);
+ } else {
+ val = cpsr_read(env);
+ }
+
+ qemu_put_be32(f, val);
}
static const VMStateInfo vmstate_cpsr = {
@@ -222,13 +236,15 @@
const VMStateDescription vmstate_arm_cpu = {
.name = "cpu",
- .version_id = 17,
- .minimum_version_id = 17,
- .minimum_version_id_old = 17,
+ .version_id = 18,
+ .minimum_version_id = 18,
+ .minimum_version_id_old = 18,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
+ VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
+ VMSTATE_UINT64(env.pc, ARMCPU),
{
.name = "cpsr",
.version_id = 0,