commit ebc9525c953dfbb6c44ab99320b5278e4314dafe
author Christian Lang <lang.chr86@gmail.com> Tue Jul 22 21:23:12 2025 +0200
committer Damien George <damien@micropython.org> Fri Jul 25 11:25:24 2025 +1000
tree 7a6108d7f45839598dae4bea330c183f9cef32e1
parent ab620f40844a837546497252849933ef2f685f4d

rp2/modmachine: Do not use deprecated XOSC_MHZ and XOSC_KHZ.

XOSC_MHZ and XOSC_KHZ may not be defined if we use a custom XIN clock
by defining PLL_SYS_REFDIV etc. calculated by vcocalc.py.

Signed-off-by: Christian Lang <lang.chr86@gmail.com>

ports/rp2/clocks_extra.c

diff --git a/ports/rp2/clocks_extra.c b/ports/rp2/clocks_extra.c
index 73def24..ab3e626 100644
--- a/ports/rp2/clocks_extra.c
+++ b/ports/rp2/clocks_extra.c
@@ -83,8 +83,8 @@
     clock_configure(clk_ref,
         CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
         0,             // No aux mux
-        XOSC_KHZ * KHZ,
-        XOSC_KHZ * KHZ);
+        XOSC_HZ,
+        XOSC_HZ);
 
     /// \tag::configure_clk_sys[]
     // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz

ports/rp2/modmachine.c

diff --git a/ports/rp2/modmachine.c b/ports/rp2/modmachine.c
index 1f1b0e2..e5cf703 100644
--- a/ports/rp2/modmachine.c
+++ b/ports/rp2/modmachine.c
@@ -163,8 +163,6 @@
         }
     }
 
-    const uint32_t xosc_hz = XOSC_MHZ * 1000000;
-
     uint32_t my_interrupts = MICROPY_BEGIN_ATOMIC_SECTION();
     #if MICROPY_PY_NETWORK_CYW43
     if (cyw43_poll_is_pending()) {
@@ -200,18 +198,18 @@
     #endif
 
     // CLK_REF = XOSC
-    clock_configure(clk_ref, CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, 0, xosc_hz, xosc_hz);
+    clock_configure(clk_ref, CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC, 0, XOSC_HZ, XOSC_HZ);
 
     // CLK_SYS = CLK_REF
-    clock_configure(clk_sys, CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF, 0, xosc_hz, xosc_hz);
+    clock_configure(clk_sys, CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF, 0, XOSC_HZ, XOSC_HZ);
 
     // CLK_RTC = XOSC / 256
     #if PICO_RP2040
-    clock_configure(clk_rtc, 0, CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC, xosc_hz, xosc_hz / 256);
+    clock_configure(clk_rtc, 0, CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC, XOSC_HZ, XOSC_HZ / 256);
     #endif
 
     // CLK_PERI = CLK_SYS
-    clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, xosc_hz, xosc_hz);
+    clock_configure(clk_peri, 0, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, XOSC_HZ, XOSC_HZ);
 
     // Disable PLLs.
     pll_deinit(pll_sys);