blob: e441fd8e7c868e41b45789188f0defe2ba2e9310 [file] [log] [blame]
David Brownella603a7f2008-10-15 12:15:39 +02001/*
2 * twl4030.h - header for TWL4030 PM and audio CODEC device
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
Balaji T Kfc7b92f2009-12-13 21:23:33 +010025#ifndef __TWL_H_
26#define __TWL_H_
David Brownella603a7f2008-10-15 12:15:39 +020027
David Brownell9d834062009-08-25 19:24:14 -070028#include <linux/types.h>
29#include <linux/input/matrix_keypad.h>
30
David Brownella603a7f2008-10-15 12:15:39 +020031/*
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
36 *
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
40 */
41
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010042/* Module IDs for similar functionalities found in twl4030/twl6030 */
43enum twl_module_ids {
44 TWL_MODULE_USB,
45 TWL_MODULE_PIH,
46 TWL_MODULE_MAIN_CHARGE,
47 TWL_MODULE_PM_MASTER,
48 TWL_MODULE_PM_RECEIVER,
49
50 TWL_MODULE_RTC,
51 TWL_MODULE_PWM,
52 TWL_MODULE_LED,
53 TWL_MODULE_SECURED_REG,
54
55 TWL_MODULE_LAST,
56};
57
58/* Modules only available in twl4030 series */
Peter Ujfalusida059ec2012-11-13 09:28:48 +010059enum twl4030_module_ids {
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010060 TWL4030_MODULE_AUDIO_VOICE = TWL_MODULE_LAST,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010061 TWL4030_MODULE_GPIO,
62 TWL4030_MODULE_INTBR,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010063 TWL4030_MODULE_TEST,
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010064 TWL4030_MODULE_KEYPAD,
65
Peter Ujfalusida059ec2012-11-13 09:28:48 +010066 TWL4030_MODULE_MADC,
67 TWL4030_MODULE_INTERRUPTS,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010068 TWL4030_MODULE_PRECHARGE,
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010069 TWL4030_MODULE_BACKUP,
Peter Ujfalusida059ec2012-11-13 09:28:48 +010070 TWL4030_MODULE_INT,
Ilkka Koskinen1920a612009-11-10 17:26:15 +020071
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010072 TWL5031_MODULE_ACCESSORY,
73 TWL5031_MODULE_INTERRUPTS,
74
Peter Ujfalusida059ec2012-11-13 09:28:48 +010075 TWL4030_MODULE_LAST,
76};
David Brownella603a7f2008-10-15 12:15:39 +020077
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010078/* Modules only available in twl6030 series */
79enum twl6030_module_ids {
80 TWL6030_MODULE_ID0 = TWL_MODULE_LAST,
81 TWL6030_MODULE_ID1,
82 TWL6030_MODULE_ID2,
83 TWL6030_MODULE_GPADC,
84 TWL6030_MODULE_GASGAUGE,
Balaji T Kfa0d9762010-02-19 12:39:38 +010085
Peter Ujfalusi5d4e9bd2013-01-16 14:53:50 +010086 TWL6030_MODULE_LAST,
87};
88
89/* Until the clients has been converted to use TWL_MODULE_LED */
90#define TWL4030_MODULE_LED TWL_MODULE_LED
Balaji T Kfc7b92f2009-12-13 21:23:33 +010091
92#define GPIO_INTR_OFFSET 0
93#define KEYPAD_INTR_OFFSET 1
94#define BCI_INTR_OFFSET 2
95#define MADC_INTR_OFFSET 3
96#define USB_INTR_OFFSET 4
Graeme Gregory6523b142011-05-12 14:27:56 +010097#define CHARGERFAULT_INTR_OFFSET 5
Balaji T Kfc7b92f2009-12-13 21:23:33 +010098#define BCI_PRES_INTR_OFFSET 9
99#define USB_PRES_INTR_OFFSET 10
100#define RTC_INTR_OFFSET 11
Balaji T Ke8deb282009-12-14 00:25:31 +0100101
102/*
103 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
104 */
105#define PWR_INTR_OFFSET 0
106#define HOTDIE_INTR_OFFSET 12
107#define SMPSLDO_INTR_OFFSET 13
108#define BATDETECT_INTR_OFFSET 14
109#define SIMDETECT_INTR_OFFSET 15
110#define MMCDETECT_INTR_OFFSET 16
111#define GASGAUGE_INTR_OFFSET 17
112#define USBOTG_INTR_OFFSET 4
113#define CHARGER_INTR_OFFSET 2
114#define RSV_INTR_OFFSET 0
115
116/* INT register offsets */
117#define REG_INT_STS_A 0x00
118#define REG_INT_STS_B 0x01
119#define REG_INT_STS_C 0x02
120
121#define REG_INT_MSK_LINE_A 0x03
122#define REG_INT_MSK_LINE_B 0x04
123#define REG_INT_MSK_LINE_C 0x05
124
125#define REG_INT_MSK_STS_A 0x06
126#define REG_INT_MSK_STS_B 0x07
127#define REG_INT_MSK_STS_C 0x08
128
129/* MASK INT REG GROUP A */
130#define TWL6030_PWR_INT_MASK 0x07
131#define TWL6030_RTC_INT_MASK 0x18
132#define TWL6030_HOTDIE_INT_MASK 0x20
133#define TWL6030_SMPSLDOA_INT_MASK 0xC0
134
135/* MASK INT REG GROUP B */
136#define TWL6030_SMPSLDOB_INT_MASK 0x01
137#define TWL6030_BATDETECT_INT_MASK 0x02
138#define TWL6030_SIMDETECT_INT_MASK 0x04
139#define TWL6030_MMCDETECT_INT_MASK 0x08
140#define TWL6030_GPADC_INT_MASK 0x60
141#define TWL6030_GASGAUGE_INT_MASK 0x80
142
143/* MASK INT REG GROUP C */
144#define TWL6030_USBOTG_INT_MASK 0x0F
145#define TWL6030_CHARGER_CTRL_INT_MASK 0x10
146#define TWL6030_CHARGER_FAULT_INT_MASK 0x60
147
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000148#define TWL6030_MMCCTRL 0xEE
149#define VMMC_AUTO_OFF (0x1 << 3)
150#define SW_FC (0x1 << 2)
151#define STS_MMC 0x1
152
153#define TWL6030_CFG_INPUT_PUPD3 0xF2
154#define MMC_PU (0x1 << 3)
155#define MMC_PD (0x1 << 2)
156
Lesly A Mca972d12011-04-14 17:57:53 +0530157#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
158#define TWL_SIL_REV(rev) ((rev) >> 24)
159#define TWL_SIL_5030 0x09002F
160#define TWL5030_REV_1_0 0x00
161#define TWL5030_REV_1_1 0x10
162#define TWL5030_REV_1_2 0x30
Balaji T Ke8deb282009-12-14 00:25:31 +0100163
164#define TWL4030_CLASS_ID 0x4030
165#define TWL6030_CLASS_ID 0x6030
166unsigned int twl_rev(void);
167#define GET_TWL_REV (twl_rev())
168#define TWL_CLASS_IS(class, id) \
169static inline int twl_class_is_ ##class(void) \
170{ \
171 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
172}
173
174TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
175TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
176
David Brownella603a7f2008-10-15 12:15:39 +0200177/*
178 * Read and write single 8-bit registers
179 */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100180int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
181int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
David Brownella603a7f2008-10-15 12:15:39 +0200182
183/*
184 * Read and write several 8-bit registers at once.
David Brownella603a7f2008-10-15 12:15:39 +0200185 */
Balaji T Kfc7b92f2009-12-13 21:23:33 +0100186int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
187int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
David Brownella603a7f2008-10-15 12:15:39 +0200188
Lesly A Mca972d12011-04-14 17:57:53 +0530189int twl_get_type(void);
190int twl_get_version(void);
Peter Ujfalusi2275c542012-09-10 13:46:22 +0300191int twl_get_hfclk_rate(void);
Lesly A Mca972d12011-04-14 17:57:53 +0530192
Balaji T Ke8deb282009-12-14 00:25:31 +0100193int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
194int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
195
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000196/* Card detect Configuration for MMC1 Controller on OMAP4 */
197#ifdef CONFIG_TWL4030_CORE
198int twl6030_mmc_card_detect_config(void);
199#else
200static inline int twl6030_mmc_card_detect_config(void)
201{
202 pr_debug("twl6030_mmc_card_detect_config not supported\n");
203 return 0;
204}
205#endif
206
207/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */
208#ifdef CONFIG_TWL4030_CORE
209int twl6030_mmc_card_detect(struct device *dev, int slot);
210#else
211static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
212{
213 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
214 return -EIO;
215}
216#endif
David Brownella603a7f2008-10-15 12:15:39 +0200217/*----------------------------------------------------------------------*/
218
219/*
220 * NOTE: at up to 1024 registers, this is a big chip.
221 *
222 * Avoid putting register declarations in this file, instead of into
223 * a driver-private file, unless some of the registers in a block
224 * need to be shared with other drivers. One example is blocks that
225 * have Secondary IRQ Handler (SIH) registers.
226 */
227
228#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
229#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
230#define TWL4030_SIH_CTRL_COR_MASK BIT(2)
231
232/*----------------------------------------------------------------------*/
233
234/*
235 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
236 */
237
238#define REG_GPIODATAIN1 0x0
239#define REG_GPIODATAIN2 0x1
240#define REG_GPIODATAIN3 0x2
241#define REG_GPIODATADIR1 0x3
242#define REG_GPIODATADIR2 0x4
243#define REG_GPIODATADIR3 0x5
244#define REG_GPIODATAOUT1 0x6
245#define REG_GPIODATAOUT2 0x7
246#define REG_GPIODATAOUT3 0x8
247#define REG_CLEARGPIODATAOUT1 0x9
248#define REG_CLEARGPIODATAOUT2 0xA
249#define REG_CLEARGPIODATAOUT3 0xB
250#define REG_SETGPIODATAOUT1 0xC
251#define REG_SETGPIODATAOUT2 0xD
252#define REG_SETGPIODATAOUT3 0xE
253#define REG_GPIO_DEBEN1 0xF
254#define REG_GPIO_DEBEN2 0x10
255#define REG_GPIO_DEBEN3 0x11
256#define REG_GPIO_CTRL 0x12
257#define REG_GPIOPUPDCTR1 0x13
258#define REG_GPIOPUPDCTR2 0x14
259#define REG_GPIOPUPDCTR3 0x15
260#define REG_GPIOPUPDCTR4 0x16
261#define REG_GPIOPUPDCTR5 0x17
262#define REG_GPIO_ISR1A 0x19
263#define REG_GPIO_ISR2A 0x1A
264#define REG_GPIO_ISR3A 0x1B
265#define REG_GPIO_IMR1A 0x1C
266#define REG_GPIO_IMR2A 0x1D
267#define REG_GPIO_IMR3A 0x1E
268#define REG_GPIO_ISR1B 0x1F
269#define REG_GPIO_ISR2B 0x20
270#define REG_GPIO_ISR3B 0x21
271#define REG_GPIO_IMR1B 0x22
272#define REG_GPIO_IMR2B 0x23
273#define REG_GPIO_IMR3B 0x24
274#define REG_GPIO_EDR1 0x28
275#define REG_GPIO_EDR2 0x29
276#define REG_GPIO_EDR3 0x2A
277#define REG_GPIO_EDR4 0x2B
278#define REG_GPIO_EDR5 0x2C
279#define REG_GPIO_SIH_CTRL 0x2D
280
281/* Up to 18 signals are available as GPIOs, when their
282 * pins are not assigned to another use (such as ULPI/USB).
283 */
284#define TWL4030_GPIO_MAX 18
285
286/*----------------------------------------------------------------------*/
287
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600288/*Interface Bit Register (INTBR) offsets
289 *(Use TWL_4030_MODULE_INTBR)
290 */
291
Lesly A Mca972d12011-04-14 17:57:53 +0530292#define REG_IDCODE_7_0 0x00
293#define REG_IDCODE_15_8 0x01
294#define REG_IDCODE_16_23 0x02
295#define REG_IDCODE_31_24 0x03
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600296#define REG_GPPUPDCTR1 0x0F
Lesly A Mca972d12011-04-14 17:57:53 +0530297#define REG_UNLOCK_TEST_REG 0x12
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600298
299/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
300
301#define I2C_SCL_CTRL_PU BIT(0)
302#define I2C_SDA_CTRL_PU BIT(2)
303#define SR_I2C_SCL_CTRL_PU BIT(4)
304#define SR_I2C_SDA_CTRL_PU BIT(6)
305
Lesly A Mca972d12011-04-14 17:57:53 +0530306#define TWL_EEPROM_R_UNLOCK 0x49
307
Moiz Sonasatha29aaf52010-02-16 18:57:21 -0600308/*----------------------------------------------------------------------*/
309
David Brownella603a7f2008-10-15 12:15:39 +0200310/*
311 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
312 * ... SIH/interrupt only
313 */
314
315#define TWL4030_KEYPAD_KEYP_ISR1 0x11
316#define TWL4030_KEYPAD_KEYP_IMR1 0x12
317#define TWL4030_KEYPAD_KEYP_ISR2 0x13
318#define TWL4030_KEYPAD_KEYP_IMR2 0x14
319#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
320#define TWL4030_KEYPAD_KEYP_EDR 0x16
321#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
322
323/*----------------------------------------------------------------------*/
324
325/*
326 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
327 * ... SIH/interrupt only
328 */
329
330#define TWL4030_MADC_ISR1 0x61
331#define TWL4030_MADC_IMR1 0x62
332#define TWL4030_MADC_ISR2 0x63
333#define TWL4030_MADC_IMR2 0x64
334#define TWL4030_MADC_SIR 0x65 /* test register */
335#define TWL4030_MADC_EDR 0x66
336#define TWL4030_MADC_SIH_CTRL 0x67
337
338/*----------------------------------------------------------------------*/
339
340/*
341 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
342 */
343
344#define TWL4030_INTERRUPTS_BCIISR1A 0x0
345#define TWL4030_INTERRUPTS_BCIISR2A 0x1
346#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
347#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
348#define TWL4030_INTERRUPTS_BCIISR1B 0x4
349#define TWL4030_INTERRUPTS_BCIISR2B 0x5
350#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
351#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
352#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
353#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
354#define TWL4030_INTERRUPTS_BCIEDR1 0xa
355#define TWL4030_INTERRUPTS_BCIEDR2 0xb
356#define TWL4030_INTERRUPTS_BCIEDR3 0xc
357#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
358
359/*----------------------------------------------------------------------*/
360
361/*
362 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
363 */
364
365#define TWL4030_INT_PWR_ISR1 0x0
366#define TWL4030_INT_PWR_IMR1 0x1
367#define TWL4030_INT_PWR_ISR2 0x2
368#define TWL4030_INT_PWR_IMR2 0x3
369#define TWL4030_INT_PWR_SIR 0x4 /* test register */
370#define TWL4030_INT_PWR_EDR1 0x5
371#define TWL4030_INT_PWR_EDR2 0x6
372#define TWL4030_INT_PWR_SIH_CTRL 0x7
373
374/*----------------------------------------------------------------------*/
375
Ilkka Koskinen1920a612009-11-10 17:26:15 +0200376/*
377 * Accessory Interrupts
378 */
379#define TWL5031_ACIIMR_LSB 0x05
380#define TWL5031_ACIIMR_MSB 0x06
381#define TWL5031_ACIIDR_LSB 0x07
382#define TWL5031_ACIIDR_MSB 0x08
383#define TWL5031_ACCISR1 0x0F
384#define TWL5031_ACCIMR1 0x10
385#define TWL5031_ACCISR2 0x11
386#define TWL5031_ACCIMR2 0x12
387#define TWL5031_ACCSIR 0x13
388#define TWL5031_ACCEDR1 0x14
389#define TWL5031_ACCSIHCTRL 0x15
390
391/*----------------------------------------------------------------------*/
392
393/*
394 * Battery Charger Controller
395 */
396
397#define TWL5031_INTERRUPTS_BCIISR1 0x0
398#define TWL5031_INTERRUPTS_BCIIMR1 0x1
399#define TWL5031_INTERRUPTS_BCIISR2 0x2
400#define TWL5031_INTERRUPTS_BCIIMR2 0x3
401#define TWL5031_INTERRUPTS_BCISIR 0x4
402#define TWL5031_INTERRUPTS_BCIEDR1 0x5
403#define TWL5031_INTERRUPTS_BCIEDR2 0x6
404#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
405
406/*----------------------------------------------------------------------*/
407
Felipe Balbi89712052010-09-10 17:10:21 +0200408/*
409 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
410 */
411
412#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
413#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
414#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
415#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
416#define TWL4030_PM_MASTER_STS_BOOT 0x04
417#define TWL4030_PM_MASTER_CFG_BOOT 0x05
418#define TWL4030_PM_MASTER_SHUNDAN 0x06
419#define TWL4030_PM_MASTER_BOOT_BCI 0x07
420#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
421#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
422#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
423#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
424#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
425#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
426#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
427#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
428#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
429#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
430#define TWL4030_PM_MASTER_STS_P123_STATE 0x13
431#define TWL4030_PM_MASTER_PB_CFG 0x14
432#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
433#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
434#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
435#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
436#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
437#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
438#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
439#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
440#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
441#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
442#define TWL4030_PM_MASTER_MEMORY_DATA 0x24
443
444#define TWL4030_PM_MASTER_KEY_CFG1 0xc0
445#define TWL4030_PM_MASTER_KEY_CFG2 0x0c
446
447#define TWL4030_PM_MASTER_KEY_TST1 0xe0
448#define TWL4030_PM_MASTER_KEY_TST2 0x0e
449
450#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
451
452/*----------------------------------------------------------------------*/
453
David Brownellfa16a5c2009-02-08 10:37:06 -0800454/* Power bus message definitions */
455
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200456/* The TWL4030/5030 splits its power-management resources (the various
457 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
458 * P3. These groups can then be configured to transition between sleep, wait-on
459 * and active states by sending messages to the power bus. See Section 5.4.2
460 * Power Resources of TWL4030 TRM
461 */
David Brownellfa16a5c2009-02-08 10:37:06 -0800462
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200463/* Processor groups */
464#define DEV_GRP_NULL 0x0
465#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
466#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
467#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
468
469/* Resource groups */
470#define RES_GRP_RES 0x0 /* Reserved */
471#define RES_GRP_PP 0x1 /* Power providers */
472#define RES_GRP_RC 0x2 /* Reset and control */
David Brownellfa16a5c2009-02-08 10:37:06 -0800473#define RES_GRP_PP_RC 0x3
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200474#define RES_GRP_PR 0x4 /* Power references */
David Brownellfa16a5c2009-02-08 10:37:06 -0800475#define RES_GRP_PP_PR 0x5
476#define RES_GRP_RC_PR 0x6
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200477#define RES_GRP_ALL 0x7 /* All resource groups */
David Brownellfa16a5c2009-02-08 10:37:06 -0800478
479#define RES_TYPE2_R0 0x0
480
481#define RES_TYPE_ALL 0x7
482
Amit Kucheriab4ead612009-10-19 15:11:00 +0300483/* Resource states */
David Brownellfa16a5c2009-02-08 10:37:06 -0800484#define RES_STATE_WRST 0xF
485#define RES_STATE_ACTIVE 0xE
486#define RES_STATE_SLEEP 0x8
487#define RES_STATE_OFF 0x0
488
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200489/* Power resources */
490
491/* Power providers */
492#define RES_VAUX1 1
493#define RES_VAUX2 2
494#define RES_VAUX3 3
495#define RES_VAUX4 4
496#define RES_VMMC1 5
497#define RES_VMMC2 6
498#define RES_VPLL1 7
499#define RES_VPLL2 8
500#define RES_VSIM 9
501#define RES_VDAC 10
502#define RES_VINTANA1 11
503#define RES_VINTANA2 12
504#define RES_VINTDIG 13
505#define RES_VIO 14
506#define RES_VDD1 15
507#define RES_VDD2 16
508#define RES_VUSB_1V5 17
509#define RES_VUSB_1V8 18
510#define RES_VUSB_3V1 19
511#define RES_VUSBCP 20
512#define RES_REGEN 21
513/* Reset and control */
514#define RES_NRES_PWRON 22
515#define RES_CLKEN 23
516#define RES_SYSEN 24
517#define RES_HFCLKOUT 25
518#define RES_32KCLKOUT 26
519#define RES_RESET 27
520/* Power Reference */
Lesly A Md7ac8292011-04-14 17:57:51 +0530521#define RES_MAIN_REF 28
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200522
523#define TOTAL_RESOURCES 28
David Brownellfa16a5c2009-02-08 10:37:06 -0800524/*
525 * Power Bus Message Format ... these can be sent individually by Linux,
526 * but are usually part of downloaded scripts that are run when various
527 * power events are triggered.
528 *
529 * Broadcast Message (16 Bits):
530 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
531 * RES_STATE[3:0]
532 *
533 * Singular Message (16 Bits):
534 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
535 */
536
537#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
538 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
539 | (type) << 4 | (state))
540
541#define MSG_SINGULAR(devgrp, id, state) \
542 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
543
Rajendra Nayak441a4502009-12-13 22:19:23 +0100544#define MSG_BROADCAST_ALL(devgrp, state) \
545 ((devgrp) << 5 | (state))
546
547#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
548#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
549#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
David Brownellfa16a5c2009-02-08 10:37:06 -0800550/*----------------------------------------------------------------------*/
551
Ilkka Koskinen38a68492009-10-22 14:14:09 +0300552struct twl4030_clock_init_data {
553 bool ck32k_lowpwr_enable;
554};
555
David Brownella603a7f2008-10-15 12:15:39 +0200556struct twl4030_bci_platform_data {
557 int *battery_tmp_tbl;
558 unsigned int tblsize;
NeilBrown210d4bc2012-05-09 07:40:40 +1000559 int bb_uvolt; /* voltage to charge backup battery */
560 int bb_uamp; /* current for backup battery charging */
David Brownella603a7f2008-10-15 12:15:39 +0200561};
562
563/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
564struct twl4030_gpio_platform_data {
David Brownella30d46c2008-10-20 23:46:28 +0200565 /* package the two LED signals as output-only GPIOs? */
566 bool use_leds;
567
568 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
569 u8 mmc_cd;
570
David Brownellcabb3fc2009-01-06 14:42:26 -0800571 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
572 u32 debounce;
573
David Brownella603a7f2008-10-15 12:15:39 +0200574 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
575 * should be enabled. Else, if that bit is set in "pulldowns",
576 * that pulldown is enabled. Don't waste power by letting any
577 * digital inputs float...
578 */
579 u32 pullups;
580 u32 pulldowns;
581
582 int (*setup)(struct device *dev,
583 unsigned gpio, unsigned ngpio);
584 int (*teardown)(struct device *dev,
585 unsigned gpio, unsigned ngpio);
586};
587
588struct twl4030_madc_platform_data {
589 int irq_line;
590};
591
Thomas Weberf7223772010-03-23 19:50:16 +0100592/* Boards have unique mappings of {row, col} --> keycode.
Amit Kucheriaacf442d2009-10-05 21:43:44 -0700593 * Column and row are 8 bits each, but range only from 0..7.
David Brownell9d834062009-08-25 19:24:14 -0700594 * a PERSISTENT_KEY is "always on" and never reported.
595 */
Amit Kucheriaacf442d2009-10-05 21:43:44 -0700596#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
David Brownell9d834062009-08-25 19:24:14 -0700597
David Brownella603a7f2008-10-15 12:15:39 +0200598struct twl4030_keypad_data {
David Brownell9d834062009-08-25 19:24:14 -0700599 const struct matrix_keymap_data *keymap_data;
600 unsigned rows;
601 unsigned cols;
602 bool rep;
David Brownella603a7f2008-10-15 12:15:39 +0200603};
604
605enum twl4030_usb_mode {
606 T2_USB_MODE_ULPI = 1,
607 T2_USB_MODE_CEA2011_3PIN = 2,
608};
609
610struct twl4030_usb_data {
611 enum twl4030_usb_mode usb_mode;
Graeme Gregory521d8ec2011-05-12 14:27:55 +0100612 unsigned long features;
Hema HKe70357e2010-12-10 18:09:52 +0530613
614 int (*phy_init)(struct device *dev);
615 int (*phy_exit)(struct device *dev);
616 /* Power on/off the PHY */
617 int (*phy_power)(struct device *dev, int iD, int on);
618 /* enable/disable phy clocks */
619 int (*phy_set_clock)(struct device *dev, int on);
Hema HKd8692742011-02-17 12:06:06 +0530620 /* suspend/resume of phy */
621 int (*phy_suspend)(struct device *dev, int suspend);
David Brownella603a7f2008-10-15 12:15:39 +0200622};
623
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200624struct twl4030_ins {
625 u16 pmb_message;
626 u8 delay;
627};
628
629struct twl4030_script {
630 struct twl4030_ins *script;
631 unsigned size;
632 u8 flags;
633#define TWL4030_WRST_SCRIPT (1<<0)
634#define TWL4030_WAKEUP12_SCRIPT (1<<1)
635#define TWL4030_WAKEUP3_SCRIPT (1<<2)
636#define TWL4030_SLEEP_SCRIPT (1<<3)
637};
638
639struct twl4030_resconfig {
640 u8 resource;
641 u8 devgroup; /* Processor group that Power resource belongs to */
642 u8 type; /* Power resource addressed, 6 / broadcast message */
643 u8 type2; /* Power resource addressed, 3 / broadcast message */
Amit Kucheriab4ead612009-10-19 15:11:00 +0300644 u8 remap_off; /* off state remapping */
645 u8 remap_sleep; /* sleep state remapping */
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200646};
647
648struct twl4030_power_data {
649 struct twl4030_script **scripts;
650 unsigned num;
651 struct twl4030_resconfig *resource_config;
Aaro Koskinen56baa662009-10-19 21:24:02 +0200652#define TWL4030_RESCONFIG_UNDEF ((u8)-1)
Igor Grinberg26cc3ab2011-11-13 11:49:50 +0200653 bool use_poweroff; /* Board is wired for TWL poweroff */
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200654};
655
656extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
Mike Turquette11a441c2010-02-22 11:16:30 -0600657extern int twl4030_remove_script(u8 flags);
Igor Grinberg26cc3ab2011-11-13 11:49:50 +0200658extern void twl4030_power_off(void);
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200659
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300660struct twl4030_codec_data {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000661 unsigned int digimic_delay; /* in ms */
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300662 unsigned int ramp_delay_value;
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000663 unsigned int offset_cncl_path;
664 unsigned int check_defaults:1;
665 unsigned int reset_registers:1;
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300666 unsigned int hs_extmute:1;
Peter Ujfalusi281ecd12012-09-10 13:46:27 +0300667 int hs_extmute_gpio;
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300668};
669
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300670struct twl4030_vibra_data {
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300671 unsigned int coexist;
672};
673
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300674struct twl4030_audio_data {
Peter Ujfalusicfd53242009-11-04 09:58:17 +0200675 unsigned int audio_mclk;
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300676 struct twl4030_codec_data *codec;
677 struct twl4030_vibra_data *vibra;
Misael Lopez Cruzd62abe52010-02-23 18:10:19 -0600678
Olaya, Margarita6a1c7b72010-03-17 17:42:29 -0500679 /* twl6040 */
680 int audpwron_gpio; /* audio power-on gpio */
681 int naudint_irq; /* audio interrupt */
Misael Lopez Cruzf19b2822011-04-27 02:14:07 -0500682 unsigned int irq_base;
Peter Ujfalusi0b83dde2009-10-22 13:26:45 +0300683};
684
David Brownella603a7f2008-10-15 12:15:39 +0200685struct twl4030_platform_data {
Ilkka Koskinen38a68492009-10-22 14:14:09 +0300686 struct twl4030_clock_init_data *clock;
David Brownella603a7f2008-10-15 12:15:39 +0200687 struct twl4030_bci_platform_data *bci;
688 struct twl4030_gpio_platform_data *gpio;
689 struct twl4030_madc_platform_data *madc;
690 struct twl4030_keypad_data *keypad;
691 struct twl4030_usb_data *usb;
Amit Kucheriaebf0bd32009-08-31 18:32:18 +0200692 struct twl4030_power_data *power;
Peter Ujfalusi4ae6df52011-05-31 15:21:13 +0300693 struct twl4030_audio_data *audio;
David Brownella603a7f2008-10-15 12:15:39 +0200694
Rajendra Nayak9da66532009-12-13 22:29:47 +0100695 /* Common LDO regulators for TWL4030/TWL6030 */
David Brownelldad759f2008-12-01 00:43:58 +0100696 struct regulator_init_data *vdac;
Rajendra Nayak9da66532009-12-13 22:29:47 +0100697 struct regulator_init_data *vaux1;
698 struct regulator_init_data *vaux2;
699 struct regulator_init_data *vaux3;
Tero Kristo34a38442012-02-28 15:09:10 +0530700 struct regulator_init_data *vdd1;
701 struct regulator_init_data *vdd2;
702 struct regulator_init_data *vdd3;
Rajendra Nayak9da66532009-12-13 22:29:47 +0100703 /* TWL4030 LDO regulators */
David Brownelldad759f2008-12-01 00:43:58 +0100704 struct regulator_init_data *vpll1;
705 struct regulator_init_data *vpll2;
706 struct regulator_init_data *vmmc1;
707 struct regulator_init_data *vmmc2;
708 struct regulator_init_data *vsim;
David Brownelldad759f2008-12-01 00:43:58 +0100709 struct regulator_init_data *vaux4;
Juha Keski-Saariab4abe052009-12-11 11:12:15 +0100710 struct regulator_init_data *vio;
Juha Keski-Saariab4abe052009-12-11 11:12:15 +0100711 struct regulator_init_data *vintana1;
712 struct regulator_init_data *vintana2;
713 struct regulator_init_data *vintdig;
Rajendra Nayak9da66532009-12-13 22:29:47 +0100714 /* TWL6030 LDO regulators */
715 struct regulator_init_data *vmmc;
716 struct regulator_init_data *vpp;
717 struct regulator_init_data *vusim;
718 struct regulator_init_data *vana;
719 struct regulator_init_data *vcxio;
720 struct regulator_init_data *vusb;
Balaji T K8e6de4a2011-02-10 18:44:50 +0530721 struct regulator_init_data *clk32kg;
Peter Ujfalusi46eda3e2012-02-28 15:09:13 +0530722 struct regulator_init_data *v1v8;
723 struct regulator_init_data *v2v1;
Graeme Gregory521d8ec2011-05-12 14:27:55 +0100724 /* TWL6025 LDO regulators */
725 struct regulator_init_data *ldo1;
726 struct regulator_init_data *ldo2;
727 struct regulator_init_data *ldo3;
728 struct regulator_init_data *ldo4;
729 struct regulator_init_data *ldo5;
730 struct regulator_init_data *ldo6;
731 struct regulator_init_data *ldo7;
732 struct regulator_init_data *ldoln;
733 struct regulator_init_data *ldousb;
734 /* TWL6025 DCDC regulators */
735 struct regulator_init_data *smps3;
736 struct regulator_init_data *smps4;
737 struct regulator_init_data *vio6025;
David Brownella603a7f2008-10-15 12:15:39 +0200738};
739
Tero Kristo63bfff42012-02-16 12:27:52 +0200740struct twl_regulator_driver_data {
741 int (*set_voltage)(void *data, int target_uV);
742 int (*get_voltage)(void *data);
743 void *data;
744 unsigned long features;
745};
NeilBrownc30540d2012-05-09 05:43:59 +1000746/* chip-specific feature flags, for twl_regulator_driver_data.features */
747#define TWL4030_VAUX2 BIT(0) /* pre-5030 voltage ranges */
748#define TPS_SUBSET BIT(1) /* tps659[23]0 have fewer LDOs */
749#define TWL5031 BIT(2) /* twl5031 has different registers */
750#define TWL6030_CLASS BIT(3) /* TWL6030 class */
751#define TWL6025_SUBCLASS BIT(4) /* TWL6025 has changed registers */
NeilBrown411a2df2012-05-09 05:44:00 +1000752#define TWL4030_ALLOW_UNSUPPORTED BIT(5) /* Some voltages are possible
753 * but not officially supported.
754 * This flag is necessary to
755 * enable them.
756 */
Tero Kristo63bfff42012-02-16 12:27:52 +0200757
David Brownella603a7f2008-10-15 12:15:39 +0200758/*----------------------------------------------------------------------*/
759
Benoit Coussonf01b1f92012-02-29 22:38:06 +0100760int twl4030_sih_setup(struct device *dev, int module, int irq_base);
David Brownella30d46c2008-10-20 23:46:28 +0200761
David Brownella603a7f2008-10-15 12:15:39 +0200762/* Offsets to Power Registers */
763#define TWL4030_VDAC_DEV_GRP 0x3B
764#define TWL4030_VDAC_DEDICATED 0x3E
765#define TWL4030_VAUX1_DEV_GRP 0x17
766#define TWL4030_VAUX1_DEDICATED 0x1A
767#define TWL4030_VAUX2_DEV_GRP 0x1B
768#define TWL4030_VAUX2_DEDICATED 0x1E
769#define TWL4030_VAUX3_DEV_GRP 0x1F
770#define TWL4030_VAUX3_DEDICATED 0x22
771
Christoph Eggerf7ea2dc2010-01-15 15:33:46 +0100772static inline int twl4030charger_usb_en(int enable) { return 0; }
David Brownella603a7f2008-10-15 12:15:39 +0200773
David Brownelldad759f2008-12-01 00:43:58 +0100774/*----------------------------------------------------------------------*/
775
776/* Linux-specific regulator identifiers ... for now, we only support
777 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
778 * need to tie into hardware based voltage scaling (cpufreq etc), while
779 * VIO is generally fixed.
780 */
781
Rajendra Nayak441a4502009-12-13 22:19:23 +0100782/* TWL4030 SMPS/LDO's */
David Brownelldad759f2008-12-01 00:43:58 +0100783/* EXTERNAL dc-to-dc buck converters */
784#define TWL4030_REG_VDD1 0
785#define TWL4030_REG_VDD2 1
786#define TWL4030_REG_VIO 2
787
788/* EXTERNAL LDOs */
789#define TWL4030_REG_VDAC 3
790#define TWL4030_REG_VPLL1 4
791#define TWL4030_REG_VPLL2 5 /* not on all chips */
792#define TWL4030_REG_VMMC1 6
793#define TWL4030_REG_VMMC2 7 /* not on all chips */
794#define TWL4030_REG_VSIM 8 /* not on all chips */
795#define TWL4030_REG_VAUX1 9 /* not on all chips */
796#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
797#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
798#define TWL4030_REG_VAUX3 12 /* not on all chips */
799#define TWL4030_REG_VAUX4 13 /* not on all chips */
800
801/* INTERNAL LDOs */
802#define TWL4030_REG_VINTANA1 14
803#define TWL4030_REG_VINTANA2 15
804#define TWL4030_REG_VINTDIG 16
805#define TWL4030_REG_VUSB1V5 17
806#define TWL4030_REG_VUSB1V8 18
807#define TWL4030_REG_VUSB3V1 19
David Brownelldad759f2008-12-01 00:43:58 +0100808
Rajendra Nayak441a4502009-12-13 22:19:23 +0100809/* TWL6030 SMPS/LDO's */
Thomas Weberf7223772010-03-23 19:50:16 +0100810/* EXTERNAL dc-to-dc buck convertor controllable via SR */
Rajendra Nayak441a4502009-12-13 22:19:23 +0100811#define TWL6030_REG_VDD1 30
812#define TWL6030_REG_VDD2 31
813#define TWL6030_REG_VDD3 32
814
815/* Non SR compliant dc-to-dc buck convertors */
Thomas Weberf7223772010-03-23 19:50:16 +0100816#define TWL6030_REG_VMEM 33
Rajendra Nayak441a4502009-12-13 22:19:23 +0100817#define TWL6030_REG_V2V1 34
Thomas Weberf7223772010-03-23 19:50:16 +0100818#define TWL6030_REG_V1V29 35
Rajendra Nayak441a4502009-12-13 22:19:23 +0100819#define TWL6030_REG_V1V8 36
820
821/* EXTERNAL LDOs */
822#define TWL6030_REG_VAUX1_6030 37
823#define TWL6030_REG_VAUX2_6030 38
824#define TWL6030_REG_VAUX3_6030 39
825#define TWL6030_REG_VMMC 40
826#define TWL6030_REG_VPP 41
827#define TWL6030_REG_VUSIM 42
828#define TWL6030_REG_VANA 43
829#define TWL6030_REG_VCXIO 44
830#define TWL6030_REG_VDAC 45
831#define TWL6030_REG_VUSB 46
832
833/* INTERNAL LDOs */
834#define TWL6030_REG_VRTC 47
Balaji T K8e6de4a2011-02-10 18:44:50 +0530835#define TWL6030_REG_CLK32KG 48
Rajendra Nayak441a4502009-12-13 22:19:23 +0100836
Graeme Gregory521d8ec2011-05-12 14:27:55 +0100837/* LDOs on 6025 have different names */
838#define TWL6025_REG_LDO2 49
839#define TWL6025_REG_LDO4 50
840#define TWL6025_REG_LDO3 51
841#define TWL6025_REG_LDO5 52
842#define TWL6025_REG_LDO1 53
843#define TWL6025_REG_LDO7 54
844#define TWL6025_REG_LDO6 55
845#define TWL6025_REG_LDOLN 56
846#define TWL6025_REG_LDOUSB 57
847
848/* 6025 DCDC supplies */
849#define TWL6025_REG_SMPS3 58
850#define TWL6025_REG_SMPS4 59
851#define TWL6025_REG_VIO 60
852
853
David Brownella603a7f2008-10-15 12:15:39 +0200854#endif /* End of __TWL4030_H */