Beniamino Galvani | 101353c | 2014-06-21 16:22:06 +0200 | [diff] [blame] | 1 | /* |
| 2 | * PWM driver for Rockchip SoCs |
| 3 | * |
| 4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * version 2 as published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/clk.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/pwm.h> |
| 17 | #include <linux/time.h> |
| 18 | |
| 19 | #define PWM_CNTR 0x00 /* Counter register */ |
| 20 | #define PWM_HRC 0x04 /* High reference register */ |
| 21 | #define PWM_LRC 0x08 /* Low reference register */ |
| 22 | #define PWM_CTRL 0x0c /* Control register */ |
| 23 | #define PWM_CTRL_TIMER_EN (1 << 0) |
| 24 | #define PWM_CTRL_OUTPUT_EN (1 << 3) |
| 25 | |
| 26 | #define PRESCALER 2 |
| 27 | |
| 28 | struct rockchip_pwm_chip { |
| 29 | struct pwm_chip chip; |
| 30 | struct clk *clk; |
| 31 | void __iomem *base; |
| 32 | }; |
| 33 | |
| 34 | static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) |
| 35 | { |
| 36 | return container_of(c, struct rockchip_pwm_chip, chip); |
| 37 | } |
| 38 | |
| 39 | static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 40 | int duty_ns, int period_ns) |
| 41 | { |
| 42 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
| 43 | unsigned long period, duty; |
| 44 | u64 clk_rate, div; |
| 45 | int ret; |
| 46 | |
| 47 | clk_rate = clk_get_rate(pc->clk); |
| 48 | |
| 49 | /* |
| 50 | * Since period and duty cycle registers have a width of 32 |
| 51 | * bits, every possible input period can be obtained using the |
| 52 | * default prescaler value for all practical clock rate values. |
| 53 | */ |
| 54 | div = clk_rate * period_ns; |
| 55 | do_div(div, PRESCALER * NSEC_PER_SEC); |
| 56 | period = div; |
| 57 | |
| 58 | div = clk_rate * duty_ns; |
| 59 | do_div(div, PRESCALER * NSEC_PER_SEC); |
| 60 | duty = div; |
| 61 | |
| 62 | ret = clk_enable(pc->clk); |
| 63 | if (ret) |
| 64 | return ret; |
| 65 | |
| 66 | writel(period, pc->base + PWM_LRC); |
| 67 | writel(duty, pc->base + PWM_HRC); |
| 68 | writel(0, pc->base + PWM_CNTR); |
| 69 | |
| 70 | clk_disable(pc->clk); |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 76 | { |
| 77 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
| 78 | int ret; |
| 79 | u32 val; |
| 80 | |
| 81 | ret = clk_enable(pc->clk); |
| 82 | if (ret) |
| 83 | return ret; |
| 84 | |
| 85 | val = readl_relaxed(pc->base + PWM_CTRL); |
| 86 | val |= PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; |
| 87 | writel_relaxed(val, pc->base + PWM_CTRL); |
| 88 | |
| 89 | return 0; |
| 90 | } |
| 91 | |
| 92 | static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 93 | { |
| 94 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
| 95 | u32 val; |
| 96 | |
| 97 | val = readl_relaxed(pc->base + PWM_CTRL); |
| 98 | val &= ~(PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN); |
| 99 | writel_relaxed(val, pc->base + PWM_CTRL); |
| 100 | |
| 101 | clk_disable(pc->clk); |
| 102 | } |
| 103 | |
| 104 | static const struct pwm_ops rockchip_pwm_ops = { |
| 105 | .config = rockchip_pwm_config, |
| 106 | .enable = rockchip_pwm_enable, |
| 107 | .disable = rockchip_pwm_disable, |
| 108 | .owner = THIS_MODULE, |
| 109 | }; |
| 110 | |
| 111 | static int rockchip_pwm_probe(struct platform_device *pdev) |
| 112 | { |
| 113 | struct rockchip_pwm_chip *pc; |
| 114 | struct resource *r; |
| 115 | int ret; |
| 116 | |
| 117 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
| 118 | if (!pc) |
| 119 | return -ENOMEM; |
| 120 | |
| 121 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 122 | pc->base = devm_ioremap_resource(&pdev->dev, r); |
| 123 | if (IS_ERR(pc->base)) |
| 124 | return PTR_ERR(pc->base); |
| 125 | |
| 126 | pc->clk = devm_clk_get(&pdev->dev, NULL); |
| 127 | if (IS_ERR(pc->clk)) |
| 128 | return PTR_ERR(pc->clk); |
| 129 | |
| 130 | ret = clk_prepare(pc->clk); |
| 131 | if (ret) |
| 132 | return ret; |
| 133 | |
| 134 | platform_set_drvdata(pdev, pc); |
| 135 | |
| 136 | pc->chip.dev = &pdev->dev; |
| 137 | pc->chip.ops = &rockchip_pwm_ops; |
| 138 | pc->chip.base = -1; |
| 139 | pc->chip.npwm = 1; |
| 140 | |
| 141 | ret = pwmchip_add(&pc->chip); |
| 142 | if (ret < 0) { |
| 143 | clk_unprepare(pc->clk); |
| 144 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
| 145 | } |
| 146 | |
| 147 | return ret; |
| 148 | } |
| 149 | |
| 150 | static int rockchip_pwm_remove(struct platform_device *pdev) |
| 151 | { |
| 152 | struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); |
| 153 | |
| 154 | clk_unprepare(pc->clk); |
| 155 | |
| 156 | return pwmchip_remove(&pc->chip); |
| 157 | } |
| 158 | |
| 159 | static const struct of_device_id rockchip_pwm_dt_ids[] = { |
| 160 | { .compatible = "rockchip,rk2928-pwm" }, |
| 161 | { /* sentinel */ } |
| 162 | }; |
| 163 | MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); |
| 164 | |
| 165 | static struct platform_driver rockchip_pwm_driver = { |
| 166 | .driver = { |
| 167 | .name = "rockchip-pwm", |
| 168 | .of_match_table = rockchip_pwm_dt_ids, |
| 169 | }, |
| 170 | .probe = rockchip_pwm_probe, |
| 171 | .remove = rockchip_pwm_remove, |
| 172 | }; |
| 173 | module_platform_driver(rockchip_pwm_driver); |
| 174 | |
| 175 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); |
| 176 | MODULE_DESCRIPTION("Rockchip SoC PWM driver"); |
| 177 | MODULE_LICENSE("GPL v2"); |