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Ingo Molnar9f4c8152008-01-30 13:33:41 +01001/*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Thanks to Ben LaHaise for precious feedback.
Ingo Molnar9f4c8152008-01-30 13:33:41 +01004 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#include <linux/highmem.h>
Ingo Molnar81922062008-01-30 13:34:04 +01006#include <linux/bootmem.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#include <linux/module.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +01008#include <linux/sched.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +01009#include <linux/mm.h>
Thomas Gleixner76ebd052008-02-09 23:24:09 +010010#include <linux/interrupt.h>
Thomas Gleixneree7ae7a2008-04-17 17:40:45 +020011#include <linux/seq_file.h>
12#include <linux/debugfs.h>
Tejun Heoe59a1bb2009-06-22 11:56:24 +090013#include <linux/pfn.h>
Tejun Heo8c4bfc62009-07-04 08:10:59 +090014#include <linux/percpu.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/gfp.h>
Matthieu Castet5bd5a452010-11-16 22:31:26 +010016#include <linux/pci.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +010017
Thomas Gleixner950f9d92008-01-30 13:34:06 +010018#include <asm/e820.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019#include <asm/processor.h>
20#include <asm/tlbflush.h>
Dave Jonesf8af0952006-01-06 00:12:10 -080021#include <asm/sections.h>
Jeremy Fitzhardinge93dbda72009-02-26 17:35:44 -080022#include <asm/setup.h>
Ingo Molnar9f4c8152008-01-30 13:33:41 +010023#include <asm/uaccess.h>
24#include <asm/pgalloc.h>
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +010025#include <asm/proto.h>
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -070026#include <asm/pat.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Ingo Molnar9df84992008-02-04 16:48:09 +010028/*
29 * The current flushing context - we pass it instead of 5 arguments:
30 */
Thomas Gleixner72e458d2008-02-04 16:48:07 +010031struct cpa_data {
Shaohua Lid75586a2008-08-21 10:46:06 +080032 unsigned long *vaddr;
Thomas Gleixner72e458d2008-02-04 16:48:07 +010033 pgprot_t mask_set;
34 pgprot_t mask_clr;
Thomas Gleixner65e074d2008-02-04 16:48:07 +010035 int numpages;
Shaohua Lid75586a2008-08-21 10:46:06 +080036 int flags;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +010037 unsigned long pfn;
Andi Kleenc9caa022008-03-12 03:53:29 +010038 unsigned force_split : 1;
Shaohua Lid75586a2008-08-21 10:46:06 +080039 int curpage;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -070040 struct page **pages;
Thomas Gleixner72e458d2008-02-04 16:48:07 +010041};
42
Suresh Siddhaad5ca552008-09-23 14:00:42 -070043/*
44 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
45 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
46 * entries change the page attribute in parallel to some other cpu
47 * splitting a large page entry along with changing the attribute.
48 */
49static DEFINE_SPINLOCK(cpa_lock);
50
Shaohua Lid75586a2008-08-21 10:46:06 +080051#define CPA_FLUSHTLB 1
52#define CPA_ARRAY 2
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -070053#define CPA_PAGES_ARRAY 4
Shaohua Lid75586a2008-08-21 10:46:06 +080054
Thomas Gleixner65280e62008-05-05 16:35:21 +020055#ifdef CONFIG_PROC_FS
Andi Kleence0c0e52008-05-02 11:46:49 +020056static unsigned long direct_pages_count[PG_LEVEL_NUM];
57
Thomas Gleixner65280e62008-05-05 16:35:21 +020058void update_page_count(int level, unsigned long pages)
Andi Kleence0c0e52008-05-02 11:46:49 +020059{
Andi Kleence0c0e52008-05-02 11:46:49 +020060 /* Protect against CPA */
Andrea Arcangelia79e53d2011-02-16 15:45:22 -080061 spin_lock(&pgd_lock);
Andi Kleence0c0e52008-05-02 11:46:49 +020062 direct_pages_count[level] += pages;
Andrea Arcangelia79e53d2011-02-16 15:45:22 -080063 spin_unlock(&pgd_lock);
Andi Kleence0c0e52008-05-02 11:46:49 +020064}
65
Thomas Gleixner65280e62008-05-05 16:35:21 +020066static void split_page_count(int level)
67{
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
70}
71
Alexey Dobriyane1759c22008-10-15 23:50:22 +040072void arch_report_meminfo(struct seq_file *m)
Thomas Gleixner65280e62008-05-05 16:35:21 +020073{
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000074 seq_printf(m, "DirectMap4k: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010075 direct_pages_count[PG_LEVEL_4K] << 2);
76#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000077 seq_printf(m, "DirectMap2M: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010078 direct_pages_count[PG_LEVEL_2M] << 11);
79#else
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000080 seq_printf(m, "DirectMap4M: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010081 direct_pages_count[PG_LEVEL_2M] << 12);
82#endif
Thomas Gleixner65280e62008-05-05 16:35:21 +020083#ifdef CONFIG_X86_64
Hugh Dickinsa06de632008-08-15 13:58:32 +010084 if (direct_gbpages)
Hugh Dickinsb9c3bfc2008-11-06 12:05:40 +000085 seq_printf(m, "DirectMap1G: %8lu kB\n",
Hugh Dickinsa06de632008-08-15 13:58:32 +010086 direct_pages_count[PG_LEVEL_1G] << 20);
Thomas Gleixner65280e62008-05-05 16:35:21 +020087#endif
Thomas Gleixner65280e62008-05-05 16:35:21 +020088}
89#else
90static inline void split_page_count(int level) { }
91#endif
92
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +010093#ifdef CONFIG_X86_64
94
95static inline unsigned long highmap_start_pfn(void)
96{
Alexander Duyckfc8d7822012-11-16 13:57:13 -080097 return __pa_symbol(_text) >> PAGE_SHIFT;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +010098}
99
100static inline unsigned long highmap_end_pfn(void)
101{
Alexander Duyckfc8d7822012-11-16 13:57:13 -0800102 return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100103}
104
105#endif
106
Ingo Molnar92cb54a2008-02-13 14:37:52 +0100107#ifdef CONFIG_DEBUG_PAGEALLOC
108# define debug_pagealloc 1
109#else
110# define debug_pagealloc 0
111#endif
112
Arjan van de Vened724be2008-01-30 13:34:04 +0100113static inline int
114within(unsigned long addr, unsigned long start, unsigned long end)
Ingo Molnar687c4822008-01-30 13:34:04 +0100115{
Arjan van de Vened724be2008-01-30 13:34:04 +0100116 return addr >= start && addr < end;
117}
118
119/*
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100120 * Flushing functions
121 */
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100122
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100123/**
124 * clflush_cache_range - flush a cache range with clflush
Wanpeng Li9efc31b2012-06-10 10:50:52 +0800125 * @vaddr: virtual start address
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100126 * @size: number of bytes to flush
127 *
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
130 */
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100131void clflush_cache_range(void *vaddr, unsigned int size)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100132{
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100133 void *vend = vaddr + size - 1;
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100134
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100135 mb();
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100136
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
138 clflush(vaddr);
139 /*
140 * Flush any possible final partial cacheline:
141 */
142 clflush(vend);
143
Thomas Gleixnercd8ddf12008-01-30 13:34:08 +0100144 mb();
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100145}
Eric Anholte517a5e2009-09-10 17:48:48 -0700146EXPORT_SYMBOL_GPL(clflush_cache_range);
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100147
Thomas Gleixneraf1e6842008-01-30 13:34:08 +0100148static void __cpa_flush_all(void *arg)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100149{
Andi Kleen6bb83832008-02-04 16:48:06 +0100150 unsigned long cache = (unsigned long)arg;
151
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100152 /*
153 * Flush all to work around Errata in early athlons regarding
154 * large page flushing.
155 */
156 __flush_tlb_all();
157
venkatesh.pallipadi@intel.com0b827532009-05-22 13:23:37 -0700158 if (cache && boot_cpu_data.x86 >= 4)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100159 wbinvd();
160}
161
Andi Kleen6bb83832008-02-04 16:48:06 +0100162static void cpa_flush_all(unsigned long cache)
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100163{
164 BUG_ON(irqs_disabled());
165
Jens Axboe15c8b6c2008-05-09 09:39:44 +0200166 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100167}
168
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100169static void __cpa_flush_range(void *arg)
170{
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100171 /*
172 * We could optimize that further and do individual per page
173 * tlb invalidates for a low number of pages. Caveat: we must
174 * flush the high aliases on 64bit as well.
175 */
176 __flush_tlb_all();
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100177}
178
Andi Kleen6bb83832008-02-04 16:48:06 +0100179static void cpa_flush_range(unsigned long start, int numpages, int cache)
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100180{
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100181 unsigned int i, level;
182 unsigned long addr;
183
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100184 BUG_ON(irqs_disabled());
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100185 WARN_ON(PAGE_ALIGN(start) != start);
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100186
Jens Axboe15c8b6c2008-05-09 09:39:44 +0200187 on_each_cpu(__cpa_flush_range, NULL, 1);
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100188
Andi Kleen6bb83832008-02-04 16:48:06 +0100189 if (!cache)
190 return;
191
Thomas Gleixner3b233e52008-01-30 13:34:08 +0100192 /*
193 * We only need to flush on one CPU,
194 * clflush is a MESI-coherent instruction that
195 * will cause all other CPUs to flush the same
196 * cachelines:
197 */
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100198 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
199 pte_t *pte = lookup_address(addr, &level);
200
201 /*
202 * Only flush present addresses:
203 */
Thomas Gleixner7bfb72e2008-02-04 16:48:08 +0100204 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
Ingo Molnar4c61afc2008-01-30 13:34:09 +0100205 clflush_cache_range((void *) addr, PAGE_SIZE);
206 }
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100207}
208
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700209static void cpa_flush_array(unsigned long *start, int numpages, int cache,
210 int in_flags, struct page **pages)
Shaohua Lid75586a2008-08-21 10:46:06 +0800211{
212 unsigned int i, level;
Pallipadi, Venkatesh21717872009-05-26 10:33:35 -0700213 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
Shaohua Lid75586a2008-08-21 10:46:06 +0800214
215 BUG_ON(irqs_disabled());
216
Pallipadi, Venkatesh21717872009-05-26 10:33:35 -0700217 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
Shaohua Lid75586a2008-08-21 10:46:06 +0800218
Pallipadi, Venkatesh21717872009-05-26 10:33:35 -0700219 if (!cache || do_wbinvd)
Shaohua Lid75586a2008-08-21 10:46:06 +0800220 return;
221
Shaohua Lid75586a2008-08-21 10:46:06 +0800222 /*
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
226 * cachelines:
227 */
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700228 for (i = 0; i < numpages; i++) {
229 unsigned long addr;
230 pte_t *pte;
231
232 if (in_flags & CPA_PAGES_ARRAY)
233 addr = (unsigned long)page_address(pages[i]);
234 else
235 addr = start[i];
236
237 pte = lookup_address(addr, &level);
Shaohua Lid75586a2008-08-21 10:46:06 +0800238
239 /*
240 * Only flush present addresses:
241 */
242 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700243 clflush_cache_range((void *)addr, PAGE_SIZE);
Shaohua Lid75586a2008-08-21 10:46:06 +0800244 }
245}
246
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +0100247/*
Arjan van de Vened724be2008-01-30 13:34:04 +0100248 * Certain areas of memory on x86 require very specific protection flags,
249 * for example the BIOS area or kernel text. Callers don't always get this
250 * right (again, ioremap() on BIOS memory is not uncommon) so this function
251 * checks and fixes these known static required protection bits.
252 */
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100253static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
254 unsigned long pfn)
Arjan van de Vened724be2008-01-30 13:34:04 +0100255{
256 pgprot_t forbidden = __pgprot(0);
257
Ingo Molnar687c4822008-01-30 13:34:04 +0100258 /*
Arjan van de Vened724be2008-01-30 13:34:04 +0100259 * The BIOS area between 640k and 1Mb needs to be executable for
260 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
Ingo Molnar687c4822008-01-30 13:34:04 +0100261 */
Matthieu Castet5bd5a452010-11-16 22:31:26 +0100262#ifdef CONFIG_PCI_BIOS
263 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
Arjan van de Vened724be2008-01-30 13:34:04 +0100264 pgprot_val(forbidden) |= _PAGE_NX;
Matthieu Castet5bd5a452010-11-16 22:31:26 +0100265#endif
Arjan van de Vened724be2008-01-30 13:34:04 +0100266
267 /*
268 * The kernel text needs to be executable for obvious reasons
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100269 * Does not cover __inittext since that is gone later on. On
270 * 64bit we do not enforce !NX on the low mapping
Arjan van de Vened724be2008-01-30 13:34:04 +0100271 */
272 if (within(address, (unsigned long)_text, (unsigned long)_etext))
273 pgprot_val(forbidden) |= _PAGE_NX;
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100274
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100275 /*
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100276 * The .rodata section needs to be read-only. Using the pfn
277 * catches all aliases.
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100278 */
Alexander Duyckfc8d7822012-11-16 13:57:13 -0800279 if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
280 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
Arjan van de Vencc0f21b2008-02-04 16:48:05 +0100281 pgprot_val(forbidden) |= _PAGE_RW;
Arjan van de Vened724be2008-01-30 13:34:04 +0100282
Suresh Siddha55ca3cc2009-10-28 18:46:57 -0800283#if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
Suresh Siddha74e08172009-10-14 14:46:56 -0700284 /*
Suresh Siddha502f6602009-10-28 18:46:56 -0800285 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
286 * kernel text mappings for the large page aligned text, rodata sections
287 * will be always read-only. For the kernel identity mappings covering
288 * the holes caused by this alignment can be anything that user asks.
Suresh Siddha74e08172009-10-14 14:46:56 -0700289 *
290 * This will preserve the large page mappings for kernel text/data
291 * at no extra cost.
292 */
Suresh Siddha502f6602009-10-28 18:46:56 -0800293 if (kernel_set_to_readonly &&
294 within(address, (unsigned long)_text,
Suresh Siddha281ff332010-02-18 11:51:40 -0800295 (unsigned long)__end_rodata_hpage_align)) {
296 unsigned int level;
297
298 /*
299 * Don't enforce the !RW mapping for the kernel text mapping,
300 * if the current mapping is already using small page mapping.
301 * No need to work hard to preserve large page mappings in this
302 * case.
303 *
304 * This also fixes the Linux Xen paravirt guest boot failure
305 * (because of unexpected read-only mappings for kernel identity
306 * mappings). In this paravirt guest case, the kernel text
307 * mapping and the kernel identity mapping share the same
308 * page-table pages. Thus we can't really use different
309 * protections for the kernel text and identity mappings. Also,
310 * these shared mappings are made of small page mappings.
311 * Thus this don't enforce !RW mapping for small page kernel
312 * text mapping logic will help Linux Xen parvirt guest boot
Lucas De Marchi0d2eb442011-03-17 16:24:16 -0300313 * as well.
Suresh Siddha281ff332010-02-18 11:51:40 -0800314 */
315 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
316 pgprot_val(forbidden) |= _PAGE_RW;
317 }
Suresh Siddha74e08172009-10-14 14:46:56 -0700318#endif
319
Arjan van de Vened724be2008-01-30 13:34:04 +0100320 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
Ingo Molnar687c4822008-01-30 13:34:04 +0100321
322 return prot;
323}
324
Thomas Gleixner9a14aef2008-02-04 16:48:07 +0100325/*
326 * Lookup the page table entry for a virtual address. Return a pointer
327 * to the entry and the level of the mapping.
328 *
329 * Note: We return pud and pmd either when the entry is marked large
330 * or when the present bit is not set. Otherwise we would return a
331 * pointer to a nonexisting mapping.
332 */
Harvey Harrisonda7bfc52008-02-09 23:24:08 +0100333pte_t *lookup_address(unsigned long address, unsigned int *level)
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100334{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 pgd_t *pgd = pgd_offset_k(address);
336 pud_t *pud;
337 pmd_t *pmd;
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100338
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100339 *level = PG_LEVEL_NONE;
340
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341 if (pgd_none(*pgd))
342 return NULL;
Ingo Molnar9df84992008-02-04 16:48:09 +0100343
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 pud = pud_offset(pgd, address);
345 if (pud_none(*pud))
346 return NULL;
Andi Kleenc2f71ee2008-02-04 16:48:09 +0100347
348 *level = PG_LEVEL_1G;
349 if (pud_large(*pud) || !pud_present(*pud))
350 return (pte_t *)pud;
351
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 pmd = pmd_offset(pud, address);
353 if (pmd_none(*pmd))
354 return NULL;
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100355
356 *level = PG_LEVEL_2M;
Thomas Gleixner9a14aef2008-02-04 16:48:07 +0100357 if (pmd_large(*pmd) || !pmd_present(*pmd))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358 return (pte_t *)pmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100360 *level = PG_LEVEL_4K;
Ingo Molnar9df84992008-02-04 16:48:09 +0100361
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100362 return pte_offset_kernel(pmd, address);
363}
Pekka Paalanen75bb8832008-05-12 21:20:56 +0200364EXPORT_SYMBOL_GPL(lookup_address);
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100365
Ingo Molnar9df84992008-02-04 16:48:09 +0100366/*
367 * Set the new pmd in all the pgds we know about:
368 */
Ingo Molnar9a3dc782008-01-30 13:33:57 +0100369static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100370{
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100371 /* change init_mm */
372 set_pte_atomic(kpte, pte);
Ingo Molnar44af6c42008-01-30 13:34:03 +0100373#ifdef CONFIG_X86_32
Ingo Molnare4b71dc2008-01-30 13:34:04 +0100374 if (!SHARED_KERNEL_PMD) {
Ingo Molnar44af6c42008-01-30 13:34:03 +0100375 struct page *page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376
Jeremy Fitzhardingee3ed9102008-01-30 13:34:11 +0100377 list_for_each_entry(page, &pgd_list, lru) {
Ingo Molnar44af6c42008-01-30 13:34:03 +0100378 pgd_t *pgd;
379 pud_t *pud;
380 pmd_t *pmd;
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100381
Ingo Molnar44af6c42008-01-30 13:34:03 +0100382 pgd = (pgd_t *)page_address(page) + pgd_index(address);
383 pud = pud_offset(pgd, address);
384 pmd = pmd_offset(pud, address);
385 set_pte_atomic((pte_t *)pmd, pte);
386 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 }
Ingo Molnar44af6c42008-01-30 13:34:03 +0100388#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389}
390
Ingo Molnar9df84992008-02-04 16:48:09 +0100391static int
392try_preserve_large_page(pte_t *kpte, unsigned long address,
393 struct cpa_data *cpa)
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100394{
Andrea Arcangelia79e53d2011-02-16 15:45:22 -0800395 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100396 pte_t new_pte, old_pte, *tmp;
matthieu castet64edc8e2010-11-16 22:30:27 +0100397 pgprot_t old_prot, new_prot, req_prot;
Thomas Gleixnerfac84932008-02-09 23:24:09 +0100398 int i, do_split = 1;
Dave Hansenf3c4fbb2013-01-22 13:24:32 -0800399 enum pg_level level;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100400
Andi Kleenc9caa022008-03-12 03:53:29 +0100401 if (cpa->force_split)
402 return 1;
403
Andrea Arcangelia79e53d2011-02-16 15:45:22 -0800404 spin_lock(&pgd_lock);
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100405 /*
406 * Check for races, another CPU might have split this page
407 * up already:
408 */
409 tmp = lookup_address(address, &level);
410 if (tmp != kpte)
411 goto out_unlock;
412
413 switch (level) {
414 case PG_LEVEL_2M:
Andi Kleenf07333f2008-02-04 16:48:09 +0100415#ifdef CONFIG_X86_64
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100416 case PG_LEVEL_1G:
Andi Kleenf07333f2008-02-04 16:48:09 +0100417#endif
Dave Hansenf3c4fbb2013-01-22 13:24:32 -0800418 psize = page_level_size(level);
419 pmask = page_level_mask(level);
420 break;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100421 default:
Ingo Molnarbeaff632008-02-04 16:48:09 +0100422 do_split = -EINVAL;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100423 goto out_unlock;
424 }
425
426 /*
427 * Calculate the number of pages, which fit into this large
428 * page starting at address:
429 */
430 nextpage_addr = (address + psize) & pmask;
431 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100432 if (numpages < cpa->numpages)
433 cpa->numpages = numpages;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100434
435 /*
436 * We are safe now. Check whether the new pgprot is the same:
437 */
438 old_pte = *kpte;
matthieu castet64edc8e2010-11-16 22:30:27 +0100439 old_prot = new_prot = req_prot = pte_pgprot(old_pte);
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100440
matthieu castet64edc8e2010-11-16 22:30:27 +0100441 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
442 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100443
444 /*
445 * old_pte points to the large page base address. So we need
446 * to add the offset of the virtual address:
447 */
448 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
449 cpa->pfn = pfn;
450
matthieu castet64edc8e2010-11-16 22:30:27 +0100451 new_prot = static_protections(req_prot, address, pfn);
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100452
453 /*
Thomas Gleixnerfac84932008-02-09 23:24:09 +0100454 * We need to check the full range, whether
455 * static_protection() requires a different pgprot for one of
456 * the pages in the range we try to preserve:
457 */
matthieu castet64edc8e2010-11-16 22:30:27 +0100458 addr = address & pmask;
459 pfn = pte_pfn(old_pte);
460 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
461 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
Thomas Gleixnerfac84932008-02-09 23:24:09 +0100462
463 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
464 goto out_unlock;
465 }
466
467 /*
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100468 * If there are no changes, return. maxpages has been updated
469 * above:
470 */
471 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
Ingo Molnarbeaff632008-02-04 16:48:09 +0100472 do_split = 0;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100473 goto out_unlock;
474 }
475
476 /*
477 * We need to change the attributes. Check, whether we can
478 * change the large page in one go. We request a split, when
479 * the address is not aligned and the number of pages is
480 * smaller than the number of pages in the large page. Note
481 * that we limited the number of possible pages already to
482 * the number of pages in the large page.
483 */
matthieu castet64edc8e2010-11-16 22:30:27 +0100484 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100485 /*
486 * The address is aligned and the number of pages
487 * covers the full page.
488 */
489 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
490 __set_pmd_pte(kpte, address, new_pte);
Shaohua Lid75586a2008-08-21 10:46:06 +0800491 cpa->flags |= CPA_FLUSHTLB;
Ingo Molnarbeaff632008-02-04 16:48:09 +0100492 do_split = 0;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100493 }
494
495out_unlock:
Andrea Arcangelia79e53d2011-02-16 15:45:22 -0800496 spin_unlock(&pgd_lock);
Ingo Molnar9df84992008-02-04 16:48:09 +0100497
Ingo Molnarbeaff632008-02-04 16:48:09 +0100498 return do_split;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100499}
500
Ingo Molnar7afe15b2008-01-30 13:33:57 +0100501static int split_large_page(pte_t *kpte, unsigned long address)
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100502{
Andrea Arcangelia79e53d2011-02-16 15:45:22 -0800503 unsigned long pfn, pfninc = 1;
Ingo Molnar86f03982008-01-30 13:34:09 +0100504 unsigned int i, level;
Ingo Molnar9df84992008-02-04 16:48:09 +0100505 pte_t *pbase, *tmp;
506 pgprot_t ref_prot;
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700507 struct page *base;
508
509 if (!debug_pagealloc)
510 spin_unlock(&cpa_lock);
Vegard Nossum9e730232009-02-22 11:28:25 +0100511 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700512 if (!debug_pagealloc)
513 spin_lock(&cpa_lock);
Suresh Siddha8311eb82008-09-23 14:00:41 -0700514 if (!base)
515 return -ENOMEM;
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100516
Andrea Arcangelia79e53d2011-02-16 15:45:22 -0800517 spin_lock(&pgd_lock);
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100518 /*
519 * Check for races, another CPU might have split this page
520 * up for us already:
521 */
522 tmp = lookup_address(address, &level);
Ingo Molnar6ce9fc12008-02-04 16:48:08 +0100523 if (tmp != kpte)
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100524 goto out_unlock;
525
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100526 pbase = (pte_t *)page_address(base);
Jeremy Fitzhardinge6944a9c2008-03-17 16:37:01 -0700527 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
Thomas Gleixner07cf89c2008-02-04 16:48:08 +0100528 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
Ingo Molnar7a5714e2009-02-20 17:44:21 +0100529 /*
530 * If we ever want to utilize the PAT bit, we need to
531 * update this function to make sure it's converted from
532 * bit 12 to bit 7 when we cross from the 2MB level to
533 * the 4K level:
534 */
535 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100536
Andi Kleenf07333f2008-02-04 16:48:09 +0100537#ifdef CONFIG_X86_64
538 if (level == PG_LEVEL_1G) {
539 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
540 pgprot_val(ref_prot) |= _PAGE_PSE;
Andi Kleenf07333f2008-02-04 16:48:09 +0100541 }
542#endif
543
Thomas Gleixner63c1dcf2008-02-04 16:48:05 +0100544 /*
545 * Get the target pfn from the original entry:
546 */
547 pfn = pte_pfn(*kpte);
Andi Kleenf07333f2008-02-04 16:48:09 +0100548 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
Thomas Gleixner63c1dcf2008-02-04 16:48:05 +0100549 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100550
Andi Kleence0c0e52008-05-02 11:46:49 +0200551 if (address >= (unsigned long)__va(0) &&
Yinghai Luf361a452008-07-10 20:38:26 -0700552 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
553 split_page_count(level);
554
555#ifdef CONFIG_X86_64
556 if (address >= (unsigned long)__va(1UL<<32) &&
Thomas Gleixner65280e62008-05-05 16:35:21 +0200557 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
558 split_page_count(level);
Yinghai Luf361a452008-07-10 20:38:26 -0700559#endif
Andi Kleence0c0e52008-05-02 11:46:49 +0200560
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100561 /*
Ingo Molnar07a66d72009-02-20 08:04:13 +0100562 * Install the new, split up pagetable.
Huang, Ying4c881ca2008-01-30 13:34:04 +0100563 *
Ingo Molnar07a66d72009-02-20 08:04:13 +0100564 * We use the standard kernel pagetable protections for the new
565 * pagetable protections, the actual ptes set above control the
566 * primary protection behavior:
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100567 */
Ingo Molnar07a66d72009-02-20 08:04:13 +0100568 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
Ingo Molnar211b3d02009-03-10 22:31:03 +0100569
570 /*
571 * Intel Atom errata AAH41 workaround.
572 *
573 * The real fix should be in hw or in a microcode update, but
574 * we also probabilistically try to reduce the window of having
575 * a large TLB mixed with 4K TLBs while instruction fetches are
576 * going on.
577 */
578 __flush_tlb_all();
579
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100580 base = NULL;
581
582out_unlock:
Thomas Gleixnereb5b5f02008-02-09 23:24:09 +0100583 /*
584 * If we dropped out via the lookup_address check under
585 * pgd_lock then stick the page back into the pool:
586 */
Suresh Siddha8311eb82008-09-23 14:00:41 -0700587 if (base)
588 __free_page(base);
Andrea Arcangelia79e53d2011-02-16 15:45:22 -0800589 spin_unlock(&pgd_lock);
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100590
Ingo Molnarbb5c2db2008-01-30 13:33:56 +0100591 return 0;
592}
593
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800594static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
595 int primary)
596{
597 /*
598 * Ignore all non primary paths.
599 */
600 if (!primary)
601 return 0;
602
603 /*
604 * Ignore the NULL PTE for kernel identity mapping, as it is expected
605 * to have holes.
606 * Also set numpages to '1' indicating that we processed cpa req for
607 * one virtual address page and its pfn. TBD: numpages can be set based
608 * on the initial value and the level returned by lookup_address().
609 */
610 if (within(vaddr, PAGE_OFFSET,
611 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
612 cpa->numpages = 1;
613 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
614 return 0;
615 } else {
616 WARN(1, KERN_WARNING "CPA: called for zero pte. "
617 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
618 *cpa->vaddr);
619
620 return -EFAULT;
621 }
622}
623
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100624static int __change_page_attr(struct cpa_data *cpa, int primary)
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100625{
Shaohua Lid75586a2008-08-21 10:46:06 +0800626 unsigned long address;
Harvey Harrisonda7bfc52008-02-09 23:24:08 +0100627 int do_split, err;
628 unsigned int level;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100629 pte_t *kpte, old_pte;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630
Thomas Hellstrom8523acf2009-08-03 09:25:45 +0200631 if (cpa->flags & CPA_PAGES_ARRAY) {
632 struct page *page = cpa->pages[cpa->curpage];
633 if (unlikely(PageHighMem(page)))
634 return 0;
635 address = (unsigned long)page_address(page);
636 } else if (cpa->flags & CPA_ARRAY)
Shaohua Lid75586a2008-08-21 10:46:06 +0800637 address = cpa->vaddr[cpa->curpage];
638 else
639 address = *cpa->vaddr;
Ingo Molnar97f99fe2008-01-30 13:33:55 +0100640repeat:
Ingo Molnarf0646e42008-01-30 13:33:43 +0100641 kpte = lookup_address(address, &level);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642 if (!kpte)
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800643 return __cpa_process_fault(cpa, address, primary);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100644
645 old_pte = *kpte;
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800646 if (!pte_val(old_pte))
647 return __cpa_process_fault(cpa, address, primary);
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100648
Thomas Gleixner30551bb2008-01-30 13:34:04 +0100649 if (level == PG_LEVEL_4K) {
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100650 pte_t new_pte;
Arjan van de Ven626c2c92008-02-04 16:48:05 +0100651 pgprot_t new_prot = pte_pgprot(old_pte);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100652 unsigned long pfn = pte_pfn(old_pte);
Thomas Gleixnera72a08a2008-01-30 13:34:07 +0100653
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100654 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
655 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
Ingo Molnar86f03982008-01-30 13:34:09 +0100656
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100657 new_prot = static_protections(new_prot, address, pfn);
Ingo Molnar86f03982008-01-30 13:34:09 +0100658
Arjan van de Ven626c2c92008-02-04 16:48:05 +0100659 /*
660 * We need to keep the pfn from the existing PTE,
661 * after all we're only going to change it's attributes
662 * not the memory it points to
663 */
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100664 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
665 cpa->pfn = pfn;
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100666 /*
667 * Do we really change anything ?
668 */
669 if (pte_val(old_pte) != pte_val(new_pte)) {
670 set_pte_atomic(kpte, new_pte);
Shaohua Lid75586a2008-08-21 10:46:06 +0800671 cpa->flags |= CPA_FLUSHTLB;
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100672 }
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100673 cpa->numpages = 1;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100674 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 }
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100676
677 /*
678 * Check, whether we can keep the large page intact
679 * and just change the pte:
680 */
Ingo Molnarbeaff632008-02-04 16:48:09 +0100681 do_split = try_preserve_large_page(kpte, address, cpa);
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100682 /*
683 * When the range fits into the existing large page,
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100684 * return. cp->numpages and cpa->tlbflush have been updated in
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100685 * try_large_page:
686 */
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100687 if (do_split <= 0)
688 return do_split;
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100689
690 /*
691 * We have to split the large page:
692 */
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100693 err = split_large_page(kpte, address);
694 if (!err) {
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700695 /*
696 * Do a global flush tlb after splitting the large page
697 * and before we do the actual change page attribute in the PTE.
698 *
699 * With out this, we violate the TLB application note, that says
700 * "The TLBs may contain both ordinary and large-page
701 * translations for a 4-KByte range of linear addresses. This
702 * may occur if software modifies the paging structures so that
703 * the page size used for the address range changes. If the two
704 * translations differ with respect to page frame or attributes
705 * (e.g., permissions), processor behavior is undefined and may
706 * be implementation-specific."
707 *
708 * We do this global tlb flush inside the cpa_lock, so that we
709 * don't allow any other cpu, with stale tlb entries change the
710 * page attribute in parallel, that also falls into the
711 * just split large page entry.
712 */
713 flush_tlb_all();
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100714 goto repeat;
715 }
Ingo Molnarbeaff632008-02-04 16:48:09 +0100716
Ingo Molnar87f7f8f2008-02-04 16:48:10 +0100717 return err;
Ingo Molnar9f4c8152008-01-30 13:33:41 +0100718}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100720static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
721
722static int cpa_process_alias(struct cpa_data *cpa)
Ingo Molnar44af6c42008-01-30 13:34:03 +0100723{
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100724 struct cpa_data alias_cpa;
Tejun Heo992f4c12009-06-22 11:56:24 +0900725 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
Tejun Heoe933a732009-08-14 15:00:53 +0900726 unsigned long vaddr;
Tejun Heo992f4c12009-06-22 11:56:24 +0900727 int ret;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100728
Yinghai Lu965194c2008-07-12 14:31:28 -0700729 if (cpa->pfn >= max_pfn_mapped)
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100730 return 0;
731
Yinghai Luf361a452008-07-10 20:38:26 -0700732#ifdef CONFIG_X86_64
Yinghai Lu965194c2008-07-12 14:31:28 -0700733 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
Yinghai Luf361a452008-07-10 20:38:26 -0700734 return 0;
735#endif
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100736 /*
737 * No need to redo, when the primary call touched the direct
738 * mapping already:
739 */
Thomas Hellstrom8523acf2009-08-03 09:25:45 +0200740 if (cpa->flags & CPA_PAGES_ARRAY) {
741 struct page *page = cpa->pages[cpa->curpage];
742 if (unlikely(PageHighMem(page)))
743 return 0;
744 vaddr = (unsigned long)page_address(page);
745 } else if (cpa->flags & CPA_ARRAY)
Shaohua Lid75586a2008-08-21 10:46:06 +0800746 vaddr = cpa->vaddr[cpa->curpage];
747 else
748 vaddr = *cpa->vaddr;
749
750 if (!(within(vaddr, PAGE_OFFSET,
Suresh Siddhaa1e46212009-01-20 14:20:21 -0800751 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100752
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100753 alias_cpa = *cpa;
Tejun Heo992f4c12009-06-22 11:56:24 +0900754 alias_cpa.vaddr = &laddr;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700755 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
Shaohua Lid75586a2008-08-21 10:46:06 +0800756
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100757 ret = __change_page_attr_set_clr(&alias_cpa, 0);
Tejun Heo992f4c12009-06-22 11:56:24 +0900758 if (ret)
759 return ret;
Thomas Gleixnerf34b4392008-02-15 22:17:57 +0100760 }
Ingo Molnar44af6c42008-01-30 13:34:03 +0100761
Arjan van de Ven488fd992008-01-30 13:34:07 +0100762#ifdef CONFIG_X86_64
Thomas Gleixner08797502008-01-30 13:34:09 +0100763 /*
Tejun Heo992f4c12009-06-22 11:56:24 +0900764 * If the primary call didn't touch the high mapping already
765 * and the physical address is inside the kernel map, we need
Thomas Gleixner08797502008-01-30 13:34:09 +0100766 * to touch the high mapped kernel as well:
767 */
Tejun Heo992f4c12009-06-22 11:56:24 +0900768 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
769 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
770 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
771 __START_KERNEL_map - phys_base;
772 alias_cpa = *cpa;
773 alias_cpa.vaddr = &temp_cpa_vaddr;
774 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
Thomas Gleixner08797502008-01-30 13:34:09 +0100775
Tejun Heo992f4c12009-06-22 11:56:24 +0900776 /*
777 * The high mapping range is imprecise, so ignore the
778 * return value.
779 */
780 __change_page_attr_set_clr(&alias_cpa, 0);
781 }
Thomas Gleixner08797502008-01-30 13:34:09 +0100782#endif
Tejun Heo992f4c12009-06-22 11:56:24 +0900783
784 return 0;
Ingo Molnar44af6c42008-01-30 13:34:03 +0100785}
786
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100787static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
Thomas Gleixnerff314522008-01-30 13:34:08 +0100788{
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100789 int ret, numpages = cpa->numpages;
Thomas Gleixnerff314522008-01-30 13:34:08 +0100790
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100791 while (numpages) {
792 /*
793 * Store the remaining nr of pages for the large page
794 * preservation check.
795 */
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100796 cpa->numpages = numpages;
Shaohua Lid75586a2008-08-21 10:46:06 +0800797 /* for array changes, we can't use large page */
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700798 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
Shaohua Lid75586a2008-08-21 10:46:06 +0800799 cpa->numpages = 1;
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100800
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700801 if (!debug_pagealloc)
802 spin_lock(&cpa_lock);
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100803 ret = __change_page_attr(cpa, checkalias);
Suresh Siddhaad5ca552008-09-23 14:00:42 -0700804 if (!debug_pagealloc)
805 spin_unlock(&cpa_lock);
Thomas Gleixnerff314522008-01-30 13:34:08 +0100806 if (ret)
807 return ret;
Thomas Gleixnerff314522008-01-30 13:34:08 +0100808
Thomas Gleixnerc31c7d42008-02-18 20:54:14 +0100809 if (checkalias) {
810 ret = cpa_process_alias(cpa);
811 if (ret)
812 return ret;
813 }
814
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100815 /*
816 * Adjust the number of pages with the result of the
817 * CPA operation. Either a large page has been
818 * preserved or a single page update happened.
819 */
Rafael J. Wysocki9b5cf482008-03-03 01:17:37 +0100820 BUG_ON(cpa->numpages > numpages);
821 numpages -= cpa->numpages;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700822 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
Shaohua Lid75586a2008-08-21 10:46:06 +0800823 cpa->curpage++;
824 else
825 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
826
Thomas Gleixner65e074d2008-02-04 16:48:07 +0100827 }
Thomas Gleixnerff314522008-01-30 13:34:08 +0100828 return 0;
829}
830
Andi Kleen6bb83832008-02-04 16:48:06 +0100831static inline int cache_attr(pgprot_t attr)
832{
833 return pgprot_val(attr) &
834 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
835}
836
Shaohua Lid75586a2008-08-21 10:46:06 +0800837static int change_page_attr_set_clr(unsigned long *addr, int numpages,
Andi Kleenc9caa022008-03-12 03:53:29 +0100838 pgprot_t mask_set, pgprot_t mask_clr,
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700839 int force_split, int in_flag,
840 struct page **pages)
Thomas Gleixnerff314522008-01-30 13:34:08 +0100841{
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100842 struct cpa_data cpa;
Ingo Molnarcacf8902008-08-21 13:46:33 +0200843 int ret, cache, checkalias;
Jack Steinerfa526d02009-09-03 12:56:02 -0500844 unsigned long baddr = 0;
Thomas Gleixner331e4062008-02-04 16:48:06 +0100845
846 /*
847 * Check, if we are requested to change a not supported
848 * feature:
849 */
850 mask_set = canon_pgprot(mask_set);
851 mask_clr = canon_pgprot(mask_clr);
Andi Kleenc9caa022008-03-12 03:53:29 +0100852 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
Thomas Gleixner331e4062008-02-04 16:48:06 +0100853 return 0;
854
Thomas Gleixner69b14152008-02-13 11:04:50 +0100855 /* Ensure we are PAGE_SIZE aligned */
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700856 if (in_flag & CPA_ARRAY) {
Shaohua Lid75586a2008-08-21 10:46:06 +0800857 int i;
858 for (i = 0; i < numpages; i++) {
859 if (addr[i] & ~PAGE_MASK) {
860 addr[i] &= PAGE_MASK;
861 WARN_ON_ONCE(1);
862 }
863 }
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700864 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
865 /*
866 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
867 * No need to cehck in that case
868 */
869 if (*addr & ~PAGE_MASK) {
870 *addr &= PAGE_MASK;
871 /*
872 * People should not be passing in unaligned addresses:
873 */
874 WARN_ON_ONCE(1);
875 }
Jack Steinerfa526d02009-09-03 12:56:02 -0500876 /*
877 * Save address for cache flush. *addr is modified in the call
878 * to __change_page_attr_set_clr() below.
879 */
880 baddr = *addr;
Thomas Gleixner69b14152008-02-13 11:04:50 +0100881 }
882
Nick Piggin5843d9a2008-08-01 03:15:21 +0200883 /* Must avoid aliasing mappings in the highmem code */
884 kmap_flush_unused();
885
Nick Piggindb64fe02008-10-18 20:27:03 -0700886 vm_unmap_aliases();
887
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100888 cpa.vaddr = addr;
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700889 cpa.pages = pages;
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100890 cpa.numpages = numpages;
891 cpa.mask_set = mask_set;
892 cpa.mask_clr = mask_clr;
Shaohua Lid75586a2008-08-21 10:46:06 +0800893 cpa.flags = 0;
894 cpa.curpage = 0;
Andi Kleenc9caa022008-03-12 03:53:29 +0100895 cpa.force_split = force_split;
Thomas Gleixner72e458d2008-02-04 16:48:07 +0100896
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700897 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
898 cpa.flags |= in_flag;
Shaohua Lid75586a2008-08-21 10:46:06 +0800899
Thomas Gleixneraf96e442008-02-15 21:49:46 +0100900 /* No alias checking for _NX bit modifications */
901 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
902
903 ret = __change_page_attr_set_clr(&cpa, checkalias);
Thomas Gleixnerff314522008-01-30 13:34:08 +0100904
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100905 /*
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100906 * Check whether we really changed something:
907 */
Shaohua Lid75586a2008-08-21 10:46:06 +0800908 if (!(cpa.flags & CPA_FLUSHTLB))
Shaohua Li1ac2f7d2008-08-04 14:51:24 +0800909 goto out;
Ingo Molnarcacf8902008-08-21 13:46:33 +0200910
Thomas Gleixnerf4ae5da2008-02-04 16:48:07 +0100911 /*
Andi Kleen6bb83832008-02-04 16:48:06 +0100912 * No need to flush, when we did not set any of the caching
913 * attributes:
914 */
915 cache = cache_attr(mask_set);
916
917 /*
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100918 * On success we use clflush, when the CPU supports it to
H. Peter Anvinf026cfa2012-08-14 09:53:38 -0700919 * avoid the wbindv. If the CPU does not support it and in the
920 * error case we fall back to cpa_flush_all (which uses
921 * wbindv):
Thomas Gleixner57a6a462008-01-30 13:34:08 +0100922 */
H. Peter Anvinf026cfa2012-08-14 09:53:38 -0700923 if (!ret && cpu_has_clflush) {
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700924 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
925 cpa_flush_array(addr, numpages, cache,
926 cpa.flags, pages);
927 } else
Jack Steinerfa526d02009-09-03 12:56:02 -0500928 cpa_flush_range(baddr, numpages, cache);
Shaohua Lid75586a2008-08-21 10:46:06 +0800929 } else
Andi Kleen6bb83832008-02-04 16:48:06 +0100930 cpa_flush_all(cache);
Ingo Molnarcacf8902008-08-21 13:46:33 +0200931
Thomas Gleixner76ebd052008-02-09 23:24:09 +0100932out:
Thomas Gleixnerff314522008-01-30 13:34:08 +0100933 return ret;
934}
935
Shaohua Lid75586a2008-08-21 10:46:06 +0800936static inline int change_page_attr_set(unsigned long *addr, int numpages,
937 pgprot_t mask, int array)
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100938{
Shaohua Lid75586a2008-08-21 10:46:06 +0800939 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700940 (array ? CPA_ARRAY : 0), NULL);
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100941}
942
Shaohua Lid75586a2008-08-21 10:46:06 +0800943static inline int change_page_attr_clear(unsigned long *addr, int numpages,
944 pgprot_t mask, int array)
Thomas Gleixner72932c72008-01-30 13:34:08 +0100945{
Shaohua Lid75586a2008-08-21 10:46:06 +0800946 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -0700947 (array ? CPA_ARRAY : 0), NULL);
Thomas Gleixner72932c72008-01-30 13:34:08 +0100948}
949
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -0700950static inline int cpa_set_pages_array(struct page **pages, int numpages,
951 pgprot_t mask)
952{
953 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
954 CPA_PAGES_ARRAY, pages);
955}
956
957static inline int cpa_clear_pages_array(struct page **pages, int numpages,
958 pgprot_t mask)
959{
960 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
961 CPA_PAGES_ARRAY, pages);
962}
963
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700964int _set_memory_uc(unsigned long addr, int numpages)
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100965{
Suresh Siddhade33c442008-04-25 17:07:22 -0700966 /*
967 * for now UC MINUS. see comments in ioremap_nocache()
968 */
Shaohua Lid75586a2008-08-21 10:46:06 +0800969 return change_page_attr_set(&addr, numpages,
970 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100971}
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700972
973int set_memory_uc(unsigned long addr, int numpages)
974{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -0700975 int ret;
976
Suresh Siddhade33c442008-04-25 17:07:22 -0700977 /*
978 * for now UC MINUS. see comments in ioremap_nocache()
979 */
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -0700980 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
981 _PAGE_CACHE_UC_MINUS, NULL);
982 if (ret)
983 goto out_err;
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700984
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -0700985 ret = _set_memory_uc(addr, numpages);
986 if (ret)
987 goto out_free;
988
989 return 0;
990
991out_free:
992 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
993out_err:
994 return ret;
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -0700995}
Arjan van de Ven75cbade2008-01-30 13:34:06 +0100996EXPORT_SYMBOL(set_memory_uc);
997
H Hartley Sweeten2d070ef2011-11-15 14:49:00 -0800998static int _set_memory_array(unsigned long *addr, int addrinarray,
Pauli Nieminen4f646252010-04-01 12:45:01 +0000999 unsigned long new_type)
Shaohua Lid75586a2008-08-21 10:46:06 +08001000{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001001 int i, j;
1002 int ret;
1003
Shaohua Lid75586a2008-08-21 10:46:06 +08001004 /*
1005 * for now UC MINUS. see comments in ioremap_nocache()
1006 */
1007 for (i = 0; i < addrinarray; i++) {
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001008 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
Pauli Nieminen4f646252010-04-01 12:45:01 +00001009 new_type, NULL);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001010 if (ret)
1011 goto out_free;
Shaohua Lid75586a2008-08-21 10:46:06 +08001012 }
1013
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001014 ret = change_page_attr_set(addr, addrinarray,
Shaohua Lid75586a2008-08-21 10:46:06 +08001015 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
Pauli Nieminen4f646252010-04-01 12:45:01 +00001016
1017 if (!ret && new_type == _PAGE_CACHE_WC)
1018 ret = change_page_attr_set_clr(addr, addrinarray,
1019 __pgprot(_PAGE_CACHE_WC),
1020 __pgprot(_PAGE_CACHE_MASK),
1021 0, CPA_ARRAY, NULL);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001022 if (ret)
1023 goto out_free;
Rene Hermanc5e147c2008-08-22 01:02:20 +02001024
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001025 return 0;
1026
1027out_free:
1028 for (j = 0; j < i; j++)
1029 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1030
1031 return ret;
Shaohua Lid75586a2008-08-21 10:46:06 +08001032}
Pauli Nieminen4f646252010-04-01 12:45:01 +00001033
1034int set_memory_array_uc(unsigned long *addr, int addrinarray)
1035{
1036 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1037}
Shaohua Lid75586a2008-08-21 10:46:06 +08001038EXPORT_SYMBOL(set_memory_array_uc);
1039
Pauli Nieminen4f646252010-04-01 12:45:01 +00001040int set_memory_array_wc(unsigned long *addr, int addrinarray)
1041{
1042 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1043}
1044EXPORT_SYMBOL(set_memory_array_wc);
1045
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001046int _set_memory_wc(unsigned long addr, int numpages)
1047{
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001048 int ret;
Pallipadi, Venkateshbdc63402009-07-30 14:43:19 -07001049 unsigned long addr_copy = addr;
1050
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001051 ret = change_page_attr_set(&addr, numpages,
1052 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001053 if (!ret) {
Pallipadi, Venkateshbdc63402009-07-30 14:43:19 -07001054 ret = change_page_attr_set_clr(&addr_copy, numpages,
1055 __pgprot(_PAGE_CACHE_WC),
1056 __pgprot(_PAGE_CACHE_MASK),
1057 0, 0, NULL);
venkatesh.pallipadi@intel.com3869c4a2009-04-09 14:26:50 -07001058 }
1059 return ret;
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001060}
1061
1062int set_memory_wc(unsigned long addr, int numpages)
1063{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001064 int ret;
1065
Andreas Herrmann499f8f82008-06-10 16:06:21 +02001066 if (!pat_enabled)
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001067 return set_memory_uc(addr, numpages);
1068
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001069 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1070 _PAGE_CACHE_WC, NULL);
1071 if (ret)
1072 goto out_err;
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001073
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001074 ret = _set_memory_wc(addr, numpages);
1075 if (ret)
1076 goto out_free;
1077
1078 return 0;
1079
1080out_free:
1081 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1082out_err:
1083 return ret;
venkatesh.pallipadi@intel.comef354af2008-03-18 17:00:23 -07001084}
1085EXPORT_SYMBOL(set_memory_wc);
1086
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -07001087int _set_memory_wb(unsigned long addr, int numpages)
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001088{
Shaohua Lid75586a2008-08-21 10:46:06 +08001089 return change_page_attr_clear(&addr, numpages,
1090 __pgprot(_PAGE_CACHE_MASK), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001091}
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -07001092
1093int set_memory_wb(unsigned long addr, int numpages)
1094{
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001095 int ret;
1096
1097 ret = _set_memory_wb(addr, numpages);
1098 if (ret)
1099 return ret;
1100
venkatesh.pallipadi@intel.comc15238d2008-08-20 16:45:51 -07001101 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001102 return 0;
venkatesh.pallipadi@intel.com12193332008-03-18 17:00:18 -07001103}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001104EXPORT_SYMBOL(set_memory_wb);
1105
Shaohua Lid75586a2008-08-21 10:46:06 +08001106int set_memory_array_wb(unsigned long *addr, int addrinarray)
1107{
1108 int i;
venkatesh.pallipadi@intel.coma5593e02009-04-09 14:26:48 -07001109 int ret;
1110
1111 ret = change_page_attr_clear(addr, addrinarray,
1112 __pgprot(_PAGE_CACHE_MASK), 1);
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001113 if (ret)
1114 return ret;
Shaohua Lid75586a2008-08-21 10:46:06 +08001115
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001116 for (i = 0; i < addrinarray; i++)
1117 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
Rene Hermanc5e147c2008-08-22 01:02:20 +02001118
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001119 return 0;
Shaohua Lid75586a2008-08-21 10:46:06 +08001120}
1121EXPORT_SYMBOL(set_memory_array_wb);
1122
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001123int set_memory_x(unsigned long addr, int numpages)
1124{
H. Peter Anvin583140a2009-11-13 15:28:15 -08001125 if (!(__supported_pte_mask & _PAGE_NX))
1126 return 0;
1127
Shaohua Lid75586a2008-08-21 10:46:06 +08001128 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001129}
1130EXPORT_SYMBOL(set_memory_x);
1131
1132int set_memory_nx(unsigned long addr, int numpages)
1133{
H. Peter Anvin583140a2009-11-13 15:28:15 -08001134 if (!(__supported_pte_mask & _PAGE_NX))
1135 return 0;
1136
Shaohua Lid75586a2008-08-21 10:46:06 +08001137 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001138}
1139EXPORT_SYMBOL(set_memory_nx);
1140
1141int set_memory_ro(unsigned long addr, int numpages)
1142{
Shaohua Lid75586a2008-08-21 10:46:06 +08001143 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001144}
Bruce Allana03352d2008-09-29 20:19:22 -07001145EXPORT_SYMBOL_GPL(set_memory_ro);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001146
1147int set_memory_rw(unsigned long addr, int numpages)
1148{
Shaohua Lid75586a2008-08-21 10:46:06 +08001149 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001150}
Bruce Allana03352d2008-09-29 20:19:22 -07001151EXPORT_SYMBOL_GPL(set_memory_rw);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001152
1153int set_memory_np(unsigned long addr, int numpages)
1154{
Shaohua Lid75586a2008-08-21 10:46:06 +08001155 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001156}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001157
Andi Kleenc9caa022008-03-12 03:53:29 +01001158int set_memory_4k(unsigned long addr, int numpages)
1159{
Shaohua Lid75586a2008-08-21 10:46:06 +08001160 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
venkatesh.pallipadi@intel.com9ae28472009-03-19 14:51:14 -07001161 __pgprot(0), 1, 0, NULL);
Andi Kleenc9caa022008-03-12 03:53:29 +01001162}
1163
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001164int set_pages_uc(struct page *page, int numpages)
1165{
1166 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001167
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001168 return set_memory_uc(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001169}
1170EXPORT_SYMBOL(set_pages_uc);
1171
Pauli Nieminen4f646252010-04-01 12:45:01 +00001172static int _set_pages_array(struct page **pages, int addrinarray,
1173 unsigned long new_type)
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001174{
1175 unsigned long start;
1176 unsigned long end;
1177 int i;
1178 int free_idx;
Pauli Nieminen4f646252010-04-01 12:45:01 +00001179 int ret;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001180
1181 for (i = 0; i < addrinarray; i++) {
Thomas Hellstrom8523acf2009-08-03 09:25:45 +02001182 if (PageHighMem(pages[i]))
1183 continue;
1184 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001185 end = start + PAGE_SIZE;
Pauli Nieminen4f646252010-04-01 12:45:01 +00001186 if (reserve_memtype(start, end, new_type, NULL))
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001187 goto err_out;
1188 }
1189
Pauli Nieminen4f646252010-04-01 12:45:01 +00001190 ret = cpa_set_pages_array(pages, addrinarray,
1191 __pgprot(_PAGE_CACHE_UC_MINUS));
1192 if (!ret && new_type == _PAGE_CACHE_WC)
1193 ret = change_page_attr_set_clr(NULL, addrinarray,
1194 __pgprot(_PAGE_CACHE_WC),
1195 __pgprot(_PAGE_CACHE_MASK),
1196 0, CPA_PAGES_ARRAY, pages);
1197 if (ret)
1198 goto err_out;
1199 return 0; /* Success */
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001200err_out:
1201 free_idx = i;
1202 for (i = 0; i < free_idx; i++) {
Thomas Hellstrom8523acf2009-08-03 09:25:45 +02001203 if (PageHighMem(pages[i]))
1204 continue;
1205 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001206 end = start + PAGE_SIZE;
1207 free_memtype(start, end);
1208 }
1209 return -EINVAL;
1210}
Pauli Nieminen4f646252010-04-01 12:45:01 +00001211
1212int set_pages_array_uc(struct page **pages, int addrinarray)
1213{
1214 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1215}
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001216EXPORT_SYMBOL(set_pages_array_uc);
1217
Pauli Nieminen4f646252010-04-01 12:45:01 +00001218int set_pages_array_wc(struct page **pages, int addrinarray)
1219{
1220 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1221}
1222EXPORT_SYMBOL(set_pages_array_wc);
1223
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001224int set_pages_wb(struct page *page, int numpages)
1225{
1226 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001227
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001228 return set_memory_wb(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001229}
1230EXPORT_SYMBOL(set_pages_wb);
1231
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001232int set_pages_array_wb(struct page **pages, int addrinarray)
1233{
1234 int retval;
1235 unsigned long start;
1236 unsigned long end;
1237 int i;
1238
1239 retval = cpa_clear_pages_array(pages, addrinarray,
1240 __pgprot(_PAGE_CACHE_MASK));
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001241 if (retval)
1242 return retval;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001243
1244 for (i = 0; i < addrinarray; i++) {
Thomas Hellstrom8523acf2009-08-03 09:25:45 +02001245 if (PageHighMem(pages[i]))
1246 continue;
1247 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001248 end = start + PAGE_SIZE;
1249 free_memtype(start, end);
1250 }
1251
venkatesh.pallipadi@intel.com9fa3ab32009-04-09 14:26:49 -07001252 return 0;
venkatesh.pallipadi@intel.com0f350752009-03-19 14:51:15 -07001253}
1254EXPORT_SYMBOL(set_pages_array_wb);
1255
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001256int set_pages_x(struct page *page, int numpages)
1257{
1258 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001259
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001260 return set_memory_x(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001261}
1262EXPORT_SYMBOL(set_pages_x);
1263
1264int set_pages_nx(struct page *page, int numpages)
1265{
1266 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001267
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001268 return set_memory_nx(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001269}
1270EXPORT_SYMBOL(set_pages_nx);
1271
1272int set_pages_ro(struct page *page, int numpages)
1273{
1274 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001275
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001276 return set_memory_ro(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001277}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001278
1279int set_pages_rw(struct page *page, int numpages)
1280{
1281 unsigned long addr = (unsigned long)page_address(page);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001282
Thomas Gleixnerd7c8f212008-01-30 13:34:07 +01001283 return set_memory_rw(addr, numpages);
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001284}
Arjan van de Ven75cbade2008-01-30 13:34:06 +01001285
Linus Torvalds1da177e2005-04-16 15:20:36 -07001286#ifdef CONFIG_DEBUG_PAGEALLOC
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001287
1288static int __set_pages_p(struct page *page, int numpages)
1289{
Shaohua Lid75586a2008-08-21 10:46:06 +08001290 unsigned long tempaddr = (unsigned long) page_address(page);
1291 struct cpa_data cpa = { .vaddr = &tempaddr,
Thomas Gleixner72e458d2008-02-04 16:48:07 +01001292 .numpages = numpages,
1293 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
Shaohua Lid75586a2008-08-21 10:46:06 +08001294 .mask_clr = __pgprot(0),
1295 .flags = 0};
Thomas Gleixner72932c72008-01-30 13:34:08 +01001296
Suresh Siddha55121b42008-09-23 14:00:40 -07001297 /*
1298 * No alias checking needed for setting present flag. otherwise,
1299 * we may need to break large pages for 64-bit kernel text
1300 * mappings (this adds to complexity if we want to do this from
1301 * atomic context especially). Let's keep it simple!
1302 */
1303 return __change_page_attr_set_clr(&cpa, 0);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001304}
1305
1306static int __set_pages_np(struct page *page, int numpages)
1307{
Shaohua Lid75586a2008-08-21 10:46:06 +08001308 unsigned long tempaddr = (unsigned long) page_address(page);
1309 struct cpa_data cpa = { .vaddr = &tempaddr,
Thomas Gleixner72e458d2008-02-04 16:48:07 +01001310 .numpages = numpages,
1311 .mask_set = __pgprot(0),
Shaohua Lid75586a2008-08-21 10:46:06 +08001312 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1313 .flags = 0};
Thomas Gleixner72932c72008-01-30 13:34:08 +01001314
Suresh Siddha55121b42008-09-23 14:00:40 -07001315 /*
1316 * No alias checking needed for setting not present flag. otherwise,
1317 * we may need to break large pages for 64-bit kernel text
1318 * mappings (this adds to complexity if we want to do this from
1319 * atomic context especially). Let's keep it simple!
1320 */
1321 return __change_page_attr_set_clr(&cpa, 0);
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001322}
1323
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324void kernel_map_pages(struct page *page, int numpages, int enable)
1325{
1326 if (PageHighMem(page))
1327 return;
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001328 if (!enable) {
Ingo Molnarf9b84042006-06-27 02:54:49 -07001329 debug_check_no_locks_freed(page_address(page),
1330 numpages * PAGE_SIZE);
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001331 }
Ingo Molnarde5097c2006-01-09 15:59:21 -08001332
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001333 /*
Ingo Molnarf8d84062008-02-13 14:09:53 +01001334 * The return value is ignored as the calls cannot fail.
Suresh Siddha55121b42008-09-23 14:00:40 -07001335 * Large pages for identity mappings are not used at boot time
1336 * and hence no memory allocations during large page split.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 */
Ingo Molnarf62d0f02008-01-30 13:34:07 +01001338 if (enable)
1339 __set_pages_p(page, numpages);
1340 else
1341 __set_pages_np(page, numpages);
Ingo Molnar9f4c8152008-01-30 13:33:41 +01001342
1343 /*
Ingo Molnare4b71dc2008-01-30 13:34:04 +01001344 * We should perform an IPI and flush all tlbs,
1345 * but that can deadlock->flush only current cpu:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001346 */
1347 __flush_tlb_all();
1348}
Rafael J. Wysocki8a235ef2008-02-20 01:47:44 +01001349
1350#ifdef CONFIG_HIBERNATION
1351
1352bool kernel_page_present(struct page *page)
1353{
1354 unsigned int level;
1355 pte_t *pte;
1356
1357 if (PageHighMem(page))
1358 return false;
1359
1360 pte = lookup_address((unsigned long)page_address(page), &level);
1361 return (pte_val(*pte) & _PAGE_PRESENT);
1362}
1363
1364#endif /* CONFIG_HIBERNATION */
1365
1366#endif /* CONFIG_DEBUG_PAGEALLOC */
Arjan van de Vend1028a12008-01-30 13:34:07 +01001367
1368/*
1369 * The testcases use internal knowledge of the implementation that shouldn't
1370 * be exposed to the rest of the kernel. Include these directly here.
1371 */
1372#ifdef CONFIG_CPA_DEBUG
1373#include "pageattr-test.c"
1374#endif