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Joerg Roedelb6c02712008-06-26 21:27:53 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedelb6c02712008-06-26 21:27:53 +02003 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010020#include <linux/ratelimit.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020021#include <linux/pci.h>
Joerg Roedelcb41ed82011-04-05 11:00:53 +020022#include <linux/pci-ats.h>
Akinobu Mitaa66022c2009-12-15 16:48:28 -080023#include <linux/bitmap.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Joerg Roedel7f265082008-12-12 13:50:21 +010025#include <linux/debugfs.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020026#include <linux/scatterlist.h>
FUJITA Tomonori51491362009-01-05 23:47:25 +090027#include <linux/dma-mapping.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020028#include <linux/iommu-helper.h>
Joerg Roedelc156e342008-12-02 18:13:27 +010029#include <linux/iommu.h>
Joerg Roedel815b33f2011-04-06 17:26:49 +020030#include <linux/delay.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020031#include <linux/amd-iommu.h>
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010032#include <linux/notifier.h>
33#include <linux/export.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020034#include <linux/irq.h>
35#include <linux/msi.h>
36#include <asm/irq_remapping.h>
37#include <asm/io_apic.h>
38#include <asm/apic.h>
39#include <asm/hw_irq.h>
Joerg Roedel17f5b562011-07-06 17:14:44 +020040#include <asm/msidef.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020041#include <asm/proto.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090042#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010043#include <asm/gart.h>
Joerg Roedel27c21272011-05-30 15:56:24 +020044#include <asm/dma.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020045
46#include "amd_iommu_proto.h"
47#include "amd_iommu_types.h"
Joerg Roedel6b474b82012-06-26 16:46:04 +020048#include "irq_remapping.h"
Joerg Roedelb6c02712008-06-26 21:27:53 +020049
50#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51
Joerg Roedel815b33f2011-04-06 17:26:49 +020052#define LOOP_TIMEOUT 100000
Joerg Roedel136f78a2008-07-11 17:14:27 +020053
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020054/*
55 * This bitmap is used to advertise the page sizes our hardware support
56 * to the IOMMU core, which will then use this information to split
57 * physically contiguous memory regions it is mapping into page sizes
58 * that we support.
59 *
60 * Traditionally the IOMMU core just handed us the mappings directly,
61 * after making sure the size is an order of a 4KiB page and that the
62 * mapping has natural alignment.
63 *
64 * To retain this behavior, we currently advertise that we support
65 * all page sizes that are an order of 4KiB.
66 *
67 * If at some point we'd like to utilize the IOMMU core's new behavior,
68 * we could change this to advertise the real page sizes we support.
69 */
70#define AMD_IOMMU_PGSIZES (~0xFFFUL)
71
Joerg Roedelb6c02712008-06-26 21:27:53 +020072static DEFINE_RWLOCK(amd_iommu_devtable_lock);
73
Joerg Roedelbd60b732008-09-11 10:24:48 +020074/* A list of preallocated protection domains */
75static LIST_HEAD(iommu_pd_list);
76static DEFINE_SPINLOCK(iommu_pd_list_lock);
77
Joerg Roedel8fa5f802011-06-09 12:24:45 +020078/* List of all available dev_data structures */
79static LIST_HEAD(dev_data_list);
80static DEFINE_SPINLOCK(dev_data_list_lock);
81
Joerg Roedel6efed632012-06-14 15:52:58 +020082LIST_HEAD(ioapic_map);
83LIST_HEAD(hpet_map);
84
Joerg Roedel0feae532009-08-26 15:26:30 +020085/*
86 * Domain for untranslated devices - only allocated
87 * if iommu=pt passed on kernel cmd line.
88 */
89static struct protection_domain *pt_domain;
90
Joerg Roedel26961ef2008-12-03 17:00:17 +010091static struct iommu_ops amd_iommu_ops;
Joerg Roedel26961ef2008-12-03 17:00:17 +010092
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010093static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
Joerg Roedel52815b72011-11-17 17:24:28 +010094int amd_iommu_max_glx_val = -1;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010095
Joerg Roedelac1534a2012-06-21 14:52:40 +020096static struct dma_map_ops amd_iommu_dma_ops;
97
Joerg Roedel431b2a22008-07-11 17:14:22 +020098/*
99 * general struct to manage commands send to an IOMMU
100 */
Joerg Roedeld6449532008-07-11 17:14:28 +0200101struct iommu_cmd {
Joerg Roedelb6c02712008-06-26 21:27:53 +0200102 u32 data[4];
103};
104
Joerg Roedel05152a02012-06-15 16:53:51 +0200105struct kmem_cache *amd_iommu_irq_cache;
106
Joerg Roedel04bfdd82009-09-02 16:00:23 +0200107static void update_domain(struct protection_domain *domain);
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100108static int __init alloc_passthrough_domain(void);
Chris Wrightc1eee672009-05-21 00:56:58 -0700109
Joerg Roedel15898bb2009-11-24 15:39:42 +0100110/****************************************************************************
111 *
112 * Helper functions
113 *
114 ****************************************************************************/
115
Joerg Roedelf62dda62011-06-09 12:55:35 +0200116static struct iommu_dev_data *alloc_dev_data(u16 devid)
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200117{
118 struct iommu_dev_data *dev_data;
119 unsigned long flags;
120
121 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
122 if (!dev_data)
123 return NULL;
124
Joerg Roedelf62dda62011-06-09 12:55:35 +0200125 dev_data->devid = devid;
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200126 atomic_set(&dev_data->bind, 0);
127
128 spin_lock_irqsave(&dev_data_list_lock, flags);
129 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
130 spin_unlock_irqrestore(&dev_data_list_lock, flags);
131
132 return dev_data;
133}
134
135static void free_dev_data(struct iommu_dev_data *dev_data)
136{
137 unsigned long flags;
138
139 spin_lock_irqsave(&dev_data_list_lock, flags);
140 list_del(&dev_data->dev_data_list);
141 spin_unlock_irqrestore(&dev_data_list_lock, flags);
142
143 kfree(dev_data);
144}
145
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200146static struct iommu_dev_data *search_dev_data(u16 devid)
147{
148 struct iommu_dev_data *dev_data;
149 unsigned long flags;
150
151 spin_lock_irqsave(&dev_data_list_lock, flags);
152 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
153 if (dev_data->devid == devid)
154 goto out_unlock;
155 }
156
157 dev_data = NULL;
158
159out_unlock:
160 spin_unlock_irqrestore(&dev_data_list_lock, flags);
161
162 return dev_data;
163}
164
165static struct iommu_dev_data *find_dev_data(u16 devid)
166{
167 struct iommu_dev_data *dev_data;
168
169 dev_data = search_dev_data(devid);
170
171 if (dev_data == NULL)
172 dev_data = alloc_dev_data(devid);
173
174 return dev_data;
175}
176
Joerg Roedel15898bb2009-11-24 15:39:42 +0100177static inline u16 get_device_id(struct device *dev)
178{
179 struct pci_dev *pdev = to_pci_dev(dev);
180
181 return calc_devid(pdev->bus->number, pdev->devfn);
182}
183
Joerg Roedel657cbb62009-11-23 15:26:46 +0100184static struct iommu_dev_data *get_dev_data(struct device *dev)
185{
186 return dev->archdata.iommu;
187}
188
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100189static bool pci_iommuv2_capable(struct pci_dev *pdev)
190{
191 static const int caps[] = {
192 PCI_EXT_CAP_ID_ATS,
Joerg Roedel46277b72011-12-07 14:34:02 +0100193 PCI_EXT_CAP_ID_PRI,
194 PCI_EXT_CAP_ID_PASID,
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100195 };
196 int i, pos;
197
198 for (i = 0; i < 3; ++i) {
199 pos = pci_find_ext_capability(pdev, caps[i]);
200 if (pos == 0)
201 return false;
202 }
203
204 return true;
205}
206
Joerg Roedel6a113dd2011-12-01 12:04:58 +0100207static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
208{
209 struct iommu_dev_data *dev_data;
210
211 dev_data = get_dev_data(&pdev->dev);
212
213 return dev_data->errata & (1 << erratum) ? true : false;
214}
215
Joerg Roedel71c70982009-11-24 16:43:06 +0100216/*
217 * In this function the list of preallocated protection domains is traversed to
218 * find the domain for a specific device
219 */
220static struct dma_ops_domain *find_protection_domain(u16 devid)
221{
222 struct dma_ops_domain *entry, *ret = NULL;
223 unsigned long flags;
224 u16 alias = amd_iommu_alias_table[devid];
225
226 if (list_empty(&iommu_pd_list))
227 return NULL;
228
229 spin_lock_irqsave(&iommu_pd_list_lock, flags);
230
231 list_for_each_entry(entry, &iommu_pd_list, list) {
232 if (entry->target_dev == devid ||
233 entry->target_dev == alias) {
234 ret = entry;
235 break;
236 }
237 }
238
239 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
240
241 return ret;
242}
243
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100244/*
245 * This function checks if the driver got a valid device from the caller to
246 * avoid dereferencing invalid pointers.
247 */
248static bool check_device(struct device *dev)
249{
250 u16 devid;
251
252 if (!dev || !dev->dma_mask)
253 return false;
254
255 /* No device or no PCI device */
Julia Lawall339d3262010-02-06 09:42:39 +0100256 if (dev->bus != &pci_bus_type)
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100257 return false;
258
259 devid = get_device_id(dev);
260
261 /* Out of our scope? */
262 if (devid > amd_iommu_last_bdf)
263 return false;
264
265 if (amd_iommu_rlookup_table[devid] == NULL)
266 return false;
267
268 return true;
269}
270
Alex Williamson664b6002012-05-30 14:19:31 -0600271static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
272{
273 pci_dev_put(*from);
274 *from = to;
275}
276
Alex Williamson2bff6a52012-10-08 22:49:48 -0600277static struct pci_bus *find_hosted_bus(struct pci_bus *bus)
278{
279 while (!bus->self) {
280 if (!pci_is_root_bus(bus))
281 bus = bus->parent;
282 else
283 return ERR_PTR(-ENODEV);
284 }
285
286 return bus;
287}
288
Alex Williamson664b6002012-05-30 14:19:31 -0600289#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
290
Alex Williamson2851db22012-10-08 22:49:41 -0600291static struct pci_dev *get_isolation_root(struct pci_dev *pdev)
Joerg Roedel657cbb62009-11-23 15:26:46 +0100292{
Alex Williamson2851db22012-10-08 22:49:41 -0600293 struct pci_dev *dma_pdev = pdev;
Alex Williamson9dcd6132012-05-30 14:19:07 -0600294
Alex Williamson31fe9432012-08-04 12:09:03 -0600295 /* Account for quirked devices */
Alex Williamson664b6002012-05-30 14:19:31 -0600296 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
297
Alex Williamson31fe9432012-08-04 12:09:03 -0600298 /*
299 * If it's a multifunction device that does not support our
300 * required ACS flags, add to the same group as function 0.
301 */
Alex Williamson664b6002012-05-30 14:19:31 -0600302 if (dma_pdev->multifunction &&
303 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
304 swap_pci_ref(&dma_pdev,
305 pci_get_slot(dma_pdev->bus,
306 PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
307 0)));
308
Alex Williamson31fe9432012-08-04 12:09:03 -0600309 /*
310 * Devices on the root bus go through the iommu. If that's not us,
311 * find the next upstream device and test ACS up to the root bus.
312 * Finding the next device may require skipping virtual buses.
313 */
Alex Williamson664b6002012-05-30 14:19:31 -0600314 while (!pci_is_root_bus(dma_pdev->bus)) {
Alex Williamson2bff6a52012-10-08 22:49:48 -0600315 struct pci_bus *bus = find_hosted_bus(dma_pdev->bus);
316 if (IS_ERR(bus))
317 break;
Alex Williamson31fe9432012-08-04 12:09:03 -0600318
319 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
Alex Williamson664b6002012-05-30 14:19:31 -0600320 break;
321
Alex Williamson31fe9432012-08-04 12:09:03 -0600322 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
Joerg Roedel26018872011-06-06 16:50:14 +0200323 }
Joerg Roedel657cbb62009-11-23 15:26:46 +0100324
Alex Williamson2851db22012-10-08 22:49:41 -0600325 return dma_pdev;
326}
327
328static int init_iommu_group(struct device *dev)
329{
330 struct iommu_dev_data *dev_data;
331 struct iommu_group *group;
332 struct pci_dev *dma_pdev = NULL;
333 int ret;
334
335 group = iommu_group_get(dev);
336 if (group) {
337 iommu_group_put(group);
338 return 0;
339 }
340
341 dev_data = find_dev_data(get_device_id(dev));
342 if (!dev_data)
343 return -ENOMEM;
344
345 if (dev_data->alias_data) {
346 u16 alias;
347
348 alias = amd_iommu_alias_table[dev_data->devid];
349 dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff);
350 }
351
352 if (!dma_pdev)
353 dma_pdev = pci_dev_get(to_pci_dev(dev));
354
355 dma_pdev = get_isolation_root(dma_pdev);
Alex Williamson9dcd6132012-05-30 14:19:07 -0600356 group = iommu_group_get(&dma_pdev->dev);
357 pci_dev_put(dma_pdev);
358 if (!group) {
359 group = iommu_group_alloc();
360 if (IS_ERR(group))
361 return PTR_ERR(group);
Joerg Roedel657cbb62009-11-23 15:26:46 +0100362 }
363
Alex Williamson9dcd6132012-05-30 14:19:07 -0600364 ret = iommu_group_add_device(group, dev);
365
366 iommu_group_put(group);
367
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600368 return ret;
369}
370
371static int iommu_init_device(struct device *dev)
372{
373 struct pci_dev *pdev = to_pci_dev(dev);
374 struct iommu_dev_data *dev_data;
375 u16 alias;
376 int ret;
377
378 if (dev->archdata.iommu)
379 return 0;
380
381 dev_data = find_dev_data(get_device_id(dev));
382 if (!dev_data)
383 return -ENOMEM;
384
385 alias = amd_iommu_alias_table[dev_data->devid];
386 if (alias != dev_data->devid) {
387 struct iommu_dev_data *alias_data;
388
389 alias_data = find_dev_data(alias);
390 if (alias_data == NULL) {
391 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
392 dev_name(dev));
393 free_dev_data(dev_data);
394 return -ENOTSUPP;
395 }
396 dev_data->alias_data = alias_data;
397 }
398
399 ret = init_iommu_group(dev);
Alex Williamson9dcd6132012-05-30 14:19:07 -0600400 if (ret)
401 return ret;
402
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100403 if (pci_iommuv2_capable(pdev)) {
404 struct amd_iommu *iommu;
405
406 iommu = amd_iommu_rlookup_table[dev_data->devid];
407 dev_data->iommu_v2 = iommu->is_iommu_v2;
408 }
409
Joerg Roedel657cbb62009-11-23 15:26:46 +0100410 dev->archdata.iommu = dev_data;
411
Joerg Roedel657cbb62009-11-23 15:26:46 +0100412 return 0;
413}
414
Joerg Roedel26018872011-06-06 16:50:14 +0200415static void iommu_ignore_device(struct device *dev)
416{
417 u16 devid, alias;
418
419 devid = get_device_id(dev);
420 alias = amd_iommu_alias_table[devid];
421
422 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
423 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
424
425 amd_iommu_rlookup_table[devid] = NULL;
426 amd_iommu_rlookup_table[alias] = NULL;
427}
428
Joerg Roedel657cbb62009-11-23 15:26:46 +0100429static void iommu_uninit_device(struct device *dev)
430{
Alex Williamson9dcd6132012-05-30 14:19:07 -0600431 iommu_group_remove_device(dev);
432
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200433 /*
434 * Nothing to do here - we keep dev_data around for unplugged devices
435 * and reuse it when the device is re-plugged - not doing so would
436 * introduce a ton of races.
437 */
Joerg Roedel657cbb62009-11-23 15:26:46 +0100438}
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100439
440void __init amd_iommu_uninit_devices(void)
441{
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200442 struct iommu_dev_data *dev_data, *n;
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100443 struct pci_dev *pdev = NULL;
444
445 for_each_pci_dev(pdev) {
446
447 if (!check_device(&pdev->dev))
448 continue;
449
450 iommu_uninit_device(&pdev->dev);
451 }
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200452
453 /* Free all of our dev_data structures */
454 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
455 free_dev_data(dev_data);
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100456}
457
458int __init amd_iommu_init_devices(void)
459{
460 struct pci_dev *pdev = NULL;
461 int ret = 0;
462
463 for_each_pci_dev(pdev) {
464
465 if (!check_device(&pdev->dev))
466 continue;
467
468 ret = iommu_init_device(&pdev->dev);
Joerg Roedel26018872011-06-06 16:50:14 +0200469 if (ret == -ENOTSUPP)
470 iommu_ignore_device(&pdev->dev);
471 else if (ret)
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100472 goto out_free;
473 }
474
475 return 0;
476
477out_free:
478
479 amd_iommu_uninit_devices();
480
481 return ret;
482}
Joerg Roedel7f265082008-12-12 13:50:21 +0100483#ifdef CONFIG_AMD_IOMMU_STATS
484
485/*
486 * Initialization code for statistics collection
487 */
488
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100489DECLARE_STATS_COUNTER(compl_wait);
Joerg Roedel0f2a86f2008-12-12 15:05:16 +0100490DECLARE_STATS_COUNTER(cnt_map_single);
Joerg Roedel146a6912008-12-12 15:07:12 +0100491DECLARE_STATS_COUNTER(cnt_unmap_single);
Joerg Roedeld03f0672008-12-12 15:09:48 +0100492DECLARE_STATS_COUNTER(cnt_map_sg);
Joerg Roedel55877a62008-12-12 15:12:14 +0100493DECLARE_STATS_COUNTER(cnt_unmap_sg);
Joerg Roedelc8f0fb32008-12-12 15:14:21 +0100494DECLARE_STATS_COUNTER(cnt_alloc_coherent);
Joerg Roedel5d31ee72008-12-12 15:16:38 +0100495DECLARE_STATS_COUNTER(cnt_free_coherent);
Joerg Roedelc1858972008-12-12 15:42:39 +0100496DECLARE_STATS_COUNTER(cross_page);
Joerg Roedelf57d98a2008-12-12 15:46:29 +0100497DECLARE_STATS_COUNTER(domain_flush_single);
Joerg Roedel18811f52008-12-12 15:48:28 +0100498DECLARE_STATS_COUNTER(domain_flush_all);
Joerg Roedel5774f7c2008-12-12 15:57:30 +0100499DECLARE_STATS_COUNTER(alloced_io_mem);
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +0100500DECLARE_STATS_COUNTER(total_map_requests);
Joerg Roedel399be2f2011-12-01 16:53:47 +0100501DECLARE_STATS_COUNTER(complete_ppr);
502DECLARE_STATS_COUNTER(invalidate_iotlb);
503DECLARE_STATS_COUNTER(invalidate_iotlb_all);
504DECLARE_STATS_COUNTER(pri_requests);
505
Joerg Roedel7f265082008-12-12 13:50:21 +0100506static struct dentry *stats_dir;
Joerg Roedel7f265082008-12-12 13:50:21 +0100507static struct dentry *de_fflush;
508
509static void amd_iommu_stats_add(struct __iommu_counter *cnt)
510{
511 if (stats_dir == NULL)
512 return;
513
514 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
515 &cnt->value);
516}
517
518static void amd_iommu_stats_init(void)
519{
520 stats_dir = debugfs_create_dir("amd-iommu", NULL);
521 if (stats_dir == NULL)
522 return;
523
Joerg Roedel7f265082008-12-12 13:50:21 +0100524 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
Dan Carpenter3775d482012-06-27 12:09:18 +0300525 &amd_iommu_unmap_flush);
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100526
527 amd_iommu_stats_add(&compl_wait);
Joerg Roedel0f2a86f2008-12-12 15:05:16 +0100528 amd_iommu_stats_add(&cnt_map_single);
Joerg Roedel146a6912008-12-12 15:07:12 +0100529 amd_iommu_stats_add(&cnt_unmap_single);
Joerg Roedeld03f0672008-12-12 15:09:48 +0100530 amd_iommu_stats_add(&cnt_map_sg);
Joerg Roedel55877a62008-12-12 15:12:14 +0100531 amd_iommu_stats_add(&cnt_unmap_sg);
Joerg Roedelc8f0fb32008-12-12 15:14:21 +0100532 amd_iommu_stats_add(&cnt_alloc_coherent);
Joerg Roedel5d31ee72008-12-12 15:16:38 +0100533 amd_iommu_stats_add(&cnt_free_coherent);
Joerg Roedelc1858972008-12-12 15:42:39 +0100534 amd_iommu_stats_add(&cross_page);
Joerg Roedelf57d98a2008-12-12 15:46:29 +0100535 amd_iommu_stats_add(&domain_flush_single);
Joerg Roedel18811f52008-12-12 15:48:28 +0100536 amd_iommu_stats_add(&domain_flush_all);
Joerg Roedel5774f7c2008-12-12 15:57:30 +0100537 amd_iommu_stats_add(&alloced_io_mem);
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +0100538 amd_iommu_stats_add(&total_map_requests);
Joerg Roedel399be2f2011-12-01 16:53:47 +0100539 amd_iommu_stats_add(&complete_ppr);
540 amd_iommu_stats_add(&invalidate_iotlb);
541 amd_iommu_stats_add(&invalidate_iotlb_all);
542 amd_iommu_stats_add(&pri_requests);
Joerg Roedel7f265082008-12-12 13:50:21 +0100543}
544
545#endif
546
Joerg Roedel431b2a22008-07-11 17:14:22 +0200547/****************************************************************************
548 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200549 * Interrupt handling functions
550 *
551 ****************************************************************************/
552
Joerg Roedele3e59872009-09-03 14:02:10 +0200553static void dump_dte_entry(u16 devid)
554{
555 int i;
556
Joerg Roedelee6c2862011-11-09 12:06:03 +0100557 for (i = 0; i < 4; ++i)
558 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
Joerg Roedele3e59872009-09-03 14:02:10 +0200559 amd_iommu_dev_table[devid].data[i]);
560}
561
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200562static void dump_command(unsigned long phys_addr)
563{
564 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
565 int i;
566
567 for (i = 0; i < 4; ++i)
568 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
569}
570
Joerg Roedela345b232009-09-03 15:01:43 +0200571static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
Joerg Roedel90008ee2008-09-09 16:41:05 +0200572{
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200573 int type, devid, domid, flags;
574 volatile u32 *event = __evt;
575 int count = 0;
576 u64 address;
577
578retry:
579 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
580 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
581 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
582 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
583 address = (u64)(((u64)event[3]) << 32) | event[2];
584
585 if (type == 0) {
586 /* Did we hit the erratum? */
587 if (++count == LOOP_TIMEOUT) {
588 pr_err("AMD-Vi: No event written to event log\n");
589 return;
590 }
591 udelay(1);
592 goto retry;
593 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200594
Joerg Roedel4c6f40d2009-09-01 16:43:58 +0200595 printk(KERN_ERR "AMD-Vi: Event logged [");
Joerg Roedel90008ee2008-09-09 16:41:05 +0200596
597 switch (type) {
598 case EVENT_TYPE_ILL_DEV:
599 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
600 "address=0x%016llx flags=0x%04x]\n",
601 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
602 address, flags);
Joerg Roedele3e59872009-09-03 14:02:10 +0200603 dump_dte_entry(devid);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200604 break;
605 case EVENT_TYPE_IO_FAULT:
606 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
607 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
608 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
609 domid, address, flags);
610 break;
611 case EVENT_TYPE_DEV_TAB_ERR:
612 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
613 "address=0x%016llx flags=0x%04x]\n",
614 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
615 address, flags);
616 break;
617 case EVENT_TYPE_PAGE_TAB_ERR:
618 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
619 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 domid, address, flags);
622 break;
623 case EVENT_TYPE_ILL_CMD:
624 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200625 dump_command(address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200626 break;
627 case EVENT_TYPE_CMD_HARD_ERR:
628 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
629 "flags=0x%04x]\n", address, flags);
630 break;
631 case EVENT_TYPE_IOTLB_INV_TO:
632 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
633 "address=0x%016llx]\n",
634 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
635 address);
636 break;
637 case EVENT_TYPE_INV_DEV_REQ:
638 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
639 "address=0x%016llx flags=0x%04x]\n",
640 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
641 address, flags);
642 break;
643 default:
644 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
645 }
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200646
647 memset(__evt, 0, 4 * sizeof(u32));
Joerg Roedel90008ee2008-09-09 16:41:05 +0200648}
649
650static void iommu_poll_events(struct amd_iommu *iommu)
651{
652 u32 head, tail;
653 unsigned long flags;
654
655 spin_lock_irqsave(&iommu->lock, flags);
656
657 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
658 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
659
660 while (head != tail) {
Joerg Roedela345b232009-09-03 15:01:43 +0200661 iommu_print_event(iommu, iommu->evt_buf + head);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200662 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
663 }
664
665 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
666
667 spin_unlock_irqrestore(&iommu->lock, flags);
668}
669
Joerg Roedeleee53532012-06-01 15:20:23 +0200670static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100671{
672 struct amd_iommu_fault fault;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100673
Joerg Roedel399be2f2011-12-01 16:53:47 +0100674 INC_STATS_COUNTER(pri_requests);
675
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100676 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
677 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
678 return;
679 }
680
681 fault.address = raw[1];
682 fault.pasid = PPR_PASID(raw[0]);
683 fault.device_id = PPR_DEVID(raw[0]);
684 fault.tag = PPR_TAG(raw[0]);
685 fault.flags = PPR_FLAGS(raw[0]);
686
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100687 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
688}
689
690static void iommu_poll_ppr_log(struct amd_iommu *iommu)
691{
692 unsigned long flags;
693 u32 head, tail;
694
695 if (iommu->ppr_log == NULL)
696 return;
697
Joerg Roedeleee53532012-06-01 15:20:23 +0200698 /* enable ppr interrupts again */
699 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
700
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100701 spin_lock_irqsave(&iommu->lock, flags);
702
703 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
704 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
705
706 while (head != tail) {
Joerg Roedeleee53532012-06-01 15:20:23 +0200707 volatile u64 *raw;
708 u64 entry[2];
709 int i;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100710
Joerg Roedeleee53532012-06-01 15:20:23 +0200711 raw = (u64 *)(iommu->ppr_log + head);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100712
Joerg Roedeleee53532012-06-01 15:20:23 +0200713 /*
714 * Hardware bug: Interrupt may arrive before the entry is
715 * written to memory. If this happens we need to wait for the
716 * entry to arrive.
717 */
718 for (i = 0; i < LOOP_TIMEOUT; ++i) {
719 if (PPR_REQ_TYPE(raw[0]) != 0)
720 break;
721 udelay(1);
722 }
723
724 /* Avoid memcpy function-call overhead */
725 entry[0] = raw[0];
726 entry[1] = raw[1];
727
728 /*
729 * To detect the hardware bug we need to clear the entry
730 * back to zero.
731 */
732 raw[0] = raw[1] = 0UL;
733
734 /* Update head pointer of hardware ring-buffer */
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100735 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
736 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedeleee53532012-06-01 15:20:23 +0200737
738 /*
739 * Release iommu->lock because ppr-handling might need to
Frank Arnolddf805ab2012-08-27 19:21:04 +0200740 * re-acquire it
Joerg Roedeleee53532012-06-01 15:20:23 +0200741 */
742 spin_unlock_irqrestore(&iommu->lock, flags);
743
744 /* Handle PPR entry */
745 iommu_handle_ppr_entry(iommu, entry);
746
747 spin_lock_irqsave(&iommu->lock, flags);
748
749 /* Refresh ring-buffer information */
750 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100751 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
752 }
753
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100754 spin_unlock_irqrestore(&iommu->lock, flags);
755}
756
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200757irqreturn_t amd_iommu_int_thread(int irq, void *data)
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200758{
Joerg Roedel90008ee2008-09-09 16:41:05 +0200759 struct amd_iommu *iommu;
760
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100761 for_each_iommu(iommu) {
Joerg Roedel90008ee2008-09-09 16:41:05 +0200762 iommu_poll_events(iommu);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100763 iommu_poll_ppr_log(iommu);
764 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200765
766 return IRQ_HANDLED;
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200767}
768
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200769irqreturn_t amd_iommu_int_handler(int irq, void *data)
770{
771 return IRQ_WAKE_THREAD;
772}
773
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200774/****************************************************************************
775 *
Joerg Roedel431b2a22008-07-11 17:14:22 +0200776 * IOMMU command queuing functions
777 *
778 ****************************************************************************/
779
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200780static int wait_on_sem(volatile u64 *sem)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200781{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200782 int i = 0;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200783
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200784 while (*sem == 0 && i < LOOP_TIMEOUT) {
785 udelay(1);
786 i += 1;
787 }
788
789 if (i == LOOP_TIMEOUT) {
790 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
791 return -EIO;
792 }
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200793
794 return 0;
795}
796
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200797static void copy_cmd_to_buffer(struct amd_iommu *iommu,
798 struct iommu_cmd *cmd,
799 u32 tail)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200800{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200801 u8 *target;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200802
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200803 target = iommu->cmd_buf + tail;
804 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200805
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200806 /* Copy command to buffer */
807 memcpy(target, cmd, sizeof(*cmd));
808
809 /* Tell the IOMMU about it */
810 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
811}
812
Joerg Roedel815b33f2011-04-06 17:26:49 +0200813static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
Joerg Roedelded46732011-04-06 10:53:48 +0200814{
Joerg Roedel815b33f2011-04-06 17:26:49 +0200815 WARN_ON(address & 0x7ULL);
816
Joerg Roedelded46732011-04-06 10:53:48 +0200817 memset(cmd, 0, sizeof(*cmd));
Joerg Roedel815b33f2011-04-06 17:26:49 +0200818 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
819 cmd->data[1] = upper_32_bits(__pa(address));
820 cmd->data[2] = 1;
Joerg Roedelded46732011-04-06 10:53:48 +0200821 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
822}
823
Joerg Roedel94fe79e2011-04-06 11:07:21 +0200824static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
825{
826 memset(cmd, 0, sizeof(*cmd));
827 cmd->data[0] = devid;
828 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
829}
830
Joerg Roedel11b64022011-04-06 11:49:28 +0200831static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
832 size_t size, u16 domid, int pde)
833{
834 u64 pages;
835 int s;
836
837 pages = iommu_num_pages(address, size, PAGE_SIZE);
838 s = 0;
839
840 if (pages > 1) {
841 /*
842 * If we have to flush more than one page, flush all
843 * TLB entries for this domain
844 */
845 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
846 s = 1;
847 }
848
849 address &= PAGE_MASK;
850
851 memset(cmd, 0, sizeof(*cmd));
852 cmd->data[1] |= domid;
853 cmd->data[2] = lower_32_bits(address);
854 cmd->data[3] = upper_32_bits(address);
855 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
856 if (s) /* size bit - we flush more than one 4kb page */
857 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
Frank Arnolddf805ab2012-08-27 19:21:04 +0200858 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
Joerg Roedel11b64022011-04-06 11:49:28 +0200859 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
860}
861
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200862static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
863 u64 address, size_t size)
864{
865 u64 pages;
866 int s;
867
868 pages = iommu_num_pages(address, size, PAGE_SIZE);
869 s = 0;
870
871 if (pages > 1) {
872 /*
873 * If we have to flush more than one page, flush all
874 * TLB entries for this domain
875 */
876 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
877 s = 1;
878 }
879
880 address &= PAGE_MASK;
881
882 memset(cmd, 0, sizeof(*cmd));
883 cmd->data[0] = devid;
884 cmd->data[0] |= (qdep & 0xff) << 24;
885 cmd->data[1] = devid;
886 cmd->data[2] = lower_32_bits(address);
887 cmd->data[3] = upper_32_bits(address);
888 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
889 if (s)
890 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
891}
892
Joerg Roedel22e266c2011-11-21 15:59:08 +0100893static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
894 u64 address, bool size)
895{
896 memset(cmd, 0, sizeof(*cmd));
897
898 address &= ~(0xfffULL);
899
900 cmd->data[0] = pasid & PASID_MASK;
901 cmd->data[1] = domid;
902 cmd->data[2] = lower_32_bits(address);
903 cmd->data[3] = upper_32_bits(address);
904 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
905 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
906 if (size)
907 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
908 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
909}
910
911static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
912 int qdep, u64 address, bool size)
913{
914 memset(cmd, 0, sizeof(*cmd));
915
916 address &= ~(0xfffULL);
917
918 cmd->data[0] = devid;
919 cmd->data[0] |= (pasid & 0xff) << 16;
920 cmd->data[0] |= (qdep & 0xff) << 24;
921 cmd->data[1] = devid;
922 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
923 cmd->data[2] = lower_32_bits(address);
924 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
925 cmd->data[3] = upper_32_bits(address);
926 if (size)
927 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
928 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
929}
930
Joerg Roedelc99afa22011-11-21 18:19:25 +0100931static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
932 int status, int tag, bool gn)
933{
934 memset(cmd, 0, sizeof(*cmd));
935
936 cmd->data[0] = devid;
937 if (gn) {
938 cmd->data[1] = pasid & PASID_MASK;
939 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
940 }
941 cmd->data[3] = tag & 0x1ff;
942 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
943
944 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
945}
946
Joerg Roedel58fc7f12011-04-11 11:13:24 +0200947static void build_inv_all(struct iommu_cmd *cmd)
948{
949 memset(cmd, 0, sizeof(*cmd));
950 CMD_SET_TYPE(cmd, CMD_INV_ALL);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200951}
952
Joerg Roedel7ef27982012-06-21 16:46:04 +0200953static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
954{
955 memset(cmd, 0, sizeof(*cmd));
956 cmd->data[0] = devid;
957 CMD_SET_TYPE(cmd, CMD_INV_IRT);
958}
959
Joerg Roedel431b2a22008-07-11 17:14:22 +0200960/*
Joerg Roedelb6c02712008-06-26 21:27:53 +0200961 * Writes the command to the IOMMUs command buffer and informs the
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200962 * hardware about the new command.
Joerg Roedel431b2a22008-07-11 17:14:22 +0200963 */
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200964static int iommu_queue_command_sync(struct amd_iommu *iommu,
965 struct iommu_cmd *cmd,
966 bool sync)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200967{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200968 u32 left, tail, head, next_tail;
Joerg Roedel815b33f2011-04-06 17:26:49 +0200969 unsigned long flags;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200970
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200971 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100972
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200973again:
Joerg Roedel815b33f2011-04-06 17:26:49 +0200974 spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200975
976 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
977 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
978 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
979 left = (head - next_tail) % iommu->cmd_buf_size;
980
981 if (left <= 2) {
982 struct iommu_cmd sync_cmd;
983 volatile u64 sem = 0;
984 int ret;
985
986 build_completion_wait(&sync_cmd, (u64)&sem);
987 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
988
989 spin_unlock_irqrestore(&iommu->lock, flags);
990
991 if ((ret = wait_on_sem(&sem)) != 0)
992 return ret;
993
994 goto again;
Joerg Roedel136f78a2008-07-11 17:14:27 +0200995 }
996
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200997 copy_cmd_to_buffer(iommu, cmd, tail);
Joerg Roedel519c31b2008-08-14 19:55:15 +0200998
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200999 /* We need to sync now to make sure all commands are processed */
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001000 iommu->need_sync = sync;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001001
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001002 spin_unlock_irqrestore(&iommu->lock, flags);
1003
Joerg Roedel815b33f2011-04-06 17:26:49 +02001004 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +01001005}
1006
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001007static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1008{
1009 return iommu_queue_command_sync(iommu, cmd, true);
1010}
1011
Joerg Roedel8d201962008-12-02 20:34:41 +01001012/*
1013 * This function queues a completion wait command into the command
1014 * buffer of an IOMMU
1015 */
Joerg Roedel8d201962008-12-02 20:34:41 +01001016static int iommu_completion_wait(struct amd_iommu *iommu)
1017{
Joerg Roedel815b33f2011-04-06 17:26:49 +02001018 struct iommu_cmd cmd;
1019 volatile u64 sem = 0;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001020 int ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001021
1022 if (!iommu->need_sync)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001023 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +01001024
Joerg Roedel815b33f2011-04-06 17:26:49 +02001025 build_completion_wait(&cmd, (u64)&sem);
Joerg Roedel8d201962008-12-02 20:34:41 +01001026
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001027 ret = iommu_queue_command_sync(iommu, &cmd, false);
Joerg Roedel8d201962008-12-02 20:34:41 +01001028 if (ret)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001029 return ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001030
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001031 return wait_on_sem(&sem);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001032}
1033
Joerg Roedeld8c13082011-04-06 18:51:26 +02001034static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001035{
1036 struct iommu_cmd cmd;
1037
Joerg Roedeld8c13082011-04-06 18:51:26 +02001038 build_inv_dte(&cmd, devid);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001039
Joerg Roedeld8c13082011-04-06 18:51:26 +02001040 return iommu_queue_command(iommu, &cmd);
1041}
1042
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001043static void iommu_flush_dte_all(struct amd_iommu *iommu)
1044{
1045 u32 devid;
1046
1047 for (devid = 0; devid <= 0xffff; ++devid)
1048 iommu_flush_dte(iommu, devid);
1049
1050 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001051}
1052
1053/*
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001054 * This function uses heavy locking and may disable irqs for some time. But
1055 * this is no issue because it is only called during resume.
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001056 */
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001057static void iommu_flush_tlb_all(struct amd_iommu *iommu)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001058{
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001059 u32 dom_id;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001060
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001061 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1062 struct iommu_cmd cmd;
1063 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1064 dom_id, 1);
1065 iommu_queue_command(iommu, &cmd);
1066 }
Joerg Roedel431b2a22008-07-11 17:14:22 +02001067
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001068 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001069}
1070
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001071static void iommu_flush_all(struct amd_iommu *iommu)
1072{
1073 struct iommu_cmd cmd;
1074
1075 build_inv_all(&cmd);
1076
1077 iommu_queue_command(iommu, &cmd);
1078 iommu_completion_wait(iommu);
1079}
1080
Joerg Roedel7ef27982012-06-21 16:46:04 +02001081static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1082{
1083 struct iommu_cmd cmd;
1084
1085 build_inv_irt(&cmd, devid);
1086
1087 iommu_queue_command(iommu, &cmd);
1088}
1089
1090static void iommu_flush_irt_all(struct amd_iommu *iommu)
1091{
1092 u32 devid;
1093
1094 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1095 iommu_flush_irt(iommu, devid);
1096
1097 iommu_completion_wait(iommu);
1098}
1099
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001100void iommu_flush_all_caches(struct amd_iommu *iommu)
1101{
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001102 if (iommu_feature(iommu, FEATURE_IA)) {
1103 iommu_flush_all(iommu);
1104 } else {
1105 iommu_flush_dte_all(iommu);
Joerg Roedel7ef27982012-06-21 16:46:04 +02001106 iommu_flush_irt_all(iommu);
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001107 iommu_flush_tlb_all(iommu);
1108 }
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001109}
1110
Joerg Roedel431b2a22008-07-11 17:14:22 +02001111/*
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001112 * Command send function for flushing on-device TLB
1113 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001114static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1115 u64 address, size_t size)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001116{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001117 struct amd_iommu *iommu;
1118 struct iommu_cmd cmd;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001119 int qdep;
1120
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001121 qdep = dev_data->ats.qdep;
1122 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001123
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001124 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001125
1126 return iommu_queue_command(iommu, &cmd);
1127}
1128
1129/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001130 * Command send function for invalidating a device table entry
1131 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001132static int device_flush_dte(struct iommu_dev_data *dev_data)
Joerg Roedel3fa43652009-11-26 15:04:38 +01001133{
1134 struct amd_iommu *iommu;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001135 int ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001136
Joerg Roedel6c542042011-06-09 17:07:31 +02001137 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel3fa43652009-11-26 15:04:38 +01001138
Joerg Roedelf62dda62011-06-09 12:55:35 +02001139 ret = iommu_flush_dte(iommu, dev_data->devid);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001140 if (ret)
1141 return ret;
1142
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001143 if (dev_data->ats.enabled)
Joerg Roedel6c542042011-06-09 17:07:31 +02001144 ret = device_flush_iotlb(dev_data, 0, ~0UL);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001145
1146 return ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001147}
1148
Joerg Roedel431b2a22008-07-11 17:14:22 +02001149/*
1150 * TLB invalidation function which is called from the mapping functions.
1151 * It invalidates a single PTE if the range to flush is within a single
1152 * page. Otherwise it flushes the whole TLB of the IOMMU.
1153 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001154static void __domain_flush_pages(struct protection_domain *domain,
1155 u64 address, size_t size, int pde)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001156{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001157 struct iommu_dev_data *dev_data;
Joerg Roedel11b64022011-04-06 11:49:28 +02001158 struct iommu_cmd cmd;
1159 int ret = 0, i;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001160
Joerg Roedel11b64022011-04-06 11:49:28 +02001161 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
Joerg Roedel999ba412008-07-03 19:35:08 +02001162
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001163 for (i = 0; i < amd_iommus_present; ++i) {
1164 if (!domain->dev_iommu[i])
1165 continue;
1166
1167 /*
1168 * Devices of this domain are behind this IOMMU
1169 * We need a TLB flush
1170 */
Joerg Roedel11b64022011-04-06 11:49:28 +02001171 ret |= iommu_queue_command(amd_iommus[i], &cmd);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001172 }
1173
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001174 list_for_each_entry(dev_data, &domain->dev_list, list) {
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001175
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001176 if (!dev_data->ats.enabled)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001177 continue;
1178
Joerg Roedel6c542042011-06-09 17:07:31 +02001179 ret |= device_flush_iotlb(dev_data, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001180 }
1181
Joerg Roedel11b64022011-04-06 11:49:28 +02001182 WARN_ON(ret);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001183}
1184
Joerg Roedel17b124b2011-04-06 18:01:35 +02001185static void domain_flush_pages(struct protection_domain *domain,
1186 u64 address, size_t size)
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001187{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001188 __domain_flush_pages(domain, address, size, 0);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001189}
Joerg Roedelb6c02712008-06-26 21:27:53 +02001190
Joerg Roedel1c655772008-09-04 18:40:05 +02001191/* Flush the whole IO/TLB for a given protection domain */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001192static void domain_flush_tlb(struct protection_domain *domain)
Joerg Roedel1c655772008-09-04 18:40:05 +02001193{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001194 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001195}
1196
Chris Wright42a49f92009-06-15 15:42:00 +02001197/* Flush the whole IO/TLB for a given protection domain - including PDE */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001198static void domain_flush_tlb_pde(struct protection_domain *domain)
Chris Wright42a49f92009-06-15 15:42:00 +02001199{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001200 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1201}
1202
1203static void domain_flush_complete(struct protection_domain *domain)
Joerg Roedelb6c02712008-06-26 21:27:53 +02001204{
1205 int i;
1206
1207 for (i = 0; i < amd_iommus_present; ++i) {
1208 if (!domain->dev_iommu[i])
1209 continue;
1210
1211 /*
1212 * Devices of this domain are behind this IOMMU
1213 * We need to wait for completion of all commands.
1214 */
1215 iommu_completion_wait(amd_iommus[i]);
1216 }
1217}
1218
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001219
Joerg Roedel43f49602008-12-02 21:01:12 +01001220/*
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001221 * This function flushes the DTEs for all devices in domain
Joerg Roedel43f49602008-12-02 21:01:12 +01001222 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001223static void domain_flush_devices(struct protection_domain *domain)
Joerg Roedelbfd1be12009-05-05 15:33:57 +02001224{
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001225 struct iommu_dev_data *dev_data;
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001226
1227 list_for_each_entry(dev_data, &domain->dev_list, list)
Joerg Roedel6c542042011-06-09 17:07:31 +02001228 device_flush_dte(dev_data);
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001229}
1230
Joerg Roedel431b2a22008-07-11 17:14:22 +02001231/****************************************************************************
1232 *
1233 * The functions below are used the create the page table mappings for
1234 * unity mapped regions.
1235 *
1236 ****************************************************************************/
1237
1238/*
Joerg Roedel308973d2009-11-24 17:43:32 +01001239 * This function is used to add another level to an IO page table. Adding
1240 * another level increases the size of the address space by 9 bits to a size up
1241 * to 64 bits.
1242 */
1243static bool increase_address_space(struct protection_domain *domain,
1244 gfp_t gfp)
1245{
1246 u64 *pte;
1247
1248 if (domain->mode == PAGE_MODE_6_LEVEL)
1249 /* address space already 64 bit large */
1250 return false;
1251
1252 pte = (void *)get_zeroed_page(gfp);
1253 if (!pte)
1254 return false;
1255
1256 *pte = PM_LEVEL_PDE(domain->mode,
1257 virt_to_phys(domain->pt_root));
1258 domain->pt_root = pte;
1259 domain->mode += 1;
1260 domain->updated = true;
1261
1262 return true;
1263}
1264
1265static u64 *alloc_pte(struct protection_domain *domain,
1266 unsigned long address,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001267 unsigned long page_size,
Joerg Roedel308973d2009-11-24 17:43:32 +01001268 u64 **pte_page,
1269 gfp_t gfp)
1270{
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001271 int level, end_lvl;
Joerg Roedel308973d2009-11-24 17:43:32 +01001272 u64 *pte, *page;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001273
1274 BUG_ON(!is_power_of_2(page_size));
Joerg Roedel308973d2009-11-24 17:43:32 +01001275
1276 while (address > PM_LEVEL_SIZE(domain->mode))
1277 increase_address_space(domain, gfp);
1278
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001279 level = domain->mode - 1;
1280 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1281 address = PAGE_SIZE_ALIGN(address, page_size);
1282 end_lvl = PAGE_SIZE_LEVEL(page_size);
Joerg Roedel308973d2009-11-24 17:43:32 +01001283
1284 while (level > end_lvl) {
1285 if (!IOMMU_PTE_PRESENT(*pte)) {
1286 page = (u64 *)get_zeroed_page(gfp);
1287 if (!page)
1288 return NULL;
1289 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1290 }
1291
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001292 /* No level skipping support yet */
1293 if (PM_PTE_LEVEL(*pte) != level)
1294 return NULL;
1295
Joerg Roedel308973d2009-11-24 17:43:32 +01001296 level -= 1;
1297
1298 pte = IOMMU_PTE_PAGE(*pte);
1299
1300 if (pte_page && level == end_lvl)
1301 *pte_page = pte;
1302
1303 pte = &pte[PM_LEVEL_INDEX(level, address)];
1304 }
1305
1306 return pte;
1307}
1308
1309/*
1310 * This function checks if there is a PTE for a given dma address. If
1311 * there is one, it returns the pointer to it.
1312 */
Joerg Roedel24cd7722010-01-19 17:27:39 +01001313static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
Joerg Roedel308973d2009-11-24 17:43:32 +01001314{
1315 int level;
1316 u64 *pte;
1317
Joerg Roedel24cd7722010-01-19 17:27:39 +01001318 if (address > PM_LEVEL_SIZE(domain->mode))
1319 return NULL;
Joerg Roedel308973d2009-11-24 17:43:32 +01001320
Joerg Roedel24cd7722010-01-19 17:27:39 +01001321 level = domain->mode - 1;
1322 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1323
1324 while (level > 0) {
1325
1326 /* Not Present */
Joerg Roedel308973d2009-11-24 17:43:32 +01001327 if (!IOMMU_PTE_PRESENT(*pte))
1328 return NULL;
1329
Joerg Roedel24cd7722010-01-19 17:27:39 +01001330 /* Large PTE */
1331 if (PM_PTE_LEVEL(*pte) == 0x07) {
1332 unsigned long pte_mask, __pte;
1333
1334 /*
1335 * If we have a series of large PTEs, make
1336 * sure to return a pointer to the first one.
1337 */
1338 pte_mask = PTE_PAGE_SIZE(*pte);
1339 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1340 __pte = ((unsigned long)pte) & pte_mask;
1341
1342 return (u64 *)__pte;
1343 }
1344
1345 /* No level skipping support yet */
1346 if (PM_PTE_LEVEL(*pte) != level)
1347 return NULL;
1348
Joerg Roedel308973d2009-11-24 17:43:32 +01001349 level -= 1;
1350
Joerg Roedel24cd7722010-01-19 17:27:39 +01001351 /* Walk to the next level */
Joerg Roedel308973d2009-11-24 17:43:32 +01001352 pte = IOMMU_PTE_PAGE(*pte);
1353 pte = &pte[PM_LEVEL_INDEX(level, address)];
Joerg Roedel308973d2009-11-24 17:43:32 +01001354 }
1355
1356 return pte;
1357}
1358
1359/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001360 * Generic mapping functions. It maps a physical address into a DMA
1361 * address space. It allocates the page table pages if necessary.
1362 * In the future it can be extended to a generic mapping function
1363 * supporting all features of AMD IOMMU page tables like level skipping
1364 * and full 64 bit address spaces.
1365 */
Joerg Roedel38e817f2008-12-02 17:27:52 +01001366static int iommu_map_page(struct protection_domain *dom,
1367 unsigned long bus_addr,
1368 unsigned long phys_addr,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001369 int prot,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001370 unsigned long page_size)
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001371{
Joerg Roedel8bda3092009-05-12 12:02:46 +02001372 u64 __pte, *pte;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001373 int i, count;
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001374
Joerg Roedelbad1cac2009-09-02 16:52:23 +02001375 if (!(prot & IOMMU_PROT_MASK))
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001376 return -EINVAL;
1377
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001378 bus_addr = PAGE_ALIGN(bus_addr);
1379 phys_addr = PAGE_ALIGN(phys_addr);
1380 count = PAGE_SIZE_PTE_COUNT(page_size);
1381 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001382
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001383 for (i = 0; i < count; ++i)
1384 if (IOMMU_PTE_PRESENT(pte[i]))
1385 return -EBUSY;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001386
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001387 if (page_size > PAGE_SIZE) {
1388 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1389 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1390 } else
1391 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1392
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001393 if (prot & IOMMU_PROT_IR)
1394 __pte |= IOMMU_PTE_IR;
1395 if (prot & IOMMU_PROT_IW)
1396 __pte |= IOMMU_PTE_IW;
1397
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001398 for (i = 0; i < count; ++i)
1399 pte[i] = __pte;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001400
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001401 update_domain(dom);
1402
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001403 return 0;
1404}
1405
Joerg Roedel24cd7722010-01-19 17:27:39 +01001406static unsigned long iommu_unmap_page(struct protection_domain *dom,
1407 unsigned long bus_addr,
1408 unsigned long page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001409{
Joerg Roedel24cd7722010-01-19 17:27:39 +01001410 unsigned long long unmap_size, unmapped;
1411 u64 *pte;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001412
Joerg Roedel24cd7722010-01-19 17:27:39 +01001413 BUG_ON(!is_power_of_2(page_size));
1414
1415 unmapped = 0;
1416
1417 while (unmapped < page_size) {
1418
1419 pte = fetch_pte(dom, bus_addr);
1420
1421 if (!pte) {
1422 /*
1423 * No PTE for this address
1424 * move forward in 4kb steps
1425 */
1426 unmap_size = PAGE_SIZE;
1427 } else if (PM_PTE_LEVEL(*pte) == 0) {
1428 /* 4kb PTE found for this address */
1429 unmap_size = PAGE_SIZE;
1430 *pte = 0ULL;
1431 } else {
1432 int count, i;
1433
1434 /* Large PTE found which maps this address */
1435 unmap_size = PTE_PAGE_SIZE(*pte);
1436 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1437 for (i = 0; i < count; i++)
1438 pte[i] = 0ULL;
1439 }
1440
1441 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1442 unmapped += unmap_size;
1443 }
1444
1445 BUG_ON(!is_power_of_2(unmapped));
1446
1447 return unmapped;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001448}
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001449
Joerg Roedel431b2a22008-07-11 17:14:22 +02001450/*
1451 * This function checks if a specific unity mapping entry is needed for
1452 * this specific IOMMU.
1453 */
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001454static int iommu_for_unity_map(struct amd_iommu *iommu,
1455 struct unity_map_entry *entry)
1456{
1457 u16 bdf, i;
1458
1459 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1460 bdf = amd_iommu_alias_table[i];
1461 if (amd_iommu_rlookup_table[bdf] == iommu)
1462 return 1;
1463 }
1464
1465 return 0;
1466}
1467
Joerg Roedel431b2a22008-07-11 17:14:22 +02001468/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001469 * This function actually applies the mapping to the page table of the
1470 * dma_ops domain.
1471 */
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001472static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1473 struct unity_map_entry *e)
1474{
1475 u64 addr;
1476 int ret;
1477
1478 for (addr = e->address_start; addr < e->address_end;
1479 addr += PAGE_SIZE) {
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001480 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001481 PAGE_SIZE);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001482 if (ret)
1483 return ret;
1484 /*
1485 * if unity mapping is in aperture range mark the page
1486 * as allocated in the aperture
1487 */
1488 if (addr < dma_dom->aperture_size)
Joerg Roedelc3239562009-05-12 10:56:44 +02001489 __set_bit(addr >> PAGE_SHIFT,
Joerg Roedel384de722009-05-15 12:30:05 +02001490 dma_dom->aperture[0]->bitmap);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001491 }
1492
1493 return 0;
1494}
1495
Joerg Roedel431b2a22008-07-11 17:14:22 +02001496/*
Joerg Roedel171e7b32009-11-24 17:47:56 +01001497 * Init the unity mappings for a specific IOMMU in the system
1498 *
1499 * Basically iterates over all unity mapping entries and applies them to
1500 * the default domain DMA of that IOMMU if necessary.
1501 */
1502static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1503{
1504 struct unity_map_entry *entry;
1505 int ret;
1506
1507 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1508 if (!iommu_for_unity_map(iommu, entry))
1509 continue;
1510 ret = dma_ops_unity_map(iommu->default_dom, entry);
1511 if (ret)
1512 return ret;
1513 }
1514
1515 return 0;
1516}
1517
1518/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001519 * Inits the unity mappings required for a specific device
1520 */
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001521static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1522 u16 devid)
1523{
1524 struct unity_map_entry *e;
1525 int ret;
1526
1527 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1528 if (!(devid >= e->devid_start && devid <= e->devid_end))
1529 continue;
1530 ret = dma_ops_unity_map(dma_dom, e);
1531 if (ret)
1532 return ret;
1533 }
1534
1535 return 0;
1536}
1537
Joerg Roedel431b2a22008-07-11 17:14:22 +02001538/****************************************************************************
1539 *
1540 * The next functions belong to the address allocator for the dma_ops
1541 * interface functions. They work like the allocators in the other IOMMU
1542 * drivers. Its basically a bitmap which marks the allocated pages in
1543 * the aperture. Maybe it could be enhanced in the future to a more
1544 * efficient allocator.
1545 *
1546 ****************************************************************************/
Joerg Roedeld3086442008-06-26 21:27:57 +02001547
Joerg Roedel431b2a22008-07-11 17:14:22 +02001548/*
Joerg Roedel384de722009-05-15 12:30:05 +02001549 * The address allocator core functions.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001550 *
1551 * called with domain->lock held
1552 */
Joerg Roedel384de722009-05-15 12:30:05 +02001553
Joerg Roedel9cabe892009-05-18 16:38:55 +02001554/*
Joerg Roedel171e7b32009-11-24 17:47:56 +01001555 * Used to reserve address ranges in the aperture (e.g. for exclusion
1556 * ranges.
1557 */
1558static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1559 unsigned long start_page,
1560 unsigned int pages)
1561{
1562 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1563
1564 if (start_page + pages > last_page)
1565 pages = last_page - start_page;
1566
1567 for (i = start_page; i < start_page + pages; ++i) {
1568 int index = i / APERTURE_RANGE_PAGES;
1569 int page = i % APERTURE_RANGE_PAGES;
1570 __set_bit(page, dom->aperture[index]->bitmap);
1571 }
1572}
1573
1574/*
Joerg Roedel9cabe892009-05-18 16:38:55 +02001575 * This function is used to add a new aperture range to an existing
1576 * aperture in case of dma_ops domain allocation or address allocation
1577 * failure.
1578 */
Joerg Roedel576175c2009-11-23 19:08:46 +01001579static int alloc_new_range(struct dma_ops_domain *dma_dom,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001580 bool populate, gfp_t gfp)
1581{
1582 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
Joerg Roedel576175c2009-11-23 19:08:46 +01001583 struct amd_iommu *iommu;
Joerg Roedel17f5b562011-07-06 17:14:44 +02001584 unsigned long i, old_size;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001585
Joerg Roedelf5e97052009-05-22 12:31:53 +02001586#ifdef CONFIG_IOMMU_STRESS
1587 populate = false;
1588#endif
1589
Joerg Roedel9cabe892009-05-18 16:38:55 +02001590 if (index >= APERTURE_MAX_RANGES)
1591 return -ENOMEM;
1592
1593 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1594 if (!dma_dom->aperture[index])
1595 return -ENOMEM;
1596
1597 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1598 if (!dma_dom->aperture[index]->bitmap)
1599 goto out_free;
1600
1601 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1602
1603 if (populate) {
1604 unsigned long address = dma_dom->aperture_size;
1605 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1606 u64 *pte, *pte_page;
1607
1608 for (i = 0; i < num_ptes; ++i) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001609 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001610 &pte_page, gfp);
1611 if (!pte)
1612 goto out_free;
1613
1614 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1615
1616 address += APERTURE_RANGE_SIZE / 64;
1617 }
1618 }
1619
Joerg Roedel17f5b562011-07-06 17:14:44 +02001620 old_size = dma_dom->aperture_size;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001621 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1622
Joerg Roedel17f5b562011-07-06 17:14:44 +02001623 /* Reserve address range used for MSI messages */
1624 if (old_size < MSI_ADDR_BASE_LO &&
1625 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1626 unsigned long spage;
1627 int pages;
1628
1629 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1630 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1631
1632 dma_ops_reserve_addresses(dma_dom, spage, pages);
1633 }
1634
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001635 /* Initialize the exclusion range if necessary */
Joerg Roedel576175c2009-11-23 19:08:46 +01001636 for_each_iommu(iommu) {
1637 if (iommu->exclusion_start &&
1638 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1639 && iommu->exclusion_start < dma_dom->aperture_size) {
1640 unsigned long startpage;
1641 int pages = iommu_num_pages(iommu->exclusion_start,
1642 iommu->exclusion_length,
1643 PAGE_SIZE);
1644 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1645 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1646 }
Joerg Roedel00cd1222009-05-19 09:52:40 +02001647 }
1648
1649 /*
1650 * Check for areas already mapped as present in the new aperture
1651 * range and mark those pages as reserved in the allocator. Such
1652 * mappings may already exist as a result of requested unity
1653 * mappings for devices.
1654 */
1655 for (i = dma_dom->aperture[index]->offset;
1656 i < dma_dom->aperture_size;
1657 i += PAGE_SIZE) {
Joerg Roedel24cd7722010-01-19 17:27:39 +01001658 u64 *pte = fetch_pte(&dma_dom->domain, i);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001659 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1660 continue;
1661
Joerg Roedelfcd08612011-10-11 17:41:32 +02001662 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001663 }
1664
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001665 update_domain(&dma_dom->domain);
1666
Joerg Roedel9cabe892009-05-18 16:38:55 +02001667 return 0;
1668
1669out_free:
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001670 update_domain(&dma_dom->domain);
1671
Joerg Roedel9cabe892009-05-18 16:38:55 +02001672 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1673
1674 kfree(dma_dom->aperture[index]);
1675 dma_dom->aperture[index] = NULL;
1676
1677 return -ENOMEM;
1678}
1679
Joerg Roedel384de722009-05-15 12:30:05 +02001680static unsigned long dma_ops_area_alloc(struct device *dev,
1681 struct dma_ops_domain *dom,
1682 unsigned int pages,
1683 unsigned long align_mask,
1684 u64 dma_mask,
1685 unsigned long start)
1686{
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001687 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
Joerg Roedel384de722009-05-15 12:30:05 +02001688 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1689 int i = start >> APERTURE_RANGE_SHIFT;
1690 unsigned long boundary_size;
1691 unsigned long address = -1;
1692 unsigned long limit;
1693
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001694 next_bit >>= PAGE_SHIFT;
1695
Joerg Roedel384de722009-05-15 12:30:05 +02001696 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1697 PAGE_SIZE) >> PAGE_SHIFT;
1698
1699 for (;i < max_index; ++i) {
1700 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1701
1702 if (dom->aperture[i]->offset >= dma_mask)
1703 break;
1704
1705 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1706 dma_mask >> PAGE_SHIFT);
1707
1708 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1709 limit, next_bit, pages, 0,
1710 boundary_size, align_mask);
1711 if (address != -1) {
1712 address = dom->aperture[i]->offset +
1713 (address << PAGE_SHIFT);
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001714 dom->next_address = address + (pages << PAGE_SHIFT);
Joerg Roedel384de722009-05-15 12:30:05 +02001715 break;
1716 }
1717
1718 next_bit = 0;
1719 }
1720
1721 return address;
1722}
1723
Joerg Roedeld3086442008-06-26 21:27:57 +02001724static unsigned long dma_ops_alloc_addresses(struct device *dev,
1725 struct dma_ops_domain *dom,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02001726 unsigned int pages,
Joerg Roedel832a90c2008-09-18 15:54:23 +02001727 unsigned long align_mask,
1728 u64 dma_mask)
Joerg Roedeld3086442008-06-26 21:27:57 +02001729{
Joerg Roedeld3086442008-06-26 21:27:57 +02001730 unsigned long address;
Joerg Roedeld3086442008-06-26 21:27:57 +02001731
Joerg Roedelfe16f082009-05-22 12:27:53 +02001732#ifdef CONFIG_IOMMU_STRESS
1733 dom->next_address = 0;
1734 dom->need_flush = true;
1735#endif
Joerg Roedeld3086442008-06-26 21:27:57 +02001736
Joerg Roedel384de722009-05-15 12:30:05 +02001737 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001738 dma_mask, dom->next_address);
Joerg Roedeld3086442008-06-26 21:27:57 +02001739
Joerg Roedel1c655772008-09-04 18:40:05 +02001740 if (address == -1) {
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001741 dom->next_address = 0;
Joerg Roedel384de722009-05-15 12:30:05 +02001742 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1743 dma_mask, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001744 dom->need_flush = true;
1745 }
Joerg Roedeld3086442008-06-26 21:27:57 +02001746
Joerg Roedel384de722009-05-15 12:30:05 +02001747 if (unlikely(address == -1))
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09001748 address = DMA_ERROR_CODE;
Joerg Roedeld3086442008-06-26 21:27:57 +02001749
1750 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1751
1752 return address;
1753}
1754
Joerg Roedel431b2a22008-07-11 17:14:22 +02001755/*
1756 * The address free function.
1757 *
1758 * called with domain->lock held
1759 */
Joerg Roedeld3086442008-06-26 21:27:57 +02001760static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1761 unsigned long address,
1762 unsigned int pages)
1763{
Joerg Roedel384de722009-05-15 12:30:05 +02001764 unsigned i = address >> APERTURE_RANGE_SHIFT;
1765 struct aperture_range *range = dom->aperture[i];
Joerg Roedel80be3082008-11-06 14:59:05 +01001766
Joerg Roedel384de722009-05-15 12:30:05 +02001767 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1768
Joerg Roedel47bccd62009-05-22 12:40:54 +02001769#ifdef CONFIG_IOMMU_STRESS
1770 if (i < 4)
1771 return;
1772#endif
1773
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001774 if (address >= dom->next_address)
Joerg Roedel80be3082008-11-06 14:59:05 +01001775 dom->need_flush = true;
Joerg Roedel384de722009-05-15 12:30:05 +02001776
1777 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001778
Akinobu Mitaa66022c2009-12-15 16:48:28 -08001779 bitmap_clear(range->bitmap, address, pages);
Joerg Roedel384de722009-05-15 12:30:05 +02001780
Joerg Roedeld3086442008-06-26 21:27:57 +02001781}
1782
Joerg Roedel431b2a22008-07-11 17:14:22 +02001783/****************************************************************************
1784 *
1785 * The next functions belong to the domain allocation. A domain is
1786 * allocated for every IOMMU as the default domain. If device isolation
1787 * is enabled, every device get its own domain. The most important thing
1788 * about domains is the page table mapping the DMA address space they
1789 * contain.
1790 *
1791 ****************************************************************************/
1792
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001793/*
1794 * This function adds a protection domain to the global protection domain list
1795 */
1796static void add_domain_to_list(struct protection_domain *domain)
1797{
1798 unsigned long flags;
1799
1800 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1801 list_add(&domain->list, &amd_iommu_pd_list);
1802 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1803}
1804
1805/*
1806 * This function removes a protection domain to the global
1807 * protection domain list
1808 */
1809static void del_domain_from_list(struct protection_domain *domain)
1810{
1811 unsigned long flags;
1812
1813 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1814 list_del(&domain->list);
1815 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1816}
1817
Joerg Roedelec487d12008-06-26 21:27:58 +02001818static u16 domain_id_alloc(void)
1819{
1820 unsigned long flags;
1821 int id;
1822
1823 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1824 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1825 BUG_ON(id == 0);
1826 if (id > 0 && id < MAX_DOMAIN_ID)
1827 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1828 else
1829 id = 0;
1830 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1831
1832 return id;
1833}
1834
Joerg Roedela2acfb72008-12-02 18:28:53 +01001835static void domain_id_free(int id)
1836{
1837 unsigned long flags;
1838
1839 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1840 if (id > 0 && id < MAX_DOMAIN_ID)
1841 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1842 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1843}
Joerg Roedela2acfb72008-12-02 18:28:53 +01001844
Joerg Roedel86db2e52008-12-02 18:20:21 +01001845static void free_pagetable(struct protection_domain *domain)
Joerg Roedelec487d12008-06-26 21:27:58 +02001846{
1847 int i, j;
1848 u64 *p1, *p2, *p3;
1849
Joerg Roedel86db2e52008-12-02 18:20:21 +01001850 p1 = domain->pt_root;
Joerg Roedelec487d12008-06-26 21:27:58 +02001851
1852 if (!p1)
1853 return;
1854
1855 for (i = 0; i < 512; ++i) {
1856 if (!IOMMU_PTE_PRESENT(p1[i]))
1857 continue;
1858
1859 p2 = IOMMU_PTE_PAGE(p1[i]);
Joerg Roedel3cc3d842008-12-04 16:44:31 +01001860 for (j = 0; j < 512; ++j) {
Joerg Roedelec487d12008-06-26 21:27:58 +02001861 if (!IOMMU_PTE_PRESENT(p2[j]))
1862 continue;
1863 p3 = IOMMU_PTE_PAGE(p2[j]);
1864 free_page((unsigned long)p3);
1865 }
1866
1867 free_page((unsigned long)p2);
1868 }
1869
1870 free_page((unsigned long)p1);
Joerg Roedel86db2e52008-12-02 18:20:21 +01001871
1872 domain->pt_root = NULL;
Joerg Roedelec487d12008-06-26 21:27:58 +02001873}
1874
Joerg Roedelb16137b2011-11-21 16:50:23 +01001875static void free_gcr3_tbl_level1(u64 *tbl)
1876{
1877 u64 *ptr;
1878 int i;
1879
1880 for (i = 0; i < 512; ++i) {
1881 if (!(tbl[i] & GCR3_VALID))
1882 continue;
1883
1884 ptr = __va(tbl[i] & PAGE_MASK);
1885
1886 free_page((unsigned long)ptr);
1887 }
1888}
1889
1890static void free_gcr3_tbl_level2(u64 *tbl)
1891{
1892 u64 *ptr;
1893 int i;
1894
1895 for (i = 0; i < 512; ++i) {
1896 if (!(tbl[i] & GCR3_VALID))
1897 continue;
1898
1899 ptr = __va(tbl[i] & PAGE_MASK);
1900
1901 free_gcr3_tbl_level1(ptr);
1902 }
1903}
1904
Joerg Roedel52815b72011-11-17 17:24:28 +01001905static void free_gcr3_table(struct protection_domain *domain)
1906{
Joerg Roedelb16137b2011-11-21 16:50:23 +01001907 if (domain->glx == 2)
1908 free_gcr3_tbl_level2(domain->gcr3_tbl);
1909 else if (domain->glx == 1)
1910 free_gcr3_tbl_level1(domain->gcr3_tbl);
1911 else if (domain->glx != 0)
1912 BUG();
1913
Joerg Roedel52815b72011-11-17 17:24:28 +01001914 free_page((unsigned long)domain->gcr3_tbl);
1915}
1916
Joerg Roedel431b2a22008-07-11 17:14:22 +02001917/*
1918 * Free a domain, only used if something went wrong in the
1919 * allocation path and we need to free an already allocated page table
1920 */
Joerg Roedelec487d12008-06-26 21:27:58 +02001921static void dma_ops_domain_free(struct dma_ops_domain *dom)
1922{
Joerg Roedel384de722009-05-15 12:30:05 +02001923 int i;
1924
Joerg Roedelec487d12008-06-26 21:27:58 +02001925 if (!dom)
1926 return;
1927
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001928 del_domain_from_list(&dom->domain);
1929
Joerg Roedel86db2e52008-12-02 18:20:21 +01001930 free_pagetable(&dom->domain);
Joerg Roedelec487d12008-06-26 21:27:58 +02001931
Joerg Roedel384de722009-05-15 12:30:05 +02001932 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1933 if (!dom->aperture[i])
1934 continue;
1935 free_page((unsigned long)dom->aperture[i]->bitmap);
1936 kfree(dom->aperture[i]);
1937 }
Joerg Roedelec487d12008-06-26 21:27:58 +02001938
1939 kfree(dom);
1940}
1941
Joerg Roedel431b2a22008-07-11 17:14:22 +02001942/*
1943 * Allocates a new protection domain usable for the dma_ops functions.
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001944 * It also initializes the page table and the address allocator data
Joerg Roedel431b2a22008-07-11 17:14:22 +02001945 * structures required for the dma_ops interface
1946 */
Joerg Roedel87a64d52009-11-24 17:26:43 +01001947static struct dma_ops_domain *dma_ops_domain_alloc(void)
Joerg Roedelec487d12008-06-26 21:27:58 +02001948{
1949 struct dma_ops_domain *dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001950
1951 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1952 if (!dma_dom)
1953 return NULL;
1954
1955 spin_lock_init(&dma_dom->domain.lock);
1956
1957 dma_dom->domain.id = domain_id_alloc();
1958 if (dma_dom->domain.id == 0)
1959 goto free_dma_dom;
Joerg Roedel7c392cb2009-11-26 11:13:32 +01001960 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
Joerg Roedel8f7a0172009-09-02 16:55:24 +02001961 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
Joerg Roedelec487d12008-06-26 21:27:58 +02001962 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
Joerg Roedel9fdb19d2008-12-02 17:46:25 +01001963 dma_dom->domain.flags = PD_DMA_OPS_MASK;
Joerg Roedelec487d12008-06-26 21:27:58 +02001964 dma_dom->domain.priv = dma_dom;
1965 if (!dma_dom->domain.pt_root)
1966 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001967
Joerg Roedel1c655772008-09-04 18:40:05 +02001968 dma_dom->need_flush = false;
Joerg Roedelbd60b732008-09-11 10:24:48 +02001969 dma_dom->target_dev = 0xffff;
Joerg Roedel1c655772008-09-04 18:40:05 +02001970
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001971 add_domain_to_list(&dma_dom->domain);
1972
Joerg Roedel576175c2009-11-23 19:08:46 +01001973 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
Joerg Roedelec487d12008-06-26 21:27:58 +02001974 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001975
Joerg Roedel431b2a22008-07-11 17:14:22 +02001976 /*
Joerg Roedelec487d12008-06-26 21:27:58 +02001977 * mark the first page as allocated so we never return 0 as
1978 * a valid dma-address. So we can use 0 as error value
Joerg Roedel431b2a22008-07-11 17:14:22 +02001979 */
Joerg Roedel384de722009-05-15 12:30:05 +02001980 dma_dom->aperture[0]->bitmap[0] = 1;
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001981 dma_dom->next_address = 0;
Joerg Roedelec487d12008-06-26 21:27:58 +02001982
Joerg Roedelec487d12008-06-26 21:27:58 +02001983
1984 return dma_dom;
1985
1986free_dma_dom:
1987 dma_ops_domain_free(dma_dom);
1988
1989 return NULL;
1990}
1991
Joerg Roedel431b2a22008-07-11 17:14:22 +02001992/*
Joerg Roedel5b28df62008-12-02 17:49:42 +01001993 * little helper function to check whether a given protection domain is a
1994 * dma_ops domain
1995 */
1996static bool dma_ops_domain(struct protection_domain *domain)
1997{
1998 return domain->flags & PD_DMA_OPS_MASK;
1999}
2000
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002001static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002002{
Joerg Roedel132bd682011-11-17 14:18:46 +01002003 u64 pte_root = 0;
Joerg Roedelee6c2862011-11-09 12:06:03 +01002004 u64 flags = 0;
Joerg Roedel863c74e2008-12-02 17:56:36 +01002005
Joerg Roedel132bd682011-11-17 14:18:46 +01002006 if (domain->mode != PAGE_MODE_NONE)
2007 pte_root = virt_to_phys(domain->pt_root);
2008
Joerg Roedel38ddf412008-09-11 10:38:32 +02002009 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2010 << DEV_ENTRY_MODE_SHIFT;
2011 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002012
Joerg Roedelee6c2862011-11-09 12:06:03 +01002013 flags = amd_iommu_dev_table[devid].data[1];
2014
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002015 if (ats)
2016 flags |= DTE_FLAG_IOTLB;
2017
Joerg Roedel52815b72011-11-17 17:24:28 +01002018 if (domain->flags & PD_IOMMUV2_MASK) {
2019 u64 gcr3 = __pa(domain->gcr3_tbl);
2020 u64 glx = domain->glx;
2021 u64 tmp;
2022
2023 pte_root |= DTE_FLAG_GV;
2024 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2025
2026 /* First mask out possible old values for GCR3 table */
2027 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2028 flags &= ~tmp;
2029
2030 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2031 flags &= ~tmp;
2032
2033 /* Encode GCR3 table into DTE */
2034 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2035 pte_root |= tmp;
2036
2037 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2038 flags |= tmp;
2039
2040 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2041 flags |= tmp;
2042 }
2043
Joerg Roedelee6c2862011-11-09 12:06:03 +01002044 flags &= ~(0xffffUL);
2045 flags |= domain->id;
2046
2047 amd_iommu_dev_table[devid].data[1] = flags;
2048 amd_iommu_dev_table[devid].data[0] = pte_root;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002049}
2050
Joerg Roedel15898bb2009-11-24 15:39:42 +01002051static void clear_dte_entry(u16 devid)
Joerg Roedel355bf552008-12-08 12:02:41 +01002052{
Joerg Roedel355bf552008-12-08 12:02:41 +01002053 /* remove entry from the device table seen by the hardware */
2054 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2055 amd_iommu_dev_table[devid].data[1] = 0;
Joerg Roedel355bf552008-12-08 12:02:41 +01002056
Joerg Roedelc5cca142009-10-09 18:31:20 +02002057 amd_iommu_apply_erratum_63(devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002058}
2059
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002060static void do_attach(struct iommu_dev_data *dev_data,
2061 struct protection_domain *domain)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002062{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002063 struct amd_iommu *iommu;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002064 bool ats;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002065
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002066 iommu = amd_iommu_rlookup_table[dev_data->devid];
2067 ats = dev_data->ats.enabled;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002068
2069 /* Update data structures */
2070 dev_data->domain = domain;
2071 list_add(&dev_data->list, &domain->dev_list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02002072 set_dte_entry(dev_data->devid, domain, ats);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002073
2074 /* Do reference counting */
2075 domain->dev_iommu[iommu->index] += 1;
2076 domain->dev_cnt += 1;
2077
2078 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02002079 device_flush_dte(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002080}
2081
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002082static void do_detach(struct iommu_dev_data *dev_data)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002083{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002084 struct amd_iommu *iommu;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002085
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002086 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelc5cca142009-10-09 18:31:20 +02002087
Joerg Roedelc4596112009-11-20 14:57:32 +01002088 /* decrease reference counters */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002089 dev_data->domain->dev_iommu[iommu->index] -= 1;
2090 dev_data->domain->dev_cnt -= 1;
Joerg Roedel355bf552008-12-08 12:02:41 +01002091
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002092 /* Update data structures */
2093 dev_data->domain = NULL;
2094 list_del(&dev_data->list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02002095 clear_dte_entry(dev_data->devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002096
2097 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02002098 device_flush_dte(dev_data);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002099}
2100
2101/*
2102 * If a device is not yet associated with a domain, this function does
2103 * assigns it visible for the hardware
2104 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002105static int __attach_device(struct iommu_dev_data *dev_data,
Joerg Roedel15898bb2009-11-24 15:39:42 +01002106 struct protection_domain *domain)
2107{
Julia Lawall84fe6c12010-05-27 12:31:51 +02002108 int ret;
Joerg Roedel657cbb62009-11-23 15:26:46 +01002109
Joerg Roedel15898bb2009-11-24 15:39:42 +01002110 /* lock domain */
2111 spin_lock(&domain->lock);
2112
Joerg Roedel71f77582011-06-09 19:03:15 +02002113 if (dev_data->alias_data != NULL) {
2114 struct iommu_dev_data *alias_data = dev_data->alias_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002115
Joerg Roedel2b02b092011-06-09 17:48:39 +02002116 /* Some sanity checks */
2117 ret = -EBUSY;
2118 if (alias_data->domain != NULL &&
2119 alias_data->domain != domain)
2120 goto out_unlock;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002121
Joerg Roedel2b02b092011-06-09 17:48:39 +02002122 if (dev_data->domain != NULL &&
2123 dev_data->domain != domain)
2124 goto out_unlock;
2125
2126 /* Do real assignment */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002127 if (alias_data->domain == NULL)
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002128 do_attach(alias_data, domain);
Joerg Roedel24100052009-11-25 15:59:57 +01002129
2130 atomic_inc(&alias_data->bind);
Joerg Roedel657cbb62009-11-23 15:26:46 +01002131 }
Joerg Roedel15898bb2009-11-24 15:39:42 +01002132
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002133 if (dev_data->domain == NULL)
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002134 do_attach(dev_data, domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002135
Joerg Roedel24100052009-11-25 15:59:57 +01002136 atomic_inc(&dev_data->bind);
2137
Julia Lawall84fe6c12010-05-27 12:31:51 +02002138 ret = 0;
2139
2140out_unlock:
2141
Joerg Roedel355bf552008-12-08 12:02:41 +01002142 /* ready */
2143 spin_unlock(&domain->lock);
Joerg Roedel21129f72009-09-01 11:59:42 +02002144
Julia Lawall84fe6c12010-05-27 12:31:51 +02002145 return ret;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002146}
2147
Joerg Roedel52815b72011-11-17 17:24:28 +01002148
2149static void pdev_iommuv2_disable(struct pci_dev *pdev)
2150{
2151 pci_disable_ats(pdev);
2152 pci_disable_pri(pdev);
2153 pci_disable_pasid(pdev);
2154}
2155
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002156/* FIXME: Change generic reset-function to do the same */
2157static int pri_reset_while_enabled(struct pci_dev *pdev)
2158{
2159 u16 control;
2160 int pos;
2161
Joerg Roedel46277b72011-12-07 14:34:02 +01002162 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002163 if (!pos)
2164 return -EINVAL;
2165
Joerg Roedel46277b72011-12-07 14:34:02 +01002166 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2167 control |= PCI_PRI_CTRL_RESET;
2168 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002169
2170 return 0;
2171}
2172
Joerg Roedel52815b72011-11-17 17:24:28 +01002173static int pdev_iommuv2_enable(struct pci_dev *pdev)
2174{
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002175 bool reset_enable;
2176 int reqs, ret;
2177
2178 /* FIXME: Hardcode number of outstanding requests for now */
2179 reqs = 32;
2180 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2181 reqs = 1;
2182 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
Joerg Roedel52815b72011-11-17 17:24:28 +01002183
2184 /* Only allow access to user-accessible pages */
2185 ret = pci_enable_pasid(pdev, 0);
2186 if (ret)
2187 goto out_err;
2188
2189 /* First reset the PRI state of the device */
2190 ret = pci_reset_pri(pdev);
2191 if (ret)
2192 goto out_err;
2193
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002194 /* Enable PRI */
2195 ret = pci_enable_pri(pdev, reqs);
Joerg Roedel52815b72011-11-17 17:24:28 +01002196 if (ret)
2197 goto out_err;
2198
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002199 if (reset_enable) {
2200 ret = pri_reset_while_enabled(pdev);
2201 if (ret)
2202 goto out_err;
2203 }
2204
Joerg Roedel52815b72011-11-17 17:24:28 +01002205 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2206 if (ret)
2207 goto out_err;
2208
2209 return 0;
2210
2211out_err:
2212 pci_disable_pri(pdev);
2213 pci_disable_pasid(pdev);
2214
2215 return ret;
2216}
2217
Joerg Roedelc99afa22011-11-21 18:19:25 +01002218/* FIXME: Move this to PCI code */
Joerg Roedela3b93122012-04-12 12:49:26 +02002219#define PCI_PRI_TLP_OFF (1 << 15)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002220
Joerg Roedel98f1ad22012-07-06 13:28:37 +02002221static bool pci_pri_tlp_required(struct pci_dev *pdev)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002222{
Joerg Roedela3b93122012-04-12 12:49:26 +02002223 u16 status;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002224 int pos;
2225
Joerg Roedel46277b72011-12-07 14:34:02 +01002226 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002227 if (!pos)
2228 return false;
2229
Joerg Roedela3b93122012-04-12 12:49:26 +02002230 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002231
Joerg Roedela3b93122012-04-12 12:49:26 +02002232 return (status & PCI_PRI_TLP_OFF) ? true : false;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002233}
2234
Joerg Roedel15898bb2009-11-24 15:39:42 +01002235/*
Frank Arnolddf805ab2012-08-27 19:21:04 +02002236 * If a device is not yet associated with a domain, this function
Joerg Roedel15898bb2009-11-24 15:39:42 +01002237 * assigns it visible for the hardware
2238 */
2239static int attach_device(struct device *dev,
2240 struct protection_domain *domain)
2241{
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002242 struct pci_dev *pdev = to_pci_dev(dev);
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002243 struct iommu_dev_data *dev_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002244 unsigned long flags;
2245 int ret;
2246
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002247 dev_data = get_dev_data(dev);
2248
Joerg Roedel52815b72011-11-17 17:24:28 +01002249 if (domain->flags & PD_IOMMUV2_MASK) {
2250 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2251 return -EINVAL;
2252
2253 if (pdev_iommuv2_enable(pdev) != 0)
2254 return -EINVAL;
2255
2256 dev_data->ats.enabled = true;
2257 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002258 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002259 } else if (amd_iommu_iotlb_sup &&
2260 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002261 dev_data->ats.enabled = true;
2262 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2263 }
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002264
Joerg Roedel15898bb2009-11-24 15:39:42 +01002265 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002266 ret = __attach_device(dev_data, domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002267 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2268
2269 /*
2270 * We might boot into a crash-kernel here. The crashed kernel
2271 * left the caches in the IOMMU dirty. So we have to flush
2272 * here to evict all dirty stuff.
2273 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02002274 domain_flush_tlb_pde(domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002275
2276 return ret;
2277}
2278
2279/*
2280 * Removes a device from a protection domain (unlocked)
2281 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002282static void __detach_device(struct iommu_dev_data *dev_data)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002283{
Joerg Roedel2ca76272010-01-22 16:45:31 +01002284 struct protection_domain *domain;
Joerg Roedel7c392cb2009-11-26 11:13:32 +01002285 unsigned long flags;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002286
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002287 BUG_ON(!dev_data->domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002288
Joerg Roedel2ca76272010-01-22 16:45:31 +01002289 domain = dev_data->domain;
2290
2291 spin_lock_irqsave(&domain->lock, flags);
Joerg Roedel24100052009-11-25 15:59:57 +01002292
Joerg Roedel71f77582011-06-09 19:03:15 +02002293 if (dev_data->alias_data != NULL) {
2294 struct iommu_dev_data *alias_data = dev_data->alias_data;
2295
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002296 if (atomic_dec_and_test(&alias_data->bind))
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002297 do_detach(alias_data);
Joerg Roedel24100052009-11-25 15:59:57 +01002298 }
2299
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002300 if (atomic_dec_and_test(&dev_data->bind))
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002301 do_detach(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002302
Joerg Roedel2ca76272010-01-22 16:45:31 +01002303 spin_unlock_irqrestore(&domain->lock, flags);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002304
Joerg Roedel21129f72009-09-01 11:59:42 +02002305 /*
2306 * If we run in passthrough mode the device must be assigned to the
Joerg Roedeld3ad9372010-01-22 17:55:27 +01002307 * passthrough domain if it is detached from any other domain.
2308 * Make sure we can deassign from the pt_domain itself.
Joerg Roedel21129f72009-09-01 11:59:42 +02002309 */
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002310 if (dev_data->passthrough &&
Joerg Roedeld3ad9372010-01-22 17:55:27 +01002311 (dev_data->domain == NULL && domain != pt_domain))
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002312 __attach_device(dev_data, pt_domain);
Joerg Roedel355bf552008-12-08 12:02:41 +01002313}
2314
2315/*
2316 * Removes a device from a protection domain (with devtable_lock held)
2317 */
Joerg Roedel15898bb2009-11-24 15:39:42 +01002318static void detach_device(struct device *dev)
Joerg Roedel355bf552008-12-08 12:02:41 +01002319{
Joerg Roedel52815b72011-11-17 17:24:28 +01002320 struct protection_domain *domain;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002321 struct iommu_dev_data *dev_data;
Joerg Roedel355bf552008-12-08 12:02:41 +01002322 unsigned long flags;
2323
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002324 dev_data = get_dev_data(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002325 domain = dev_data->domain;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002326
Joerg Roedel355bf552008-12-08 12:02:41 +01002327 /* lock device table */
2328 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002329 __detach_device(dev_data);
Joerg Roedel355bf552008-12-08 12:02:41 +01002330 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002331
Joerg Roedel52815b72011-11-17 17:24:28 +01002332 if (domain->flags & PD_IOMMUV2_MASK)
2333 pdev_iommuv2_disable(to_pci_dev(dev));
2334 else if (dev_data->ats.enabled)
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002335 pci_disable_ats(to_pci_dev(dev));
Joerg Roedel52815b72011-11-17 17:24:28 +01002336
2337 dev_data->ats.enabled = false;
Joerg Roedel355bf552008-12-08 12:02:41 +01002338}
Joerg Roedele275a2a2008-12-10 18:27:25 +01002339
Joerg Roedel15898bb2009-11-24 15:39:42 +01002340/*
2341 * Find out the protection domain structure for a given PCI device. This
2342 * will give us the pointer to the page table root for example.
2343 */
2344static struct protection_domain *domain_for_device(struct device *dev)
2345{
Joerg Roedel71f77582011-06-09 19:03:15 +02002346 struct iommu_dev_data *dev_data;
Joerg Roedel2b02b092011-06-09 17:48:39 +02002347 struct protection_domain *dom = NULL;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002348 unsigned long flags;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002349
Joerg Roedel657cbb62009-11-23 15:26:46 +01002350 dev_data = get_dev_data(dev);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002351
Joerg Roedel2b02b092011-06-09 17:48:39 +02002352 if (dev_data->domain)
2353 return dev_data->domain;
2354
Joerg Roedel71f77582011-06-09 19:03:15 +02002355 if (dev_data->alias_data != NULL) {
2356 struct iommu_dev_data *alias_data = dev_data->alias_data;
Joerg Roedel2b02b092011-06-09 17:48:39 +02002357
2358 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2359 if (alias_data->domain != NULL) {
2360 __attach_device(dev_data, alias_data->domain);
2361 dom = alias_data->domain;
2362 }
2363 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002364 }
2365
Joerg Roedel15898bb2009-11-24 15:39:42 +01002366 return dom;
2367}
2368
Joerg Roedele275a2a2008-12-10 18:27:25 +01002369static int device_change_notifier(struct notifier_block *nb,
2370 unsigned long action, void *data)
2371{
Joerg Roedele275a2a2008-12-10 18:27:25 +01002372 struct dma_ops_domain *dma_domain;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002373 struct protection_domain *domain;
2374 struct iommu_dev_data *dev_data;
2375 struct device *dev = data;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002376 struct amd_iommu *iommu;
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002377 unsigned long flags;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002378 u16 devid;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002379
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002380 if (!check_device(dev))
2381 return 0;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002382
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002383 devid = get_device_id(dev);
2384 iommu = amd_iommu_rlookup_table[devid];
2385 dev_data = get_dev_data(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002386
2387 switch (action) {
Chris Wrightc1eee672009-05-21 00:56:58 -07002388 case BUS_NOTIFY_UNBOUND_DRIVER:
Joerg Roedel657cbb62009-11-23 15:26:46 +01002389
2390 domain = domain_for_device(dev);
2391
Joerg Roedele275a2a2008-12-10 18:27:25 +01002392 if (!domain)
2393 goto out;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002394 if (dev_data->passthrough)
Joerg Roedela1ca3312009-09-01 12:22:22 +02002395 break;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002396 detach_device(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002397 break;
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002398 case BUS_NOTIFY_ADD_DEVICE:
Joerg Roedel657cbb62009-11-23 15:26:46 +01002399
2400 iommu_init_device(dev);
2401
Joerg Roedel2c9195e2012-07-19 13:42:54 +02002402 /*
2403 * dev_data is still NULL and
2404 * got initialized in iommu_init_device
2405 */
2406 dev_data = get_dev_data(dev);
2407
2408 if (iommu_pass_through || dev_data->iommu_v2) {
2409 dev_data->passthrough = true;
2410 attach_device(dev, pt_domain);
2411 break;
2412 }
2413
Joerg Roedel657cbb62009-11-23 15:26:46 +01002414 domain = domain_for_device(dev);
2415
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002416 /* allocate a protection domain if a device is added */
2417 dma_domain = find_protection_domain(devid);
2418 if (dma_domain)
2419 goto out;
Joerg Roedel87a64d52009-11-24 17:26:43 +01002420 dma_domain = dma_ops_domain_alloc();
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002421 if (!dma_domain)
2422 goto out;
2423 dma_domain->target_dev = devid;
2424
2425 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2426 list_add_tail(&dma_domain->list, &iommu_pd_list);
2427 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2428
Joerg Roedelac1534a2012-06-21 14:52:40 +02002429 dev_data = get_dev_data(dev);
2430
Joerg Roedel2c9195e2012-07-19 13:42:54 +02002431 dev->archdata.dma_ops = &amd_iommu_dma_ops;
Joerg Roedelac1534a2012-06-21 14:52:40 +02002432
Joerg Roedel1ac4cbb2008-12-10 19:33:26 +01002433 break;
Joerg Roedel657cbb62009-11-23 15:26:46 +01002434 case BUS_NOTIFY_DEL_DEVICE:
2435
2436 iommu_uninit_device(dev);
2437
Joerg Roedele275a2a2008-12-10 18:27:25 +01002438 default:
2439 goto out;
2440 }
2441
Joerg Roedele275a2a2008-12-10 18:27:25 +01002442 iommu_completion_wait(iommu);
2443
2444out:
2445 return 0;
2446}
2447
Jaswinder Singh Rajputb25ae672009-07-01 19:53:14 +05302448static struct notifier_block device_nb = {
Joerg Roedele275a2a2008-12-10 18:27:25 +01002449 .notifier_call = device_change_notifier,
2450};
Joerg Roedel355bf552008-12-08 12:02:41 +01002451
Joerg Roedel8638c492009-12-10 11:12:25 +01002452void amd_iommu_init_notifier(void)
2453{
2454 bus_register_notifier(&pci_bus_type, &device_nb);
2455}
2456
Joerg Roedel431b2a22008-07-11 17:14:22 +02002457/*****************************************************************************
2458 *
2459 * The next functions belong to the dma_ops mapping/unmapping code.
2460 *
2461 *****************************************************************************/
2462
2463/*
2464 * In the dma_ops path we only have the struct device. This function
2465 * finds the corresponding IOMMU, the protection domain and the
2466 * requestor id for a given device.
2467 * If the device is not yet associated with a domain this is also done
2468 * in this function.
2469 */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002470static struct protection_domain *get_domain(struct device *dev)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002471{
Joerg Roedel94f6d192009-11-24 16:40:02 +01002472 struct protection_domain *domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002473 struct dma_ops_domain *dma_dom;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002474 u16 devid = get_device_id(dev);
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002475
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002476 if (!check_device(dev))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002477 return ERR_PTR(-EINVAL);
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002478
Joerg Roedel94f6d192009-11-24 16:40:02 +01002479 domain = domain_for_device(dev);
2480 if (domain != NULL && !dma_ops_domain(domain))
2481 return ERR_PTR(-EBUSY);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002482
Joerg Roedel94f6d192009-11-24 16:40:02 +01002483 if (domain != NULL)
2484 return domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002485
Frank Arnolddf805ab2012-08-27 19:21:04 +02002486 /* Device not bound yet - bind it */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002487 dma_dom = find_protection_domain(devid);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002488 if (!dma_dom)
Joerg Roedel94f6d192009-11-24 16:40:02 +01002489 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2490 attach_device(dev, &dma_dom->domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002491 DUMP_printk("Using protection domain %d for device %s\n",
Joerg Roedel94f6d192009-11-24 16:40:02 +01002492 dma_dom->domain.id, dev_name(dev));
Joerg Roedelf91ba192008-11-25 12:56:12 +01002493
Joerg Roedel94f6d192009-11-24 16:40:02 +01002494 return &dma_dom->domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002495}
2496
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002497static void update_device_table(struct protection_domain *domain)
2498{
Joerg Roedel492667d2009-11-27 13:25:47 +01002499 struct iommu_dev_data *dev_data;
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002500
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002501 list_for_each_entry(dev_data, &domain->dev_list, list)
2502 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002503}
2504
2505static void update_domain(struct protection_domain *domain)
2506{
2507 if (!domain->updated)
2508 return;
2509
2510 update_device_table(domain);
Joerg Roedel17b124b2011-04-06 18:01:35 +02002511
2512 domain_flush_devices(domain);
2513 domain_flush_tlb_pde(domain);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002514
2515 domain->updated = false;
2516}
2517
Joerg Roedel431b2a22008-07-11 17:14:22 +02002518/*
Joerg Roedel8bda3092009-05-12 12:02:46 +02002519 * This function fetches the PTE for a given address in the aperture
2520 */
2521static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2522 unsigned long address)
2523{
Joerg Roedel384de722009-05-15 12:30:05 +02002524 struct aperture_range *aperture;
Joerg Roedel8bda3092009-05-12 12:02:46 +02002525 u64 *pte, *pte_page;
2526
Joerg Roedel384de722009-05-15 12:30:05 +02002527 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2528 if (!aperture)
2529 return NULL;
2530
2531 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
Joerg Roedel8bda3092009-05-12 12:02:46 +02002532 if (!pte) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01002533 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02002534 GFP_ATOMIC);
Joerg Roedel384de722009-05-15 12:30:05 +02002535 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2536 } else
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002537 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002538
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002539 update_domain(&dom->domain);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002540
2541 return pte;
2542}
2543
2544/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002545 * This is the generic map function. It maps one 4kb page at paddr to
2546 * the given address in the DMA address space for the domain.
2547 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002548static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002549 unsigned long address,
2550 phys_addr_t paddr,
2551 int direction)
2552{
2553 u64 *pte, __pte;
2554
2555 WARN_ON(address > dom->aperture_size);
2556
2557 paddr &= PAGE_MASK;
2558
Joerg Roedel8bda3092009-05-12 12:02:46 +02002559 pte = dma_ops_get_pte(dom, address);
Joerg Roedel53812c12009-05-12 12:17:38 +02002560 if (!pte)
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002561 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002562
2563 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2564
2565 if (direction == DMA_TO_DEVICE)
2566 __pte |= IOMMU_PTE_IR;
2567 else if (direction == DMA_FROM_DEVICE)
2568 __pte |= IOMMU_PTE_IW;
2569 else if (direction == DMA_BIDIRECTIONAL)
2570 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2571
2572 WARN_ON(*pte);
2573
2574 *pte = __pte;
2575
2576 return (dma_addr_t)address;
2577}
2578
Joerg Roedel431b2a22008-07-11 17:14:22 +02002579/*
2580 * The generic unmapping function for on page in the DMA address space.
2581 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002582static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002583 unsigned long address)
2584{
Joerg Roedel384de722009-05-15 12:30:05 +02002585 struct aperture_range *aperture;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002586 u64 *pte;
2587
2588 if (address >= dom->aperture_size)
2589 return;
2590
Joerg Roedel384de722009-05-15 12:30:05 +02002591 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2592 if (!aperture)
2593 return;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002594
Joerg Roedel384de722009-05-15 12:30:05 +02002595 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2596 if (!pte)
2597 return;
2598
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002599 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002600
2601 WARN_ON(!*pte);
2602
2603 *pte = 0ULL;
2604}
2605
Joerg Roedel431b2a22008-07-11 17:14:22 +02002606/*
2607 * This function contains common code for mapping of a physically
Joerg Roedel24f81162008-12-08 14:25:39 +01002608 * contiguous memory region into DMA address space. It is used by all
2609 * mapping functions provided with this IOMMU driver.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002610 * Must be called with the domain lock held.
2611 */
Joerg Roedelcb76c322008-06-26 21:28:00 +02002612static dma_addr_t __map_single(struct device *dev,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002613 struct dma_ops_domain *dma_dom,
2614 phys_addr_t paddr,
2615 size_t size,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002616 int dir,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002617 bool align,
2618 u64 dma_mask)
Joerg Roedelcb76c322008-06-26 21:28:00 +02002619{
2620 dma_addr_t offset = paddr & ~PAGE_MASK;
Joerg Roedel53812c12009-05-12 12:17:38 +02002621 dma_addr_t address, start, ret;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002622 unsigned int pages;
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002623 unsigned long align_mask = 0;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002624 int i;
2625
Joerg Roedele3c449f2008-10-15 22:02:11 -07002626 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002627 paddr &= PAGE_MASK;
2628
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +01002629 INC_STATS_COUNTER(total_map_requests);
2630
Joerg Roedelc1858972008-12-12 15:42:39 +01002631 if (pages > 1)
2632 INC_STATS_COUNTER(cross_page);
2633
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002634 if (align)
2635 align_mask = (1UL << get_order(size)) - 1;
2636
Joerg Roedel11b83882009-05-19 10:23:15 +02002637retry:
Joerg Roedel832a90c2008-09-18 15:54:23 +02002638 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2639 dma_mask);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002640 if (unlikely(address == DMA_ERROR_CODE)) {
Joerg Roedel11b83882009-05-19 10:23:15 +02002641 /*
2642 * setting next_address here will let the address
2643 * allocator only scan the new allocated range in the
2644 * first run. This is a small optimization.
2645 */
2646 dma_dom->next_address = dma_dom->aperture_size;
2647
Joerg Roedel576175c2009-11-23 19:08:46 +01002648 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
Joerg Roedel11b83882009-05-19 10:23:15 +02002649 goto out;
2650
2651 /*
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02002652 * aperture was successfully enlarged by 128 MB, try
Joerg Roedel11b83882009-05-19 10:23:15 +02002653 * allocation again
2654 */
2655 goto retry;
2656 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002657
2658 start = address;
2659 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002660 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002661 if (ret == DMA_ERROR_CODE)
Joerg Roedel53812c12009-05-12 12:17:38 +02002662 goto out_unmap;
2663
Joerg Roedelcb76c322008-06-26 21:28:00 +02002664 paddr += PAGE_SIZE;
2665 start += PAGE_SIZE;
2666 }
2667 address += offset;
2668
Joerg Roedel5774f7c2008-12-12 15:57:30 +01002669 ADD_STATS_COUNTER(alloced_io_mem, size);
2670
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09002671 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002672 domain_flush_tlb(&dma_dom->domain);
Joerg Roedel1c655772008-09-04 18:40:05 +02002673 dma_dom->need_flush = false;
Joerg Roedel318afd42009-11-23 18:32:38 +01002674 } else if (unlikely(amd_iommu_np_cache))
Joerg Roedel17b124b2011-04-06 18:01:35 +02002675 domain_flush_pages(&dma_dom->domain, address, size);
Joerg Roedel270cab242008-09-04 15:49:46 +02002676
Joerg Roedelcb76c322008-06-26 21:28:00 +02002677out:
2678 return address;
Joerg Roedel53812c12009-05-12 12:17:38 +02002679
2680out_unmap:
2681
2682 for (--i; i >= 0; --i) {
2683 start -= PAGE_SIZE;
Joerg Roedel680525e2009-11-23 18:44:42 +01002684 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedel53812c12009-05-12 12:17:38 +02002685 }
2686
2687 dma_ops_free_addresses(dma_dom, address, pages);
2688
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002689 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002690}
2691
Joerg Roedel431b2a22008-07-11 17:14:22 +02002692/*
2693 * Does the reverse of the __map_single function. Must be called with
2694 * the domain lock held too
2695 */
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002696static void __unmap_single(struct dma_ops_domain *dma_dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002697 dma_addr_t dma_addr,
2698 size_t size,
2699 int dir)
2700{
Joerg Roedel04e04632010-09-23 16:12:48 +02002701 dma_addr_t flush_addr;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002702 dma_addr_t i, start;
2703 unsigned int pages;
2704
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002705 if ((dma_addr == DMA_ERROR_CODE) ||
Joerg Roedelb8d99052008-12-08 14:40:26 +01002706 (dma_addr + size > dma_dom->aperture_size))
Joerg Roedelcb76c322008-06-26 21:28:00 +02002707 return;
2708
Joerg Roedel04e04632010-09-23 16:12:48 +02002709 flush_addr = dma_addr;
Joerg Roedele3c449f2008-10-15 22:02:11 -07002710 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002711 dma_addr &= PAGE_MASK;
2712 start = dma_addr;
2713
2714 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002715 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002716 start += PAGE_SIZE;
2717 }
2718
Joerg Roedel5774f7c2008-12-12 15:57:30 +01002719 SUB_STATS_COUNTER(alloced_io_mem, size);
2720
Joerg Roedelcb76c322008-06-26 21:28:00 +02002721 dma_ops_free_addresses(dma_dom, dma_addr, pages);
Joerg Roedel270cab242008-09-04 15:49:46 +02002722
Joerg Roedel80be3082008-11-06 14:59:05 +01002723 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002724 domain_flush_pages(&dma_dom->domain, flush_addr, size);
Joerg Roedel80be3082008-11-06 14:59:05 +01002725 dma_dom->need_flush = false;
2726 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002727}
2728
Joerg Roedel431b2a22008-07-11 17:14:22 +02002729/*
2730 * The exported map_single function for dma_ops.
2731 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002732static dma_addr_t map_page(struct device *dev, struct page *page,
2733 unsigned long offset, size_t size,
2734 enum dma_data_direction dir,
2735 struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002736{
2737 unsigned long flags;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002738 struct protection_domain *domain;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002739 dma_addr_t addr;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002740 u64 dma_mask;
FUJITA Tomonori51491362009-01-05 23:47:25 +09002741 phys_addr_t paddr = page_to_phys(page) + offset;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002742
Joerg Roedel0f2a86f2008-12-12 15:05:16 +01002743 INC_STATS_COUNTER(cnt_map_single);
2744
Joerg Roedel94f6d192009-11-24 16:40:02 +01002745 domain = get_domain(dev);
2746 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002747 return (dma_addr_t)paddr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002748 else if (IS_ERR(domain))
2749 return DMA_ERROR_CODE;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002750
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002751 dma_mask = *dev->dma_mask;
2752
Joerg Roedel4da70b92008-06-26 21:28:01 +02002753 spin_lock_irqsave(&domain->lock, flags);
Joerg Roedel94f6d192009-11-24 16:40:02 +01002754
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002755 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002756 dma_mask);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002757 if (addr == DMA_ERROR_CODE)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002758 goto out;
2759
Joerg Roedel17b124b2011-04-06 18:01:35 +02002760 domain_flush_complete(domain);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002761
2762out:
2763 spin_unlock_irqrestore(&domain->lock, flags);
2764
2765 return addr;
2766}
2767
Joerg Roedel431b2a22008-07-11 17:14:22 +02002768/*
2769 * The exported unmap_single function for dma_ops.
2770 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002771static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2772 enum dma_data_direction dir, struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002773{
2774 unsigned long flags;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002775 struct protection_domain *domain;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002776
Joerg Roedel146a6912008-12-12 15:07:12 +01002777 INC_STATS_COUNTER(cnt_unmap_single);
2778
Joerg Roedel94f6d192009-11-24 16:40:02 +01002779 domain = get_domain(dev);
2780 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002781 return;
2782
Joerg Roedel4da70b92008-06-26 21:28:01 +02002783 spin_lock_irqsave(&domain->lock, flags);
2784
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002785 __unmap_single(domain->priv, dma_addr, size, dir);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002786
Joerg Roedel17b124b2011-04-06 18:01:35 +02002787 domain_flush_complete(domain);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002788
2789 spin_unlock_irqrestore(&domain->lock, flags);
2790}
2791
Joerg Roedel431b2a22008-07-11 17:14:22 +02002792/*
2793 * This is a special map_sg function which is used if we should map a
2794 * device which is not handled by an AMD IOMMU in the system.
2795 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002796static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2797 int nelems, int dir)
2798{
2799 struct scatterlist *s;
2800 int i;
2801
2802 for_each_sg(sglist, s, nelems, i) {
2803 s->dma_address = (dma_addr_t)sg_phys(s);
2804 s->dma_length = s->length;
2805 }
2806
2807 return nelems;
2808}
2809
Joerg Roedel431b2a22008-07-11 17:14:22 +02002810/*
2811 * The exported map_sg function for dma_ops (handles scatter-gather
2812 * lists).
2813 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002814static int map_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002815 int nelems, enum dma_data_direction dir,
2816 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002817{
2818 unsigned long flags;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002819 struct protection_domain *domain;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002820 int i;
2821 struct scatterlist *s;
2822 phys_addr_t paddr;
2823 int mapped_elems = 0;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002824 u64 dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002825
Joerg Roedeld03f0672008-12-12 15:09:48 +01002826 INC_STATS_COUNTER(cnt_map_sg);
2827
Joerg Roedel94f6d192009-11-24 16:40:02 +01002828 domain = get_domain(dev);
2829 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002830 return map_sg_no_iommu(dev, sglist, nelems, dir);
Joerg Roedel94f6d192009-11-24 16:40:02 +01002831 else if (IS_ERR(domain))
2832 return 0;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002833
Joerg Roedel832a90c2008-09-18 15:54:23 +02002834 dma_mask = *dev->dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002835
Joerg Roedel65b050a2008-06-26 21:28:02 +02002836 spin_lock_irqsave(&domain->lock, flags);
2837
2838 for_each_sg(sglist, s, nelems, i) {
2839 paddr = sg_phys(s);
2840
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002841 s->dma_address = __map_single(dev, domain->priv,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002842 paddr, s->length, dir, false,
2843 dma_mask);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002844
2845 if (s->dma_address) {
2846 s->dma_length = s->length;
2847 mapped_elems++;
2848 } else
2849 goto unmap;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002850 }
2851
Joerg Roedel17b124b2011-04-06 18:01:35 +02002852 domain_flush_complete(domain);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002853
2854out:
2855 spin_unlock_irqrestore(&domain->lock, flags);
2856
2857 return mapped_elems;
2858unmap:
2859 for_each_sg(sglist, s, mapped_elems, i) {
2860 if (s->dma_address)
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002861 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002862 s->dma_length, dir);
2863 s->dma_address = s->dma_length = 0;
2864 }
2865
2866 mapped_elems = 0;
2867
2868 goto out;
2869}
2870
Joerg Roedel431b2a22008-07-11 17:14:22 +02002871/*
2872 * The exported map_sg function for dma_ops (handles scatter-gather
2873 * lists).
2874 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002875static void unmap_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002876 int nelems, enum dma_data_direction dir,
2877 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002878{
2879 unsigned long flags;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002880 struct protection_domain *domain;
2881 struct scatterlist *s;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002882 int i;
2883
Joerg Roedel55877a62008-12-12 15:12:14 +01002884 INC_STATS_COUNTER(cnt_unmap_sg);
2885
Joerg Roedel94f6d192009-11-24 16:40:02 +01002886 domain = get_domain(dev);
2887 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002888 return;
2889
Joerg Roedel65b050a2008-06-26 21:28:02 +02002890 spin_lock_irqsave(&domain->lock, flags);
2891
2892 for_each_sg(sglist, s, nelems, i) {
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002893 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002894 s->dma_length, dir);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002895 s->dma_address = s->dma_length = 0;
2896 }
2897
Joerg Roedel17b124b2011-04-06 18:01:35 +02002898 domain_flush_complete(domain);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002899
2900 spin_unlock_irqrestore(&domain->lock, flags);
2901}
2902
Joerg Roedel431b2a22008-07-11 17:14:22 +02002903/*
2904 * The exported alloc_coherent function for dma_ops.
2905 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002906static void *alloc_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002907 dma_addr_t *dma_addr, gfp_t flag,
2908 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002909{
2910 unsigned long flags;
2911 void *virt_addr;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002912 struct protection_domain *domain;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002913 phys_addr_t paddr;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002914 u64 dma_mask = dev->coherent_dma_mask;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002915
Joerg Roedelc8f0fb32008-12-12 15:14:21 +01002916 INC_STATS_COUNTER(cnt_alloc_coherent);
2917
Joerg Roedel94f6d192009-11-24 16:40:02 +01002918 domain = get_domain(dev);
2919 if (PTR_ERR(domain) == -EINVAL) {
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002920 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2921 *dma_addr = __pa(virt_addr);
2922 return virt_addr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002923 } else if (IS_ERR(domain))
2924 return NULL;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002925
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002926 dma_mask = dev->coherent_dma_mask;
2927 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2928 flag |= __GFP_ZERO;
FUJITA Tomonori13d9fea2008-09-10 20:19:40 +09002929
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002930 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2931 if (!virt_addr)
Jaswinder Singh Rajputb25ae672009-07-01 19:53:14 +05302932 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002933
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002934 paddr = virt_to_phys(virt_addr);
2935
Joerg Roedel832a90c2008-09-18 15:54:23 +02002936 if (!dma_mask)
2937 dma_mask = *dev->dma_mask;
2938
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002939 spin_lock_irqsave(&domain->lock, flags);
2940
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002941 *dma_addr = __map_single(dev, domain->priv, paddr,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002942 size, DMA_BIDIRECTIONAL, true, dma_mask);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002943
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002944 if (*dma_addr == DMA_ERROR_CODE) {
Jiri Slaby367d04c2009-05-28 09:54:48 +02002945 spin_unlock_irqrestore(&domain->lock, flags);
Joerg Roedel5b28df62008-12-02 17:49:42 +01002946 goto out_free;
Jiri Slaby367d04c2009-05-28 09:54:48 +02002947 }
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002948
Joerg Roedel17b124b2011-04-06 18:01:35 +02002949 domain_flush_complete(domain);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002950
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002951 spin_unlock_irqrestore(&domain->lock, flags);
2952
2953 return virt_addr;
Joerg Roedel5b28df62008-12-02 17:49:42 +01002954
2955out_free:
2956
2957 free_pages((unsigned long)virt_addr, get_order(size));
2958
2959 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002960}
2961
Joerg Roedel431b2a22008-07-11 17:14:22 +02002962/*
2963 * The exported free_coherent function for dma_ops.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002964 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002965static void free_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002966 void *virt_addr, dma_addr_t dma_addr,
2967 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002968{
2969 unsigned long flags;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002970 struct protection_domain *domain;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002971
Joerg Roedel5d31ee72008-12-12 15:16:38 +01002972 INC_STATS_COUNTER(cnt_free_coherent);
2973
Joerg Roedel94f6d192009-11-24 16:40:02 +01002974 domain = get_domain(dev);
2975 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002976 goto free_mem;
2977
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002978 spin_lock_irqsave(&domain->lock, flags);
2979
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002980 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002981
Joerg Roedel17b124b2011-04-06 18:01:35 +02002982 domain_flush_complete(domain);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002983
2984 spin_unlock_irqrestore(&domain->lock, flags);
2985
2986free_mem:
2987 free_pages((unsigned long)virt_addr, get_order(size));
2988}
2989
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002990/*
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002991 * This function is called by the DMA layer to find out if we can handle a
2992 * particular device. It is part of the dma_ops.
2993 */
2994static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2995{
Joerg Roedel420aef82009-11-23 16:14:57 +01002996 return check_device(dev);
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002997}
2998
2999/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02003000 * The function for pre-allocating protection domains.
3001 *
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003002 * If the driver core informs the DMA layer if a driver grabs a device
3003 * we don't need to preallocate the protection domains anymore.
3004 * For now we have to.
3005 */
Steffen Persvold943bc7e2012-03-15 12:16:28 +01003006static void __init prealloc_protection_domains(void)
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003007{
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003008 struct iommu_dev_data *dev_data;
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003009 struct dma_ops_domain *dma_dom;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003010 struct pci_dev *dev = NULL;
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003011 u16 devid;
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003012
Chris Wrightd18c69d2010-04-02 18:27:55 -07003013 for_each_pci_dev(dev) {
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003014
3015 /* Do we handle this device? */
3016 if (!check_device(&dev->dev))
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003017 continue;
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003018
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003019 dev_data = get_dev_data(&dev->dev);
3020 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3021 /* Make sure passthrough domain is allocated */
3022 alloc_passthrough_domain();
3023 dev_data->passthrough = true;
3024 attach_device(&dev->dev, pt_domain);
Frank Arnolddf805ab2012-08-27 19:21:04 +02003025 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003026 dev_name(&dev->dev));
3027 }
3028
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003029 /* Is there already any domain for it? */
Joerg Roedel15898bb2009-11-24 15:39:42 +01003030 if (domain_for_device(&dev->dev))
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003031 continue;
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003032
3033 devid = get_device_id(&dev->dev);
3034
Joerg Roedel87a64d52009-11-24 17:26:43 +01003035 dma_dom = dma_ops_domain_alloc();
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003036 if (!dma_dom)
3037 continue;
3038 init_unity_mappings_for_device(dma_dom, devid);
Joerg Roedelbd60b732008-09-11 10:24:48 +02003039 dma_dom->target_dev = devid;
3040
Joerg Roedel15898bb2009-11-24 15:39:42 +01003041 attach_device(&dev->dev, &dma_dom->domain);
Joerg Roedelbe831292009-11-23 12:50:00 +01003042
Joerg Roedelbd60b732008-09-11 10:24:48 +02003043 list_add_tail(&dma_dom->list, &iommu_pd_list);
Joerg Roedelc432f3d2008-06-26 21:28:04 +02003044 }
3045}
3046
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09003047static struct dma_map_ops amd_iommu_dma_ops = {
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02003048 .alloc = alloc_coherent,
3049 .free = free_coherent,
FUJITA Tomonori51491362009-01-05 23:47:25 +09003050 .map_page = map_page,
3051 .unmap_page = unmap_page,
Joerg Roedel6631ee92008-06-26 21:28:05 +02003052 .map_sg = map_sg,
3053 .unmap_sg = unmap_sg,
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02003054 .dma_supported = amd_iommu_dma_supported,
Joerg Roedel6631ee92008-06-26 21:28:05 +02003055};
3056
Joerg Roedel27c21272011-05-30 15:56:24 +02003057static unsigned device_dma_ops_init(void)
3058{
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003059 struct iommu_dev_data *dev_data;
Joerg Roedel27c21272011-05-30 15:56:24 +02003060 struct pci_dev *pdev = NULL;
3061 unsigned unhandled = 0;
3062
3063 for_each_pci_dev(pdev) {
3064 if (!check_device(&pdev->dev)) {
Joerg Roedelaf1be042012-01-18 14:03:11 +01003065
3066 iommu_ignore_device(&pdev->dev);
3067
Joerg Roedel27c21272011-05-30 15:56:24 +02003068 unhandled += 1;
3069 continue;
3070 }
3071
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003072 dev_data = get_dev_data(&pdev->dev);
3073
3074 if (!dev_data->passthrough)
3075 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3076 else
3077 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
Joerg Roedel27c21272011-05-30 15:56:24 +02003078 }
3079
3080 return unhandled;
3081}
3082
Joerg Roedel431b2a22008-07-11 17:14:22 +02003083/*
3084 * The function which clues the AMD IOMMU driver into dma_ops.
3085 */
Joerg Roedelf5325092010-01-22 17:44:35 +01003086
3087void __init amd_iommu_init_api(void)
3088{
Joerg Roedel2cc21c42011-09-06 17:56:07 +02003089 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
Joerg Roedelf5325092010-01-22 17:44:35 +01003090}
3091
Joerg Roedel6631ee92008-06-26 21:28:05 +02003092int __init amd_iommu_init_dma_ops(void)
3093{
3094 struct amd_iommu *iommu;
Joerg Roedel27c21272011-05-30 15:56:24 +02003095 int ret, unhandled;
Joerg Roedel6631ee92008-06-26 21:28:05 +02003096
Joerg Roedel431b2a22008-07-11 17:14:22 +02003097 /*
3098 * first allocate a default protection domain for every IOMMU we
3099 * found in the system. Devices not assigned to any other
3100 * protection domain will be assigned to the default one.
3101 */
Joerg Roedel3bd22172009-05-04 15:06:20 +02003102 for_each_iommu(iommu) {
Joerg Roedel87a64d52009-11-24 17:26:43 +01003103 iommu->default_dom = dma_ops_domain_alloc();
Joerg Roedel6631ee92008-06-26 21:28:05 +02003104 if (iommu->default_dom == NULL)
3105 return -ENOMEM;
Joerg Roedele2dc14a2008-12-10 18:48:59 +01003106 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
Joerg Roedel6631ee92008-06-26 21:28:05 +02003107 ret = iommu_init_unity_mappings(iommu);
3108 if (ret)
3109 goto free_domains;
3110 }
3111
Joerg Roedel431b2a22008-07-11 17:14:22 +02003112 /*
Joerg Roedel8793abe2009-11-27 11:40:33 +01003113 * Pre-allocate the protection domains for each device.
Joerg Roedel431b2a22008-07-11 17:14:22 +02003114 */
Joerg Roedel8793abe2009-11-27 11:40:33 +01003115 prealloc_protection_domains();
Joerg Roedel6631ee92008-06-26 21:28:05 +02003116
3117 iommu_detected = 1;
FUJITA Tomonori75f1cdf2009-11-10 19:46:20 +09003118 swiotlb = 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02003119
Joerg Roedel431b2a22008-07-11 17:14:22 +02003120 /* Make the driver finally visible to the drivers */
Joerg Roedel27c21272011-05-30 15:56:24 +02003121 unhandled = device_dma_ops_init();
3122 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3123 /* There are unhandled devices - initialize swiotlb for them */
3124 swiotlb = 1;
3125 }
Joerg Roedel6631ee92008-06-26 21:28:05 +02003126
Joerg Roedel7f265082008-12-12 13:50:21 +01003127 amd_iommu_stats_init();
3128
Joerg Roedel62410ee2012-06-12 16:42:43 +02003129 if (amd_iommu_unmap_flush)
3130 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3131 else
3132 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3133
Joerg Roedel6631ee92008-06-26 21:28:05 +02003134 return 0;
3135
3136free_domains:
3137
Joerg Roedel3bd22172009-05-04 15:06:20 +02003138 for_each_iommu(iommu) {
Joerg Roedel6631ee92008-06-26 21:28:05 +02003139 if (iommu->default_dom)
3140 dma_ops_domain_free(iommu->default_dom);
3141 }
3142
3143 return ret;
3144}
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003145
3146/*****************************************************************************
3147 *
3148 * The following functions belong to the exported interface of AMD IOMMU
3149 *
3150 * This interface allows access to lower level functions of the IOMMU
3151 * like protection domain handling and assignement of devices to domains
3152 * which is not possible with the dma_ops interface.
3153 *
3154 *****************************************************************************/
3155
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003156static void cleanup_domain(struct protection_domain *domain)
3157{
Joerg Roedel492667d2009-11-27 13:25:47 +01003158 struct iommu_dev_data *dev_data, *next;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003159 unsigned long flags;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003160
3161 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3162
Joerg Roedel492667d2009-11-27 13:25:47 +01003163 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
Joerg Roedelec9e79e2011-06-09 17:25:50 +02003164 __detach_device(dev_data);
Joerg Roedel492667d2009-11-27 13:25:47 +01003165 atomic_set(&dev_data->bind, 0);
3166 }
Joerg Roedel6d98cd82008-12-08 12:05:55 +01003167
3168 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3169}
3170
Joerg Roedel26508152009-08-26 16:52:40 +02003171static void protection_domain_free(struct protection_domain *domain)
3172{
3173 if (!domain)
3174 return;
3175
Joerg Roedelaeb26f52009-11-20 16:44:01 +01003176 del_domain_from_list(domain);
3177
Joerg Roedel26508152009-08-26 16:52:40 +02003178 if (domain->id)
3179 domain_id_free(domain->id);
3180
3181 kfree(domain);
3182}
3183
3184static struct protection_domain *protection_domain_alloc(void)
Joerg Roedelc156e342008-12-02 18:13:27 +01003185{
3186 struct protection_domain *domain;
3187
3188 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3189 if (!domain)
Joerg Roedel26508152009-08-26 16:52:40 +02003190 return NULL;
Joerg Roedelc156e342008-12-02 18:13:27 +01003191
3192 spin_lock_init(&domain->lock);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003193 mutex_init(&domain->api_lock);
Joerg Roedelc156e342008-12-02 18:13:27 +01003194 domain->id = domain_id_alloc();
3195 if (!domain->id)
Joerg Roedel26508152009-08-26 16:52:40 +02003196 goto out_err;
Joerg Roedel7c392cb2009-11-26 11:13:32 +01003197 INIT_LIST_HEAD(&domain->dev_list);
Joerg Roedel26508152009-08-26 16:52:40 +02003198
Joerg Roedelaeb26f52009-11-20 16:44:01 +01003199 add_domain_to_list(domain);
3200
Joerg Roedel26508152009-08-26 16:52:40 +02003201 return domain;
3202
3203out_err:
3204 kfree(domain);
3205
3206 return NULL;
3207}
3208
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003209static int __init alloc_passthrough_domain(void)
3210{
3211 if (pt_domain != NULL)
3212 return 0;
3213
3214 /* allocate passthrough domain */
3215 pt_domain = protection_domain_alloc();
3216 if (!pt_domain)
3217 return -ENOMEM;
3218
3219 pt_domain->mode = PAGE_MODE_NONE;
3220
3221 return 0;
3222}
Joerg Roedel26508152009-08-26 16:52:40 +02003223static int amd_iommu_domain_init(struct iommu_domain *dom)
3224{
3225 struct protection_domain *domain;
3226
3227 domain = protection_domain_alloc();
3228 if (!domain)
Joerg Roedelc156e342008-12-02 18:13:27 +01003229 goto out_free;
Joerg Roedel26508152009-08-26 16:52:40 +02003230
3231 domain->mode = PAGE_MODE_3_LEVEL;
Joerg Roedelc156e342008-12-02 18:13:27 +01003232 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3233 if (!domain->pt_root)
3234 goto out_free;
3235
Joerg Roedelf3572db2011-11-23 12:36:25 +01003236 domain->iommu_domain = dom;
3237
Joerg Roedelc156e342008-12-02 18:13:27 +01003238 dom->priv = domain;
3239
Joerg Roedel0ff64f82012-01-26 19:40:53 +01003240 dom->geometry.aperture_start = 0;
3241 dom->geometry.aperture_end = ~0ULL;
3242 dom->geometry.force_aperture = true;
3243
Joerg Roedelc156e342008-12-02 18:13:27 +01003244 return 0;
3245
3246out_free:
Joerg Roedel26508152009-08-26 16:52:40 +02003247 protection_domain_free(domain);
Joerg Roedelc156e342008-12-02 18:13:27 +01003248
3249 return -ENOMEM;
3250}
3251
Joerg Roedel98383fc2008-12-02 18:34:12 +01003252static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3253{
3254 struct protection_domain *domain = dom->priv;
3255
3256 if (!domain)
3257 return;
3258
3259 if (domain->dev_cnt > 0)
3260 cleanup_domain(domain);
3261
3262 BUG_ON(domain->dev_cnt != 0);
3263
Joerg Roedel132bd682011-11-17 14:18:46 +01003264 if (domain->mode != PAGE_MODE_NONE)
3265 free_pagetable(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003266
Joerg Roedel52815b72011-11-17 17:24:28 +01003267 if (domain->flags & PD_IOMMUV2_MASK)
3268 free_gcr3_table(domain);
3269
Joerg Roedel8b408fe2010-03-08 14:20:07 +01003270 protection_domain_free(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003271
3272 dom->priv = NULL;
3273}
3274
Joerg Roedel684f2882008-12-08 12:07:44 +01003275static void amd_iommu_detach_device(struct iommu_domain *dom,
3276 struct device *dev)
3277{
Joerg Roedel657cbb62009-11-23 15:26:46 +01003278 struct iommu_dev_data *dev_data = dev->archdata.iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01003279 struct amd_iommu *iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01003280 u16 devid;
3281
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003282 if (!check_device(dev))
Joerg Roedel684f2882008-12-08 12:07:44 +01003283 return;
3284
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003285 devid = get_device_id(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01003286
Joerg Roedel657cbb62009-11-23 15:26:46 +01003287 if (dev_data->domain != NULL)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003288 detach_device(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01003289
3290 iommu = amd_iommu_rlookup_table[devid];
3291 if (!iommu)
3292 return;
3293
Joerg Roedel684f2882008-12-08 12:07:44 +01003294 iommu_completion_wait(iommu);
3295}
3296
Joerg Roedel01106062008-12-02 19:34:11 +01003297static int amd_iommu_attach_device(struct iommu_domain *dom,
3298 struct device *dev)
3299{
3300 struct protection_domain *domain = dom->priv;
Joerg Roedel657cbb62009-11-23 15:26:46 +01003301 struct iommu_dev_data *dev_data;
Joerg Roedel01106062008-12-02 19:34:11 +01003302 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01003303 int ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003304
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003305 if (!check_device(dev))
Joerg Roedel01106062008-12-02 19:34:11 +01003306 return -EINVAL;
3307
Joerg Roedel657cbb62009-11-23 15:26:46 +01003308 dev_data = dev->archdata.iommu;
3309
Joerg Roedelf62dda62011-06-09 12:55:35 +02003310 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel01106062008-12-02 19:34:11 +01003311 if (!iommu)
3312 return -EINVAL;
3313
Joerg Roedel657cbb62009-11-23 15:26:46 +01003314 if (dev_data->domain)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003315 detach_device(dev);
Joerg Roedel01106062008-12-02 19:34:11 +01003316
Joerg Roedel15898bb2009-11-24 15:39:42 +01003317 ret = attach_device(dev, domain);
Joerg Roedel01106062008-12-02 19:34:11 +01003318
3319 iommu_completion_wait(iommu);
3320
Joerg Roedel15898bb2009-11-24 15:39:42 +01003321 return ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003322}
3323
Joerg Roedel468e2362010-01-21 16:37:36 +01003324static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003325 phys_addr_t paddr, size_t page_size, int iommu_prot)
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003326{
3327 struct protection_domain *domain = dom->priv;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003328 int prot = 0;
3329 int ret;
3330
Joerg Roedel132bd682011-11-17 14:18:46 +01003331 if (domain->mode == PAGE_MODE_NONE)
3332 return -EINVAL;
3333
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003334 if (iommu_prot & IOMMU_READ)
3335 prot |= IOMMU_PROT_IR;
3336 if (iommu_prot & IOMMU_WRITE)
3337 prot |= IOMMU_PROT_IW;
3338
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003339 mutex_lock(&domain->api_lock);
Joerg Roedel795e74f72010-05-11 17:40:57 +02003340 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003341 mutex_unlock(&domain->api_lock);
3342
Joerg Roedel795e74f72010-05-11 17:40:57 +02003343 return ret;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003344}
3345
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003346static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3347 size_t page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003348{
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003349 struct protection_domain *domain = dom->priv;
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003350 size_t unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003351
Joerg Roedel132bd682011-11-17 14:18:46 +01003352 if (domain->mode == PAGE_MODE_NONE)
3353 return -EINVAL;
3354
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003355 mutex_lock(&domain->api_lock);
Joerg Roedel468e2362010-01-21 16:37:36 +01003356 unmap_size = iommu_unmap_page(domain, iova, page_size);
Joerg Roedel795e74f72010-05-11 17:40:57 +02003357 mutex_unlock(&domain->api_lock);
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003358
Joerg Roedel17b124b2011-04-06 18:01:35 +02003359 domain_flush_tlb_pde(domain);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003360
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003361 return unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003362}
3363
Joerg Roedel645c4c82008-12-02 20:05:50 +01003364static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3365 unsigned long iova)
3366{
3367 struct protection_domain *domain = dom->priv;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003368 unsigned long offset_mask;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003369 phys_addr_t paddr;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003370 u64 *pte, __pte;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003371
Joerg Roedel132bd682011-11-17 14:18:46 +01003372 if (domain->mode == PAGE_MODE_NONE)
3373 return iova;
3374
Joerg Roedel24cd7722010-01-19 17:27:39 +01003375 pte = fetch_pte(domain, iova);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003376
Joerg Roedela6d41a42009-09-02 17:08:55 +02003377 if (!pte || !IOMMU_PTE_PRESENT(*pte))
Joerg Roedel645c4c82008-12-02 20:05:50 +01003378 return 0;
3379
Joerg Roedelf03152b2010-01-21 16:15:24 +01003380 if (PM_PTE_LEVEL(*pte) == 0)
3381 offset_mask = PAGE_SIZE - 1;
3382 else
3383 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3384
3385 __pte = *pte & PM_ADDR_MASK;
3386 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003387
3388 return paddr;
3389}
3390
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003391static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3392 unsigned long cap)
3393{
Joerg Roedel80a506b2010-07-27 17:14:24 +02003394 switch (cap) {
3395 case IOMMU_CAP_CACHE_COHERENCY:
3396 return 1;
Joerg Roedelbdddadc2012-07-02 18:38:13 +02003397 case IOMMU_CAP_INTR_REMAP:
3398 return irq_remapping_enabled;
Joerg Roedel80a506b2010-07-27 17:14:24 +02003399 }
3400
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003401 return 0;
3402}
3403
Joerg Roedel26961ef2008-12-03 17:00:17 +01003404static struct iommu_ops amd_iommu_ops = {
3405 .domain_init = amd_iommu_domain_init,
3406 .domain_destroy = amd_iommu_domain_destroy,
3407 .attach_dev = amd_iommu_attach_device,
3408 .detach_dev = amd_iommu_detach_device,
Joerg Roedel468e2362010-01-21 16:37:36 +01003409 .map = amd_iommu_map,
3410 .unmap = amd_iommu_unmap,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003411 .iova_to_phys = amd_iommu_iova_to_phys,
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003412 .domain_has_cap = amd_iommu_domain_has_cap,
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +02003413 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003414};
3415
Joerg Roedel0feae532009-08-26 15:26:30 +02003416/*****************************************************************************
3417 *
3418 * The next functions do a basic initialization of IOMMU for pass through
3419 * mode
3420 *
3421 * In passthrough mode the IOMMU is initialized and enabled but not used for
3422 * DMA-API translation.
3423 *
3424 *****************************************************************************/
3425
3426int __init amd_iommu_init_passthrough(void)
3427{
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003428 struct iommu_dev_data *dev_data;
Joerg Roedel0feae532009-08-26 15:26:30 +02003429 struct pci_dev *dev = NULL;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003430 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01003431 u16 devid;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003432 int ret;
Joerg Roedel0feae532009-08-26 15:26:30 +02003433
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003434 ret = alloc_passthrough_domain();
3435 if (ret)
3436 return ret;
Joerg Roedel0feae532009-08-26 15:26:30 +02003437
Kulikov Vasiliy6c54aab2010-07-03 12:03:51 -04003438 for_each_pci_dev(dev) {
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003439 if (!check_device(&dev->dev))
Joerg Roedel0feae532009-08-26 15:26:30 +02003440 continue;
3441
Joerg Roedel5abcdba2011-12-01 15:49:45 +01003442 dev_data = get_dev_data(&dev->dev);
3443 dev_data->passthrough = true;
3444
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003445 devid = get_device_id(&dev->dev);
3446
Joerg Roedel15898bb2009-11-24 15:39:42 +01003447 iommu = amd_iommu_rlookup_table[devid];
Joerg Roedel0feae532009-08-26 15:26:30 +02003448 if (!iommu)
3449 continue;
3450
Joerg Roedel15898bb2009-11-24 15:39:42 +01003451 attach_device(&dev->dev, pt_domain);
Joerg Roedel0feae532009-08-26 15:26:30 +02003452 }
3453
Joerg Roedel2655d7a2011-12-22 12:35:38 +01003454 amd_iommu_stats_init();
3455
Joerg Roedel0feae532009-08-26 15:26:30 +02003456 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3457
3458 return 0;
3459}
Joerg Roedel72e1dcc2011-11-10 19:13:51 +01003460
3461/* IOMMUv2 specific functions */
3462int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3463{
3464 return atomic_notifier_chain_register(&ppr_notifier, nb);
3465}
3466EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3467
3468int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3469{
3470 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3471}
3472EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
Joerg Roedel132bd682011-11-17 14:18:46 +01003473
3474void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3475{
3476 struct protection_domain *domain = dom->priv;
3477 unsigned long flags;
3478
3479 spin_lock_irqsave(&domain->lock, flags);
3480
3481 /* Update data structure */
3482 domain->mode = PAGE_MODE_NONE;
3483 domain->updated = true;
3484
3485 /* Make changes visible to IOMMUs */
3486 update_domain(domain);
3487
3488 /* Page-table is not visible to IOMMU anymore, so free it */
3489 free_pagetable(domain);
3490
3491 spin_unlock_irqrestore(&domain->lock, flags);
3492}
3493EXPORT_SYMBOL(amd_iommu_domain_direct_map);
Joerg Roedel52815b72011-11-17 17:24:28 +01003494
3495int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3496{
3497 struct protection_domain *domain = dom->priv;
3498 unsigned long flags;
3499 int levels, ret;
3500
3501 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3502 return -EINVAL;
3503
3504 /* Number of GCR3 table levels required */
3505 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3506 levels += 1;
3507
3508 if (levels > amd_iommu_max_glx_val)
3509 return -EINVAL;
3510
3511 spin_lock_irqsave(&domain->lock, flags);
3512
3513 /*
3514 * Save us all sanity checks whether devices already in the
3515 * domain support IOMMUv2. Just force that the domain has no
3516 * devices attached when it is switched into IOMMUv2 mode.
3517 */
3518 ret = -EBUSY;
3519 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3520 goto out;
3521
3522 ret = -ENOMEM;
3523 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3524 if (domain->gcr3_tbl == NULL)
3525 goto out;
3526
3527 domain->glx = levels;
3528 domain->flags |= PD_IOMMUV2_MASK;
3529 domain->updated = true;
3530
3531 update_domain(domain);
3532
3533 ret = 0;
3534
3535out:
3536 spin_unlock_irqrestore(&domain->lock, flags);
3537
3538 return ret;
3539}
3540EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003541
3542static int __flush_pasid(struct protection_domain *domain, int pasid,
3543 u64 address, bool size)
3544{
3545 struct iommu_dev_data *dev_data;
3546 struct iommu_cmd cmd;
3547 int i, ret;
3548
3549 if (!(domain->flags & PD_IOMMUV2_MASK))
3550 return -EINVAL;
3551
3552 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3553
3554 /*
3555 * IOMMU TLB needs to be flushed before Device TLB to
3556 * prevent device TLB refill from IOMMU TLB
3557 */
3558 for (i = 0; i < amd_iommus_present; ++i) {
3559 if (domain->dev_iommu[i] == 0)
3560 continue;
3561
3562 ret = iommu_queue_command(amd_iommus[i], &cmd);
3563 if (ret != 0)
3564 goto out;
3565 }
3566
3567 /* Wait until IOMMU TLB flushes are complete */
3568 domain_flush_complete(domain);
3569
3570 /* Now flush device TLBs */
3571 list_for_each_entry(dev_data, &domain->dev_list, list) {
3572 struct amd_iommu *iommu;
3573 int qdep;
3574
3575 BUG_ON(!dev_data->ats.enabled);
3576
3577 qdep = dev_data->ats.qdep;
3578 iommu = amd_iommu_rlookup_table[dev_data->devid];
3579
3580 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3581 qdep, address, size);
3582
3583 ret = iommu_queue_command(iommu, &cmd);
3584 if (ret != 0)
3585 goto out;
3586 }
3587
3588 /* Wait until all device TLBs are flushed */
3589 domain_flush_complete(domain);
3590
3591 ret = 0;
3592
3593out:
3594
3595 return ret;
3596}
3597
3598static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3599 u64 address)
3600{
Joerg Roedel399be2f2011-12-01 16:53:47 +01003601 INC_STATS_COUNTER(invalidate_iotlb);
3602
Joerg Roedel22e266c2011-11-21 15:59:08 +01003603 return __flush_pasid(domain, pasid, address, false);
3604}
3605
3606int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3607 u64 address)
3608{
3609 struct protection_domain *domain = dom->priv;
3610 unsigned long flags;
3611 int ret;
3612
3613 spin_lock_irqsave(&domain->lock, flags);
3614 ret = __amd_iommu_flush_page(domain, pasid, address);
3615 spin_unlock_irqrestore(&domain->lock, flags);
3616
3617 return ret;
3618}
3619EXPORT_SYMBOL(amd_iommu_flush_page);
3620
3621static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3622{
Joerg Roedel399be2f2011-12-01 16:53:47 +01003623 INC_STATS_COUNTER(invalidate_iotlb_all);
3624
Joerg Roedel22e266c2011-11-21 15:59:08 +01003625 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3626 true);
3627}
3628
3629int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3630{
3631 struct protection_domain *domain = dom->priv;
3632 unsigned long flags;
3633 int ret;
3634
3635 spin_lock_irqsave(&domain->lock, flags);
3636 ret = __amd_iommu_flush_tlb(domain, pasid);
3637 spin_unlock_irqrestore(&domain->lock, flags);
3638
3639 return ret;
3640}
3641EXPORT_SYMBOL(amd_iommu_flush_tlb);
3642
Joerg Roedelb16137b2011-11-21 16:50:23 +01003643static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3644{
3645 int index;
3646 u64 *pte;
3647
3648 while (true) {
3649
3650 index = (pasid >> (9 * level)) & 0x1ff;
3651 pte = &root[index];
3652
3653 if (level == 0)
3654 break;
3655
3656 if (!(*pte & GCR3_VALID)) {
3657 if (!alloc)
3658 return NULL;
3659
3660 root = (void *)get_zeroed_page(GFP_ATOMIC);
3661 if (root == NULL)
3662 return NULL;
3663
3664 *pte = __pa(root) | GCR3_VALID;
3665 }
3666
3667 root = __va(*pte & PAGE_MASK);
3668
3669 level -= 1;
3670 }
3671
3672 return pte;
3673}
3674
3675static int __set_gcr3(struct protection_domain *domain, int pasid,
3676 unsigned long cr3)
3677{
3678 u64 *pte;
3679
3680 if (domain->mode != PAGE_MODE_NONE)
3681 return -EINVAL;
3682
3683 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3684 if (pte == NULL)
3685 return -ENOMEM;
3686
3687 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3688
3689 return __amd_iommu_flush_tlb(domain, pasid);
3690}
3691
3692static int __clear_gcr3(struct protection_domain *domain, int pasid)
3693{
3694 u64 *pte;
3695
3696 if (domain->mode != PAGE_MODE_NONE)
3697 return -EINVAL;
3698
3699 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3700 if (pte == NULL)
3701 return 0;
3702
3703 *pte = 0;
3704
3705 return __amd_iommu_flush_tlb(domain, pasid);
3706}
3707
3708int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3709 unsigned long cr3)
3710{
3711 struct protection_domain *domain = dom->priv;
3712 unsigned long flags;
3713 int ret;
3714
3715 spin_lock_irqsave(&domain->lock, flags);
3716 ret = __set_gcr3(domain, pasid, cr3);
3717 spin_unlock_irqrestore(&domain->lock, flags);
3718
3719 return ret;
3720}
3721EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3722
3723int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3724{
3725 struct protection_domain *domain = dom->priv;
3726 unsigned long flags;
3727 int ret;
3728
3729 spin_lock_irqsave(&domain->lock, flags);
3730 ret = __clear_gcr3(domain, pasid);
3731 spin_unlock_irqrestore(&domain->lock, flags);
3732
3733 return ret;
3734}
3735EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
Joerg Roedelc99afa22011-11-21 18:19:25 +01003736
3737int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3738 int status, int tag)
3739{
3740 struct iommu_dev_data *dev_data;
3741 struct amd_iommu *iommu;
3742 struct iommu_cmd cmd;
3743
Joerg Roedel399be2f2011-12-01 16:53:47 +01003744 INC_STATS_COUNTER(complete_ppr);
3745
Joerg Roedelc99afa22011-11-21 18:19:25 +01003746 dev_data = get_dev_data(&pdev->dev);
3747 iommu = amd_iommu_rlookup_table[dev_data->devid];
3748
3749 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3750 tag, dev_data->pri_tlp);
3751
3752 return iommu_queue_command(iommu, &cmd);
3753}
3754EXPORT_SYMBOL(amd_iommu_complete_ppr);
Joerg Roedelf3572db2011-11-23 12:36:25 +01003755
3756struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3757{
3758 struct protection_domain *domain;
3759
3760 domain = get_domain(&pdev->dev);
3761 if (IS_ERR(domain))
3762 return NULL;
3763
3764 /* Only return IOMMUv2 domains */
3765 if (!(domain->flags & PD_IOMMUV2_MASK))
3766 return NULL;
3767
3768 return domain->iommu_domain;
3769}
3770EXPORT_SYMBOL(amd_iommu_get_v2_domain);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01003771
3772void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3773{
3774 struct iommu_dev_data *dev_data;
3775
3776 if (!amd_iommu_v2_supported())
3777 return;
3778
3779 dev_data = get_dev_data(&pdev->dev);
3780 dev_data->errata |= (1 << erratum);
3781}
3782EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
Joerg Roedel52efdb82011-12-07 12:01:36 +01003783
3784int amd_iommu_device_info(struct pci_dev *pdev,
3785 struct amd_iommu_device_info *info)
3786{
3787 int max_pasids;
3788 int pos;
3789
3790 if (pdev == NULL || info == NULL)
3791 return -EINVAL;
3792
3793 if (!amd_iommu_v2_supported())
3794 return -EINVAL;
3795
3796 memset(info, 0, sizeof(*info));
3797
3798 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3799 if (pos)
3800 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3801
3802 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3803 if (pos)
3804 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3805
3806 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3807 if (pos) {
3808 int features;
3809
3810 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3811 max_pasids = min(max_pasids, (1 << 20));
3812
3813 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3814 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3815
3816 features = pci_pasid_features(pdev);
3817 if (features & PCI_PASID_CAP_EXEC)
3818 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3819 if (features & PCI_PASID_CAP_PRIV)
3820 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3821 }
3822
3823 return 0;
3824}
3825EXPORT_SYMBOL(amd_iommu_device_info);
Joerg Roedel2b324502012-06-21 16:29:10 +02003826
3827#ifdef CONFIG_IRQ_REMAP
3828
3829/*****************************************************************************
3830 *
3831 * Interrupt Remapping Implementation
3832 *
3833 *****************************************************************************/
3834
3835union irte {
3836 u32 val;
3837 struct {
3838 u32 valid : 1,
3839 no_fault : 1,
3840 int_type : 3,
3841 rq_eoi : 1,
3842 dm : 1,
3843 rsvd_1 : 1,
3844 destination : 8,
3845 vector : 8,
3846 rsvd_2 : 8;
3847 } fields;
3848};
3849
3850#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3851#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3852#define DTE_IRQ_TABLE_LEN (8ULL << 1)
3853#define DTE_IRQ_REMAP_ENABLE 1ULL
3854
3855static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3856{
3857 u64 dte;
3858
3859 dte = amd_iommu_dev_table[devid].data[2];
3860 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3861 dte |= virt_to_phys(table->table);
3862 dte |= DTE_IRQ_REMAP_INTCTL;
3863 dte |= DTE_IRQ_TABLE_LEN;
3864 dte |= DTE_IRQ_REMAP_ENABLE;
3865
3866 amd_iommu_dev_table[devid].data[2] = dte;
3867}
3868
3869#define IRTE_ALLOCATED (~1U)
3870
3871static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3872{
3873 struct irq_remap_table *table = NULL;
3874 struct amd_iommu *iommu;
3875 unsigned long flags;
3876 u16 alias;
3877
3878 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3879
3880 iommu = amd_iommu_rlookup_table[devid];
3881 if (!iommu)
3882 goto out_unlock;
3883
3884 table = irq_lookup_table[devid];
3885 if (table)
3886 goto out;
3887
3888 alias = amd_iommu_alias_table[devid];
3889 table = irq_lookup_table[alias];
3890 if (table) {
3891 irq_lookup_table[devid] = table;
3892 set_dte_irq_entry(devid, table);
3893 iommu_flush_dte(iommu, devid);
3894 goto out;
3895 }
3896
3897 /* Nothing there yet, allocate new irq remapping table */
3898 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3899 if (!table)
3900 goto out;
3901
3902 if (ioapic)
3903 /* Keep the first 32 indexes free for IOAPIC interrupts */
3904 table->min_index = 32;
3905
3906 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3907 if (!table->table) {
3908 kfree(table);
Dan Carpenter821f0f62012-10-02 11:34:40 +03003909 table = NULL;
Joerg Roedel2b324502012-06-21 16:29:10 +02003910 goto out;
3911 }
3912
3913 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3914
3915 if (ioapic) {
3916 int i;
3917
3918 for (i = 0; i < 32; ++i)
3919 table->table[i] = IRTE_ALLOCATED;
3920 }
3921
3922 irq_lookup_table[devid] = table;
3923 set_dte_irq_entry(devid, table);
3924 iommu_flush_dte(iommu, devid);
3925 if (devid != alias) {
3926 irq_lookup_table[alias] = table;
3927 set_dte_irq_entry(devid, table);
3928 iommu_flush_dte(iommu, alias);
3929 }
3930
3931out:
3932 iommu_completion_wait(iommu);
3933
3934out_unlock:
3935 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3936
3937 return table;
3938}
3939
3940static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3941{
3942 struct irq_remap_table *table;
3943 unsigned long flags;
3944 int index, c;
3945
3946 table = get_irq_table(devid, false);
3947 if (!table)
3948 return -ENODEV;
3949
3950 spin_lock_irqsave(&table->lock, flags);
3951
3952 /* Scan table for free entries */
3953 for (c = 0, index = table->min_index;
3954 index < MAX_IRQS_PER_TABLE;
3955 ++index) {
3956 if (table->table[index] == 0)
3957 c += 1;
3958 else
3959 c = 0;
3960
3961 if (c == count) {
3962 struct irq_2_iommu *irte_info;
3963
3964 for (; c != 0; --c)
3965 table->table[index - c + 1] = IRTE_ALLOCATED;
3966
3967 index -= count - 1;
3968
3969 irte_info = &cfg->irq_2_iommu;
3970 irte_info->sub_handle = devid;
3971 irte_info->irte_index = index;
3972 irte_info->iommu = (void *)cfg;
3973
3974 goto out;
3975 }
3976 }
3977
3978 index = -ENOSPC;
3979
3980out:
3981 spin_unlock_irqrestore(&table->lock, flags);
3982
3983 return index;
3984}
3985
3986static int get_irte(u16 devid, int index, union irte *irte)
3987{
3988 struct irq_remap_table *table;
3989 unsigned long flags;
3990
3991 table = get_irq_table(devid, false);
3992 if (!table)
3993 return -ENOMEM;
3994
3995 spin_lock_irqsave(&table->lock, flags);
3996 irte->val = table->table[index];
3997 spin_unlock_irqrestore(&table->lock, flags);
3998
3999 return 0;
4000}
4001
4002static int modify_irte(u16 devid, int index, union irte irte)
4003{
4004 struct irq_remap_table *table;
4005 struct amd_iommu *iommu;
4006 unsigned long flags;
4007
4008 iommu = amd_iommu_rlookup_table[devid];
4009 if (iommu == NULL)
4010 return -EINVAL;
4011
4012 table = get_irq_table(devid, false);
4013 if (!table)
4014 return -ENOMEM;
4015
4016 spin_lock_irqsave(&table->lock, flags);
4017 table->table[index] = irte.val;
4018 spin_unlock_irqrestore(&table->lock, flags);
4019
4020 iommu_flush_irt(iommu, devid);
4021 iommu_completion_wait(iommu);
4022
4023 return 0;
4024}
4025
4026static void free_irte(u16 devid, int index)
4027{
4028 struct irq_remap_table *table;
4029 struct amd_iommu *iommu;
4030 unsigned long flags;
4031
4032 iommu = amd_iommu_rlookup_table[devid];
4033 if (iommu == NULL)
4034 return;
4035
4036 table = get_irq_table(devid, false);
4037 if (!table)
4038 return;
4039
4040 spin_lock_irqsave(&table->lock, flags);
4041 table->table[index] = 0;
4042 spin_unlock_irqrestore(&table->lock, flags);
4043
4044 iommu_flush_irt(iommu, devid);
4045 iommu_completion_wait(iommu);
4046}
4047
Joerg Roedel5527de72012-06-26 11:17:32 +02004048static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4049 unsigned int destination, int vector,
4050 struct io_apic_irq_attr *attr)
4051{
4052 struct irq_remap_table *table;
4053 struct irq_2_iommu *irte_info;
4054 struct irq_cfg *cfg;
4055 union irte irte;
4056 int ioapic_id;
4057 int index;
4058 int devid;
4059 int ret;
4060
4061 cfg = irq_get_chip_data(irq);
4062 if (!cfg)
4063 return -EINVAL;
4064
4065 irte_info = &cfg->irq_2_iommu;
4066 ioapic_id = mpc_ioapic_id(attr->ioapic);
4067 devid = get_ioapic_devid(ioapic_id);
4068
4069 if (devid < 0)
4070 return devid;
4071
4072 table = get_irq_table(devid, true);
4073 if (table == NULL)
4074 return -ENOMEM;
4075
4076 index = attr->ioapic_pin;
4077
4078 /* Setup IRQ remapping info */
4079 irte_info->sub_handle = devid;
4080 irte_info->irte_index = index;
4081 irte_info->iommu = (void *)cfg;
4082
4083 /* Setup IRTE for IOMMU */
4084 irte.val = 0;
4085 irte.fields.vector = vector;
4086 irte.fields.int_type = apic->irq_delivery_mode;
4087 irte.fields.destination = destination;
4088 irte.fields.dm = apic->irq_dest_mode;
4089 irte.fields.valid = 1;
4090
4091 ret = modify_irte(devid, index, irte);
4092 if (ret)
4093 return ret;
4094
4095 /* Setup IOAPIC entry */
4096 memset(entry, 0, sizeof(*entry));
4097
4098 entry->vector = index;
4099 entry->mask = 0;
4100 entry->trigger = attr->trigger;
4101 entry->polarity = attr->polarity;
4102
4103 /*
4104 * Mask level triggered irqs.
Joerg Roedel5527de72012-06-26 11:17:32 +02004105 */
4106 if (attr->trigger)
4107 entry->mask = 1;
4108
4109 return 0;
4110}
4111
4112static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4113 bool force)
4114{
4115 struct irq_2_iommu *irte_info;
4116 unsigned int dest, irq;
4117 struct irq_cfg *cfg;
4118 union irte irte;
4119 int err;
4120
4121 if (!config_enabled(CONFIG_SMP))
4122 return -1;
4123
4124 cfg = data->chip_data;
4125 irq = data->irq;
4126 irte_info = &cfg->irq_2_iommu;
4127
4128 if (!cpumask_intersects(mask, cpu_online_mask))
4129 return -EINVAL;
4130
4131 if (get_irte(irte_info->sub_handle, irte_info->irte_index, &irte))
4132 return -EBUSY;
4133
4134 if (assign_irq_vector(irq, cfg, mask))
4135 return -EBUSY;
4136
4137 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4138 if (err) {
4139 if (assign_irq_vector(irq, cfg, data->affinity))
4140 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4141 return err;
4142 }
4143
4144 irte.fields.vector = cfg->vector;
4145 irte.fields.destination = dest;
4146
4147 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
4148
4149 if (cfg->move_in_progress)
4150 send_cleanup_vector(cfg);
4151
4152 cpumask_copy(data->affinity, mask);
4153
4154 return 0;
4155}
4156
4157static int free_irq(int irq)
4158{
4159 struct irq_2_iommu *irte_info;
4160 struct irq_cfg *cfg;
4161
4162 cfg = irq_get_chip_data(irq);
4163 if (!cfg)
4164 return -EINVAL;
4165
4166 irte_info = &cfg->irq_2_iommu;
4167
4168 free_irte(irte_info->sub_handle, irte_info->irte_index);
4169
4170 return 0;
4171}
4172
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004173static void compose_msi_msg(struct pci_dev *pdev,
4174 unsigned int irq, unsigned int dest,
4175 struct msi_msg *msg, u8 hpet_id)
4176{
4177 struct irq_2_iommu *irte_info;
4178 struct irq_cfg *cfg;
4179 union irte irte;
4180
4181 cfg = irq_get_chip_data(irq);
4182 if (!cfg)
4183 return;
4184
4185 irte_info = &cfg->irq_2_iommu;
4186
4187 irte.val = 0;
4188 irte.fields.vector = cfg->vector;
4189 irte.fields.int_type = apic->irq_delivery_mode;
4190 irte.fields.destination = dest;
4191 irte.fields.dm = apic->irq_dest_mode;
4192 irte.fields.valid = 1;
4193
4194 modify_irte(irte_info->sub_handle, irte_info->irte_index, irte);
4195
4196 msg->address_hi = MSI_ADDR_BASE_HI;
4197 msg->address_lo = MSI_ADDR_BASE_LO;
4198 msg->data = irte_info->irte_index;
4199}
4200
4201static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4202{
4203 struct irq_cfg *cfg;
4204 int index;
4205 u16 devid;
4206
4207 if (!pdev)
4208 return -EINVAL;
4209
4210 cfg = irq_get_chip_data(irq);
4211 if (!cfg)
4212 return -EINVAL;
4213
4214 devid = get_device_id(&pdev->dev);
4215 index = alloc_irq_index(cfg, devid, nvec);
4216
4217 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4218}
4219
4220static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4221 int index, int offset)
4222{
4223 struct irq_2_iommu *irte_info;
4224 struct irq_cfg *cfg;
4225 u16 devid;
4226
4227 if (!pdev)
4228 return -EINVAL;
4229
4230 cfg = irq_get_chip_data(irq);
4231 if (!cfg)
4232 return -EINVAL;
4233
4234 if (index >= MAX_IRQS_PER_TABLE)
4235 return 0;
4236
4237 devid = get_device_id(&pdev->dev);
4238 irte_info = &cfg->irq_2_iommu;
4239
4240 irte_info->sub_handle = devid;
4241 irte_info->irte_index = index + offset;
4242 irte_info->iommu = (void *)cfg;
4243
4244 return 0;
4245}
4246
Joerg Roedeld9761952012-06-26 16:00:08 +02004247static int setup_hpet_msi(unsigned int irq, unsigned int id)
4248{
4249 struct irq_2_iommu *irte_info;
4250 struct irq_cfg *cfg;
4251 int index, devid;
4252
4253 cfg = irq_get_chip_data(irq);
4254 if (!cfg)
4255 return -EINVAL;
4256
4257 irte_info = &cfg->irq_2_iommu;
4258 devid = get_hpet_devid(id);
4259 if (devid < 0)
4260 return devid;
4261
4262 index = alloc_irq_index(cfg, devid, 1);
4263 if (index < 0)
4264 return index;
4265
4266 irte_info->sub_handle = devid;
4267 irte_info->irte_index = index;
4268 irte_info->iommu = (void *)cfg;
4269
4270 return 0;
4271}
4272
Joerg Roedel6b474b82012-06-26 16:46:04 +02004273struct irq_remap_ops amd_iommu_irq_ops = {
4274 .supported = amd_iommu_supported,
4275 .prepare = amd_iommu_prepare,
4276 .enable = amd_iommu_enable,
4277 .disable = amd_iommu_disable,
4278 .reenable = amd_iommu_reenable,
4279 .enable_faulting = amd_iommu_enable_faulting,
4280 .setup_ioapic_entry = setup_ioapic_entry,
4281 .set_affinity = set_affinity,
4282 .free_irq = free_irq,
4283 .compose_msi_msg = compose_msi_msg,
4284 .msi_alloc_irq = msi_alloc_irq,
4285 .msi_setup_irq = msi_setup_irq,
4286 .setup_hpet_msi = setup_hpet_msi,
4287};
Joerg Roedel2b324502012-06-21 16:29:10 +02004288#endif