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Maxime Ripardb2ac5d72012-11-12 15:07:50 +01001/*
2 * Allwinner A1X SoCs timer handling.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqreturn.h>
Maxime Ripard137c6b32013-07-16 16:45:37 +020022#include <linux/sched_clock.h>
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010023#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010026
Maxime Ripard04981732013-03-10 17:03:46 +010027#define TIMER_IRQ_EN_REG 0x00
Maxime Ripard40777642013-07-16 16:45:37 +020028#define TIMER_IRQ_EN(val) BIT(val)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010029#define TIMER_IRQ_ST_REG 0x04
Maxime Ripard04981732013-03-10 17:03:46 +010030#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
Maxime Ripard40777642013-07-16 16:45:37 +020031#define TIMER_CTL_ENABLE BIT(0)
Maxime Ripard9eded232013-07-16 16:45:37 +020032#define TIMER_CTL_RELOAD BIT(1)
Maxime Ripard40777642013-07-16 16:45:37 +020033#define TIMER_CTL_ONESHOT BIT(7)
Maxime Ripardbb008b92013-07-16 16:45:37 +020034#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
35#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010036
37#define TIMER_SCAL 16
38
39static void __iomem *timer_base;
40
Maxime Ripard63d88f12013-07-16 16:45:38 +020041/*
42 * When we disable a timer, we need to wait at least for 2 cycles of
43 * the timer source clock. We will use for that the clocksource timer
44 * that is already setup and runs at the same frequency than the other
45 * timers, and we never will be disabled.
46 */
47static void sun4i_clkevt_sync(void)
48{
49 u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
50
51 while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
52 cpu_relax();
53}
54
Maxime Ripard96651a02013-07-16 16:45:38 +020055static void sun4i_clkevt_time_stop(u8 timer)
56{
57 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
58 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
59 sun4i_clkevt_sync();
60}
61
62static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
63{
64 writel(delay, timer_base + TIMER_INTVAL_REG(timer));
65}
66
67static void sun4i_clkevt_time_start(u8 timer, bool periodic)
68{
69 u32 val = readl(timer_base + TIMER_CTL_REG(timer));
70
71 if (periodic)
72 val &= ~TIMER_CTL_ONESHOT;
73 else
74 val |= TIMER_CTL_ONESHOT;
75
76 writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
77}
78
Maxime Ripard119fd632013-03-24 11:49:25 +010079static void sun4i_clkevt_mode(enum clock_event_mode mode,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010080 struct clock_event_device *clk)
81{
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010082 switch (mode) {
83 case CLOCK_EVT_MODE_PERIODIC:
Maxime Ripard96651a02013-07-16 16:45:38 +020084 sun4i_clkevt_time_stop(0);
85 sun4i_clkevt_time_start(0, true);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010086 break;
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010087 case CLOCK_EVT_MODE_ONESHOT:
Maxime Ripard96651a02013-07-16 16:45:38 +020088 sun4i_clkevt_time_stop(0);
89 sun4i_clkevt_time_start(0, false);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010090 break;
91 case CLOCK_EVT_MODE_UNUSED:
92 case CLOCK_EVT_MODE_SHUTDOWN:
93 default:
Maxime Ripard96651a02013-07-16 16:45:38 +020094 sun4i_clkevt_time_stop(0);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +010095 break;
96 }
97}
98
Maxime Ripard119fd632013-03-24 11:49:25 +010099static int sun4i_clkevt_next_event(unsigned long evt,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100100 struct clock_event_device *unused)
101{
Maxime Ripard96651a02013-07-16 16:45:38 +0200102 sun4i_clkevt_time_stop(0);
103 sun4i_clkevt_time_setup(0, evt);
104 sun4i_clkevt_time_start(0, false);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100105
106 return 0;
107}
108
Maxime Ripard119fd632013-03-24 11:49:25 +0100109static struct clock_event_device sun4i_clockevent = {
110 .name = "sun4i_tick",
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100111 .rating = 300,
112 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
Maxime Ripard119fd632013-03-24 11:49:25 +0100113 .set_mode = sun4i_clkevt_mode,
114 .set_next_event = sun4i_clkevt_next_event,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100115};
116
117
Maxime Ripard119fd632013-03-24 11:49:25 +0100118static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100119{
120 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
121
122 writel(0x1, timer_base + TIMER_IRQ_ST_REG);
123 evt->event_handler(evt);
124
125 return IRQ_HANDLED;
126}
127
Maxime Ripard119fd632013-03-24 11:49:25 +0100128static struct irqaction sun4i_timer_irq = {
129 .name = "sun4i_timer0",
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100130 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
Maxime Ripard119fd632013-03-24 11:49:25 +0100131 .handler = sun4i_timer_interrupt,
132 .dev_id = &sun4i_clockevent,
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100133};
134
Maxime Ripard137c6b32013-07-16 16:45:37 +0200135static u32 sun4i_timer_sched_read(void)
136{
137 return ~readl(timer_base + TIMER_CNTVAL_REG(1));
138}
139
Maxime Ripard119fd632013-03-24 11:49:25 +0100140static void __init sun4i_timer_init(struct device_node *node)
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100141{
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100142 unsigned long rate = 0;
143 struct clk *clk;
144 int ret, irq;
145 u32 val;
146
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100147 timer_base = of_iomap(node, 0);
148 if (!timer_base)
149 panic("Can't map registers");
150
151 irq = irq_of_parse_and_map(node, 0);
152 if (irq <= 0)
153 panic("Can't parse IRQ");
154
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100155 clk = of_clk_get(node, 0);
156 if (IS_ERR(clk))
157 panic("Can't get timer clock");
Maxime Ripard8c31bec2013-07-16 16:45:38 +0200158 clk_prepare_enable(clk);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100159
160 rate = clk_get_rate(clk);
161
Maxime Ripard137c6b32013-07-16 16:45:37 +0200162 writel(~0, timer_base + TIMER_INTVAL_REG(1));
163 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
164 TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
165 timer_base + TIMER_CTL_REG(1));
166
167 setup_sched_clock(sun4i_timer_sched_read, 32, rate);
168 clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
169 rate, 300, 32, clocksource_mmio_readl_down);
170
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100171 writel(rate / (TIMER_SCAL * HZ),
Maxime Ripard04981732013-03-10 17:03:46 +0100172 timer_base + TIMER_INTVAL_REG(0));
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100173
174 /* set clock source to HOSC, 16 pre-division */
Maxime Ripard04981732013-03-10 17:03:46 +0100175 val = readl(timer_base + TIMER_CTL_REG(0));
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100176 val &= ~(0x07 << 4);
177 val &= ~(0x03 << 2);
178 val |= (4 << 4) | (1 << 2);
Maxime Ripard04981732013-03-10 17:03:46 +0100179 writel(val, timer_base + TIMER_CTL_REG(0));
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100180
181 /* set mode to auto reload */
Maxime Ripard04981732013-03-10 17:03:46 +0100182 val = readl(timer_base + TIMER_CTL_REG(0));
Maxime Ripard9eded232013-07-16 16:45:37 +0200183 writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100184
Maxime Ripard119fd632013-03-24 11:49:25 +0100185 ret = setup_irq(irq, &sun4i_timer_irq);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100186 if (ret)
187 pr_warn("failed to setup irq %d\n", irq);
188
189 /* Enable timer0 interrupt */
Maxime Ripard04981732013-03-10 17:03:46 +0100190 val = readl(timer_base + TIMER_IRQ_EN_REG);
191 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100192
Maxime Ripard119fd632013-03-24 11:49:25 +0100193 sun4i_clockevent.cpumask = cpumask_of(0);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100194
Maxime Ripard119fd632013-03-24 11:49:25 +0100195 clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
Shawn Guo77cc9822013-01-12 11:50:06 +0000196 0x1, 0xff);
Maxime Ripardb2ac5d72012-11-12 15:07:50 +0100197}
Maxime Ripard119fd632013-03-24 11:49:25 +0100198CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
199 sun4i_timer_init);