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Tony Lindgrened1c7de2012-11-02 12:24:06 -07001/*
2 * omap iommu: main structures
3 *
4 * Copyright (C) 2008-2009 Nokia Corporation
5 *
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
Suman Anna533b40c2014-10-22 17:22:22 -050013#ifndef _OMAP_IOMMU_H
14#define _OMAP_IOMMU_H
15
Tony Lindgrened1c7de2012-11-02 12:24:06 -070016#if defined(CONFIG_ARCH_OMAP1)
17#error "iommu for this processor not implemented yet"
18#endif
19
20struct iotlb_entry {
21 u32 da;
22 u32 pa;
23 u32 pgsz, prsvd, valid;
24 union {
25 u16 ap;
26 struct {
27 u32 endian, elsz, mixed;
28 };
29 };
30};
31
32struct omap_iommu {
33 const char *name;
Tony Lindgrened1c7de2012-11-02 12:24:06 -070034 void __iomem *regbase;
35 struct device *dev;
Tony Lindgrened1c7de2012-11-02 12:24:06 -070036 struct iommu_domain *domain;
37
Tony Lindgrened1c7de2012-11-02 12:24:06 -070038 spinlock_t iommu_lock; /* global for this whole object */
39
40 /*
41 * We don't change iopgd for a situation like pgd for a task,
42 * but share it globally for each iommu.
43 */
44 u32 *iopgd;
45 spinlock_t page_table_lock; /* protect iopgd */
46
47 int nr_tlb_entries;
48
Tony Lindgrened1c7de2012-11-02 12:24:06 -070049 void *ctx; /* iommu context: registres saved area */
Suman Annab148d5f2014-02-28 14:42:37 -060050
51 int has_bus_err_back;
Tony Lindgrened1c7de2012-11-02 12:24:06 -070052};
53
54struct cr_regs {
55 union {
56 struct {
57 u16 cam_l;
58 u16 cam_h;
59 };
60 u32 cam;
61 };
62 union {
63 struct {
64 u16 ram_l;
65 u16 ram_h;
66 };
67 u32 ram;
68 };
69};
70
Tony Lindgrened1c7de2012-11-02 12:24:06 -070071/* architecture specific functions */
72struct iommu_functions {
Tony Lindgrened1c7de2012-11-02 12:24:06 -070073 int (*enable)(struct omap_iommu *obj);
74 void (*disable)(struct omap_iommu *obj);
75 void (*set_twl)(struct omap_iommu *obj, bool on);
76 u32 (*fault_isr)(struct omap_iommu *obj, u32 *ra);
77
78 void (*tlb_read_cr)(struct omap_iommu *obj, struct cr_regs *cr);
79 void (*tlb_load_cr)(struct omap_iommu *obj, struct cr_regs *cr);
80
81 struct cr_regs *(*alloc_cr)(struct omap_iommu *obj,
82 struct iotlb_entry *e);
83 int (*cr_valid)(struct cr_regs *cr);
84 u32 (*cr_to_virt)(struct cr_regs *cr);
85 void (*cr_to_e)(struct cr_regs *cr, struct iotlb_entry *e);
86 ssize_t (*dump_cr)(struct omap_iommu *obj, struct cr_regs *cr,
87 char *buf);
88
89 u32 (*get_pte_attr)(struct iotlb_entry *e);
90
91 void (*save_ctx)(struct omap_iommu *obj);
92 void (*restore_ctx)(struct omap_iommu *obj);
93 ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
94};
95
Tony Lindgrened1c7de2012-11-02 12:24:06 -070096/**
97 * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
98 * @dev: iommu client device
99 */
100static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
101{
102 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
103
104 return arch_data->iommu_dev;
105}
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700106
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700107/*
108 * MMU Register offsets
109 */
110#define MMU_REVISION 0x00
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700111#define MMU_IRQSTATUS 0x18
112#define MMU_IRQENABLE 0x1c
113#define MMU_WALKING_ST 0x40
114#define MMU_CNTL 0x44
115#define MMU_FAULT_AD 0x48
116#define MMU_TTB 0x4c
117#define MMU_LOCK 0x50
118#define MMU_LD_TLB 0x54
119#define MMU_CAM 0x58
120#define MMU_RAM 0x5c
121#define MMU_GFLUSH 0x60
122#define MMU_FLUSH_ENTRY 0x64
123#define MMU_READ_CAM 0x68
124#define MMU_READ_RAM 0x6c
125#define MMU_EMU_FAULT_AD 0x70
Suman Annab148d5f2014-02-28 14:42:37 -0600126#define MMU_GP_REG 0x88
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700127
128#define MMU_REG_SIZE 256
129
130/*
131 * MMU Register bit definitions
132 */
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700133#define MMU_CAM_VATAG_SHIFT 12
134#define MMU_CAM_VATAG_MASK \
135 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
136#define MMU_CAM_P (1 << 3)
137#define MMU_CAM_V (1 << 2)
138#define MMU_CAM_PGSZ_MASK 3
139#define MMU_CAM_PGSZ_1M (0 << 0)
140#define MMU_CAM_PGSZ_64K (1 << 0)
141#define MMU_CAM_PGSZ_4K (2 << 0)
142#define MMU_CAM_PGSZ_16M (3 << 0)
143
144#define MMU_RAM_PADDR_SHIFT 12
145#define MMU_RAM_PADDR_MASK \
146 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
147
Laurent Pinchartbaaa7b52014-07-18 12:49:55 +0200148#define MMU_RAM_ENDIAN_SHIFT 9
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700149#define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
Laurent Pinchartbaaa7b52014-07-18 12:49:55 +0200150#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700151#define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
152
Laurent Pinchartbaaa7b52014-07-18 12:49:55 +0200153#define MMU_RAM_ELSZ_SHIFT 7
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700154#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
155#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
156#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
157#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
158#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
159#define MMU_RAM_MIXED_SHIFT 6
160#define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
161#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
162
Suman Annab148d5f2014-02-28 14:42:37 -0600163#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
164
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700165/*
166 * utilities for super page(16MB, 1MB, 64KB and 4KB)
167 */
168
169#define iopgsz_max(bytes) \
170 (((bytes) >= SZ_16M) ? SZ_16M : \
171 ((bytes) >= SZ_1M) ? SZ_1M : \
172 ((bytes) >= SZ_64K) ? SZ_64K : \
173 ((bytes) >= SZ_4K) ? SZ_4K : 0)
174
175#define bytes_to_iopgsz(bytes) \
176 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
177 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
178 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
179 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
180
181#define iopgsz_to_bytes(iopgsz) \
182 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
183 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
184 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
185 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
186
187#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
188
189/*
190 * global functions
191 */
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700192extern void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
193
194extern int
195omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e);
196
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700197extern int omap_foreach_iommu_device(void *data,
198 int (*fn)(struct device *, void *));
199
Ido Yariv7bd9e252012-11-02 12:24:09 -0700200extern int omap_install_iommu_arch(const struct iommu_functions *ops);
201extern void omap_uninstall_iommu_arch(const struct iommu_functions *ops);
202
Tony Lindgrened1c7de2012-11-02 12:24:06 -0700203extern ssize_t
204omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
205extern size_t
206omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
207
208/*
209 * register accessors
210 */
211static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
212{
213 return __raw_readl(obj->regbase + offs);
214}
215
216static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
217{
218 __raw_writel(val, obj->regbase + offs);
219}
Suman Anna533b40c2014-10-22 17:22:22 -0500220
221#endif /* _OMAP_IOMMU_H */