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Stephen Boyddd15ab82011-11-08 10:34:05 -08001/*
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -08002 *
3 * Copyright (C) 2007 Google, Inc.
Kumar Gala3f8e8ce2014-01-29 16:17:30 -06004 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -08005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Stephen Boyd4a184072011-11-08 10:34:04 -080017#include <linux/clocksource.h>
18#include <linux/clockchips.h>
Stephen Boyd4d70c592013-02-15 17:31:31 -080019#include <linux/cpu.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080020#include <linux/init.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080021#include <linux/interrupt.h>
22#include <linux/irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Stephen Boyd6e332162012-09-05 12:28:53 -070024#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070027#include <linux/sched_clock.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080028
Stephen Boyde25e3d12013-03-14 20:31:39 -070029#define TIMER_MATCH_VAL 0x0000
30#define TIMER_COUNT_VAL 0x0004
31#define TIMER_ENABLE 0x0008
32#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
33#define TIMER_ENABLE_EN BIT(0)
34#define TIMER_CLEAR 0x000C
35#define DGT_CLK_CTL 0x10
36#define DGT_CLK_CTL_DIV_4 0x3
37#define TIMER_STS_GPT0_CLR_PEND BIT(10)
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080038
39#define GPT_HZ 32768
Jeff Ohlstein672039f2010-10-05 15:23:57 -070040
Stephen Boyd2081a6b2011-11-08 10:34:08 -080041#define MSM_DGT_SHIFT 5
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080042
Stephen Boyd2a00c102011-11-08 10:34:07 -080043static void __iomem *event_base;
Stephen Boyde25e3d12013-03-14 20:31:39 -070044static void __iomem *sts_base;
Stephen Boyda850c3f2011-11-08 10:34:06 -080045
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080046static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
47{
Stephen Boyd4d70c592013-02-15 17:31:31 -080048 struct clock_event_device *evt = dev_id;
Stephen Boyda850c3f2011-11-08 10:34:06 -080049 /* Stop the timer tick */
50 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
Stephen Boyd2a00c102011-11-08 10:34:07 -080051 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080052 ctrl &= ~TIMER_ENABLE_EN;
Stephen Boyd2a00c102011-11-08 10:34:07 -080053 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080054 }
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080055 evt->event_handler(evt);
56 return IRQ_HANDLED;
57}
58
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080059static int msm_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt)
61{
Stephen Boyd2a00c102011-11-08 10:34:07 -080062 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080063
Stephen Boyd4080d2d2013-03-14 20:31:37 -070064 ctrl &= ~TIMER_ENABLE_EN;
65 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
66
67 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
Stephen Boyd2a00c102011-11-08 10:34:07 -080068 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
Stephen Boyde25e3d12013-03-14 20:31:39 -070069
70 if (sts_base)
71 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
72 cpu_relax();
73
Stephen Boyd2a00c102011-11-08 10:34:07 -080074 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080075 return 0;
76}
77
78static void msm_timer_set_mode(enum clock_event_mode mode,
79 struct clock_event_device *evt)
80{
Stephen Boyda850c3f2011-11-08 10:34:06 -080081 u32 ctrl;
82
Stephen Boyd2a00c102011-11-08 10:34:07 -080083 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080084 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
Jeff Ohlstein94790ec2010-12-02 12:05:12 -080085
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080086 switch (mode) {
87 case CLOCK_EVT_MODE_RESUME:
88 case CLOCK_EVT_MODE_PERIODIC:
89 break;
90 case CLOCK_EVT_MODE_ONESHOT:
Stephen Boyda850c3f2011-11-08 10:34:06 -080091 /* Timer is enabled in set_next_event */
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080092 break;
93 case CLOCK_EVT_MODE_UNUSED:
94 case CLOCK_EVT_MODE_SHUTDOWN:
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080095 break;
96 }
Stephen Boyd2a00c102011-11-08 10:34:07 -080097 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080098}
99
Stephen Boyd4d70c592013-02-15 17:31:31 -0800100static struct clock_event_device __percpu *msm_evt;
Stephen Boyd2a00c102011-11-08 10:34:07 -0800101
102static void __iomem *source_base;
103
Stephen Boydf8e56c42012-02-22 01:39:37 +0000104static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
Stephen Boyd2a00c102011-11-08 10:34:07 -0800105{
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800106 return readl_relaxed(source_base + TIMER_COUNT_VAL);
107}
108
Stephen Boydf8e56c42012-02-22 01:39:37 +0000109static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800110{
Stephen Boyd2a00c102011-11-08 10:34:07 -0800111 /*
112 * Shift timer count down by a constant due to unreliable lower bits
113 * on some targets.
114 */
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800115 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
Stephen Boyd2a00c102011-11-08 10:34:07 -0800116}
117
118static struct clocksource msm_clocksource = {
119 .name = "dg_timer",
120 .rating = 300,
121 .read = msm_read_timer_count,
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800122 .mask = CLOCKSOURCE_MASK(32),
Stephen Boyd2a00c102011-11-08 10:34:07 -0800123 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800124};
125
Stephen Boyd4d70c592013-02-15 17:31:31 -0800126static int msm_timer_irq;
127static int msm_timer_has_ppi;
128
Paul Gortmaker8bd26e32013-06-17 15:43:14 -0400129static int msm_local_timer_setup(struct clock_event_device *evt)
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000130{
Stephen Boyd4d70c592013-02-15 17:31:31 -0800131 int cpu = smp_processor_id();
132 int err;
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000133
Stephen Boyd4d70c592013-02-15 17:31:31 -0800134 evt->irq = msm_timer_irq;
135 evt->name = "msm_timer";
136 evt->features = CLOCK_EVT_FEAT_ONESHOT;
137 evt->rating = 200;
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000138 evt->set_mode = msm_timer_set_mode;
139 evt->set_next_event = msm_timer_set_next_event;
Stephen Boyd4d70c592013-02-15 17:31:31 -0800140 evt->cpumask = cpumask_of(cpu);
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000141
Stephen Boyd4d70c592013-02-15 17:31:31 -0800142 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
143
144 if (msm_timer_has_ppi) {
145 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
146 } else {
147 err = request_irq(evt->irq, msm_timer_interrupt,
148 IRQF_TIMER | IRQF_NOBALANCING |
149 IRQF_TRIGGER_RISING, "gp_timer", evt);
150 if (err)
151 pr_err("request_irq failed\n");
152 }
153
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000154 return 0;
155}
156
157static void msm_local_timer_stop(struct clock_event_device *evt)
158{
159 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
160 disable_percpu_irq(evt->irq);
161}
162
Olof Johansson47dcd352013-07-23 14:51:34 -0700163static int msm_timer_cpu_notify(struct notifier_block *self,
Stephen Boyd4d70c592013-02-15 17:31:31 -0800164 unsigned long action, void *hcpu)
165{
166 /*
167 * Grab cpu pointer in each case to avoid spurious
168 * preemptible warnings
169 */
170 switch (action & ~CPU_TASKS_FROZEN) {
171 case CPU_STARTING:
172 msm_local_timer_setup(this_cpu_ptr(msm_evt));
173 break;
174 case CPU_DYING:
175 msm_local_timer_stop(this_cpu_ptr(msm_evt));
176 break;
177 }
178
179 return NOTIFY_OK;
180}
181
Olof Johansson47dcd352013-07-23 14:51:34 -0700182static struct notifier_block msm_timer_cpu_nb = {
Stephen Boyd4d70c592013-02-15 17:31:31 -0800183 .notifier_call = msm_timer_cpu_notify,
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000184};
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000185
Stephen Boyd6aa16a22013-11-15 15:26:16 -0800186static u64 notrace msm_sched_clock_read(void)
Stephen Boydf8e56c42012-02-22 01:39:37 +0000187{
188 return msm_clocksource.read(&msm_clocksource);
189}
190
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700191static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
192 bool percpu)
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800193{
Stephen Boyd2a00c102011-11-08 10:34:07 -0800194 struct clocksource *cs = &msm_clocksource;
Stephen Boyd4d70c592013-02-15 17:31:31 -0800195 int res = 0;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800196
Stephen Boyd4d70c592013-02-15 17:31:31 -0800197 msm_timer_irq = irq;
198 msm_timer_has_ppi = percpu;
David Brown8c27e6f2011-01-07 10:20:49 -0800199
Stephen Boyd4d70c592013-02-15 17:31:31 -0800200 msm_evt = alloc_percpu(struct clock_event_device);
201 if (!msm_evt) {
202 pr_err("memory allocation failed for clockevents\n");
203 goto err;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800204 }
Stephen Boyddd15ab82011-11-08 10:34:05 -0800205
Stephen Boyd4d70c592013-02-15 17:31:31 -0800206 if (percpu)
207 res = request_percpu_irq(irq, msm_timer_interrupt,
208 "gp_timer", msm_evt);
209
210 if (res) {
211 pr_err("request_percpu_irq failed\n");
212 } else {
213 res = register_cpu_notifier(&msm_timer_cpu_nb);
214 if (res) {
215 free_percpu_irq(irq, msm_evt);
216 goto err;
217 }
218
219 /* Immediately configure the timer on the boot CPU */
220 msm_local_timer_setup(__this_cpu_ptr(msm_evt));
221 }
222
Stephen Boyddd15ab82011-11-08 10:34:05 -0800223err:
Stephen Boyd2a00c102011-11-08 10:34:07 -0800224 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800225 res = clocksource_register_hz(cs, dgt_hz);
Stephen Boyddd15ab82011-11-08 10:34:05 -0800226 if (res)
Stephen Boyd2a00c102011-11-08 10:34:07 -0800227 pr_err("clocksource_register failed\n");
Stephen Boyd6aa16a22013-11-15 15:26:16 -0800228 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800229}
230
Stephen Boyd6e332162012-09-05 12:28:53 -0700231#ifdef CONFIG_OF
Stephen Boydc6025202013-07-24 13:54:30 -0700232static void __init msm_dt_timer_init(struct device_node *np)
Stephen Boyd6e332162012-09-05 12:28:53 -0700233{
Stephen Boyd6e332162012-09-05 12:28:53 -0700234 u32 freq;
235 int irq;
236 struct resource res;
237 u32 percpu_offset;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700238 void __iomem *base;
239 void __iomem *cpu0_base;
Stephen Boyd6e332162012-09-05 12:28:53 -0700240
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700241 base = of_iomap(np, 0);
242 if (!base) {
Stephen Boyd6e332162012-09-05 12:28:53 -0700243 pr_err("Failed to map event base\n");
244 return;
245 }
246
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700247 /* We use GPT0 for the clockevent */
248 irq = irq_of_parse_and_map(np, 1);
Stephen Boyd6e332162012-09-05 12:28:53 -0700249 if (irq <= 0) {
250 pr_err("Can't get irq\n");
251 return;
252 }
Stephen Boyd6e332162012-09-05 12:28:53 -0700253
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700254 /* We use CPU0's DGT for the clocksource */
Stephen Boyd6e332162012-09-05 12:28:53 -0700255 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
256 percpu_offset = 0;
257
258 if (of_address_to_resource(np, 0, &res)) {
259 pr_err("Failed to parse DGT resource\n");
260 return;
261 }
262
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700263 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
264 if (!cpu0_base) {
Stephen Boyd6e332162012-09-05 12:28:53 -0700265 pr_err("Failed to map source base\n");
266 return;
267 }
268
Stephen Boyd6e332162012-09-05 12:28:53 -0700269 if (of_property_read_u32(np, "clock-frequency", &freq)) {
270 pr_err("Unknown frequency\n");
271 return;
272 }
Stephen Boyd6e332162012-09-05 12:28:53 -0700273
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700274 event_base = base + 0x4;
Stephen Boyde25e3d12013-03-14 20:31:39 -0700275 sts_base = base + 0x88;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700276 source_base = cpu0_base + 0x24;
277 freq /= 4;
278 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
279
Stephen Boyd6e332162012-09-05 12:28:53 -0700280 msm_timer_init(freq, 32, irq, !!percpu_offset);
281}
Stephen Boydc6025202013-07-24 13:54:30 -0700282CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
283CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
Stephen Boyd6e332162012-09-05 12:28:53 -0700284#endif
285
Stephen Boyde25e3d12013-03-14 20:31:39 -0700286static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
287 u32 sts)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700288{
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700289 void __iomem *base;
290
291 base = ioremap(addr, SZ_256);
292 if (!base) {
293 pr_err("Failed to map timer base\n");
294 return -ENOMEM;
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700295 }
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700296 event_base = base + event;
297 source_base = base + source;
Stephen Boyde25e3d12013-03-14 20:31:39 -0700298 if (sts)
299 sts_base = base + sts;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700300
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700301 return 0;
302}
303
Stephen Warren6bb27d72012-11-08 12:40:59 -0700304void __init msm7x01_timer_init(void)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700305{
306 struct clocksource *cs = &msm_clocksource;
307
Stephen Boyde25e3d12013-03-14 20:31:39 -0700308 if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700309 return;
310 cs->read = msm_read_timer_count_shift;
311 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
312 /* 600 KHz */
313 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
314 false);
315}
316
Stephen Warren6bb27d72012-11-08 12:40:59 -0700317void __init msm7x30_timer_init(void)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700318{
Stephen Boyde25e3d12013-03-14 20:31:39 -0700319 if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700320 return;
321 msm_timer_init(24576000 / 4, 32, 1, false);
322}
323
Stephen Warren6bb27d72012-11-08 12:40:59 -0700324void __init qsd8x50_timer_init(void)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700325{
Stephen Boyde25e3d12013-03-14 20:31:39 -0700326 if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700327 return;
328 msm_timer_init(19200000 / 4, 32, 7, false);
329}