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SAN People73a59c12006-01-09 17:05:41 +00001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * linux/arch/arm/mach-at91/clock.c
SAN People73a59c12006-01-09 17:05:41 +00003 *
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/fs.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/spinlock.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010025#include <linux/io.h>
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +080026#include <linux/of_address.h>
SAN People73a59c12006-01-09 17:05:41 +000027
Russell Kinga09e64f2008-08-05 16:14:15 +010028#include <mach/hardware.h>
29#include <mach/at91_pmc.h>
30#include <mach/cpu.h>
SAN People73a59c12006-01-09 17:05:41 +000031
Jean-Christophe PLAGNIOL-VILLARD0d781712012-02-05 20:25:32 +080032#include <asm/proc-fns.h>
33
Andrew Victor2eeaaa22006-09-27 10:50:59 +010034#include "clock.h"
Andrew Victor5e38efa2009-12-15 21:57:27 +010035#include "generic.h"
SAN People73a59c12006-01-09 17:05:41 +000036
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +080037void __iomem *at91_pmc_base;
Andrew Victor55c20c02006-06-20 19:31:39 +010038
SAN People73a59c12006-01-09 17:05:41 +000039/*
40 * There's a lot more which can be done with clocks, including cpufreq
41 * integration, slow clock mode support (for system suspend), letting
42 * PLLB be used at other rates (on boards that don't need USB), etc.
43 */
44
Andrew Victor2eeaaa22006-09-27 10:50:59 +010045#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
46#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
47#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
Andrew Victord481f862006-12-01 11:27:31 +010048#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
SAN People73a59c12006-01-09 17:05:41 +000049
Andrew Victor2eeaaa22006-09-27 10:50:59 +010050
Nicolas Ferre6d0485a2009-03-31 17:13:15 +010051/*
52 * Chips have some kind of clocks : group them by functionality
53 */
Jean-Christophe PLAGNIOL-VILLARD9918cea2012-01-26 14:07:09 +010054#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
Nicolas Ferre11128722011-03-10 19:08:54 +010055 || cpu_is_at91sam9g45() \
56 || cpu_is_at91sam9x5())
Nicolas Ferre6d0485a2009-03-31 17:13:15 +010057
Nicolas Ferre2ef9df72009-06-26 15:36:57 +010058#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
Nicolas Ferre11128722011-03-10 19:08:54 +010059 || cpu_is_at91sam9g45() \
60 || cpu_is_at91sam9x5())
Nicolas Ferre6d0485a2009-03-31 17:13:15 +010061
Nicolas Ferreeab41702009-06-26 15:37:00 +010062#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
Nicolas Ferre6d0485a2009-03-31 17:13:15 +010063
Nicolas Ferre2ef9df72009-06-26 15:36:57 +010064#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
Nicolas Ferre11128722011-03-10 19:08:54 +010065 || cpu_is_at91sam9g45() \
66 || cpu_is_at91sam9x5()))
Nicolas Ferre2ef9df72009-06-26 15:36:57 +010067
Nicolas Ferre11128722011-03-10 19:08:54 +010068#define cpu_has_upll() (cpu_is_at91sam9g45() \
69 || cpu_is_at91sam9x5())
Nicolas Ferre6d0485a2009-03-31 17:13:15 +010070
71/* USB host HS & FS */
72#define cpu_has_uhp() (!cpu_is_at91sam9rl())
73
74/* USB device FS only */
Nicolas Ferre2ef9df72009-06-26 15:36:57 +010075#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
Nicolas Ferre11128722011-03-10 19:08:54 +010076 || cpu_is_at91sam9g45() \
77 || cpu_is_at91sam9x5()))
78
79#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
80 || cpu_is_at91sam9x5())
81
82#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
83 || cpu_is_at91sam9x5())
84
85#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
Nicolas Ferre6d0485a2009-03-31 17:13:15 +010086
Andrew Victor2eeaaa22006-09-27 10:50:59 +010087static LIST_HEAD(clocks);
88static DEFINE_SPINLOCK(clk_lock);
89
90static u32 at91_pllb_usb_init;
SAN People73a59c12006-01-09 17:05:41 +000091
92/*
93 * Four primary clock sources: two crystal oscillators (32K, main), and
94 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
95 * 48 MHz (unless no USB function clocks are needed). The main clock and
96 * both PLLs are turned off to run in "slow clock mode" (system suspend).
97 */
98static struct clk clk32k = {
99 .name = "clk32k",
100 .rate_hz = AT91_SLOW_CLOCK,
101 .users = 1, /* always on */
102 .id = 0,
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100103 .type = CLK_TYPE_PRIMARY,
SAN People73a59c12006-01-09 17:05:41 +0000104};
105static struct clk main_clk = {
106 .name = "main",
Andrew Victor91f8ed82006-06-19 13:20:23 +0100107 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
SAN People73a59c12006-01-09 17:05:41 +0000108 .id = 1,
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100109 .type = CLK_TYPE_PRIMARY,
SAN People73a59c12006-01-09 17:05:41 +0000110};
111static struct clk plla = {
112 .name = "plla",
113 .parent = &main_clk,
Andrew Victor91f8ed82006-06-19 13:20:23 +0100114 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
SAN People73a59c12006-01-09 17:05:41 +0000115 .id = 2,
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100116 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
SAN People73a59c12006-01-09 17:05:41 +0000117};
118
119static void pllb_mode(struct clk *clk, int is_on)
120{
121 u32 value;
122
123 if (is_on) {
124 is_on = AT91_PMC_LOCKB;
125 value = at91_pllb_usb_init;
126 } else
127 value = 0;
128
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100129 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800130 at91_pmc_write(AT91_CKGR_PLLBR, value);
SAN People73a59c12006-01-09 17:05:41 +0000131
132 do {
133 cpu_relax();
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800134 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
SAN People73a59c12006-01-09 17:05:41 +0000135}
136
137static struct clk pllb = {
138 .name = "pllb",
139 .parent = &main_clk,
Andrew Victor91f8ed82006-06-19 13:20:23 +0100140 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
SAN People73a59c12006-01-09 17:05:41 +0000141 .mode = pllb_mode,
142 .id = 3,
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100143 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
SAN People73a59c12006-01-09 17:05:41 +0000144};
145
146static void pmc_sys_mode(struct clk *clk, int is_on)
147{
148 if (is_on)
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800149 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
SAN People73a59c12006-01-09 17:05:41 +0000150 else
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800151 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
SAN People73a59c12006-01-09 17:05:41 +0000152}
153
Stelian Pop53d71682008-04-05 21:14:03 +0100154static void pmc_uckr_mode(struct clk *clk, int is_on)
155{
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800156 unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
Stelian Pop53d71682008-04-05 21:14:03 +0100157
158 if (is_on) {
159 is_on = AT91_PMC_LOCKU;
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800160 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
Stelian Pop53d71682008-04-05 21:14:03 +0100161 } else
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800162 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
Stelian Pop53d71682008-04-05 21:14:03 +0100163
164 do {
165 cpu_relax();
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800166 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
Stelian Pop53d71682008-04-05 21:14:03 +0100167}
168
SAN People73a59c12006-01-09 17:05:41 +0000169/* USB function clocks (PLLB must be 48 MHz) */
170static struct clk udpck = {
171 .name = "udpck",
172 .parent = &pllb,
SAN People73a59c12006-01-09 17:05:41 +0000173 .mode = pmc_sys_mode,
174};
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100175struct clk utmi_clk = {
Stelian Pop53d71682008-04-05 21:14:03 +0100176 .name = "utmi_clk",
177 .parent = &main_clk,
178 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
179 .mode = pmc_uckr_mode,
180 .type = CLK_TYPE_PLL,
181};
SAN People73a59c12006-01-09 17:05:41 +0000182static struct clk uhpck = {
183 .name = "uhpck",
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100184 /*.parent = ... we choose parent at runtime */
SAN People73a59c12006-01-09 17:05:41 +0000185 .mode = pmc_sys_mode,
186};
187
SAN People73a59c12006-01-09 17:05:41 +0000188
189/*
190 * The master clock is divided from the CPU clock (by 1-4). It's used for
191 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
192 * (e.g baud rate generation). It's sourced from one of the primary clocks.
193 */
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100194struct clk mck = {
SAN People73a59c12006-01-09 17:05:41 +0000195 .name = "mck",
Andrew Victor91f8ed82006-06-19 13:20:23 +0100196 .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
SAN People73a59c12006-01-09 17:05:41 +0000197};
198
199static void pmc_periph_mode(struct clk *clk, int is_on)
200{
201 if (is_on)
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800202 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
SAN People73a59c12006-01-09 17:05:41 +0000203 else
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800204 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
SAN People73a59c12006-01-09 17:05:41 +0000205}
206
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100207static struct clk __init *at91_css_to_clk(unsigned long css)
208{
209 switch (css) {
210 case AT91_PMC_CSS_SLOW:
211 return &clk32k;
212 case AT91_PMC_CSS_MAIN:
213 return &main_clk;
214 case AT91_PMC_CSS_PLLA:
215 return &plla;
216 case AT91_PMC_CSS_PLLB:
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100217 if (cpu_has_upll())
218 /* CSS_PLLB == CSS_UPLL */
219 return &utmi_clk;
220 else if (cpu_has_pllb())
221 return &pllb;
Nicolas Ferre11128722011-03-10 19:08:54 +0100222 break;
223 /* alternate PMC: can use master clock */
224 case AT91_PMC_CSS_MASTER:
225 return &mck;
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100226 }
SAN People73a59c12006-01-09 17:05:41 +0000227
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100228 return NULL;
229}
SAN People73a59c12006-01-09 17:05:41 +0000230
Nicolas Ferre11128722011-03-10 19:08:54 +0100231static int pmc_prescaler_divider(u32 reg)
232{
233 if (cpu_has_alt_prescaler()) {
234 return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
235 } else {
236 return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
237 }
238}
239
SAN People73a59c12006-01-09 17:05:41 +0000240static void __clk_enable(struct clk *clk)
241{
242 if (clk->parent)
243 __clk_enable(clk->parent);
244 if (clk->users++ == 0 && clk->mode)
245 clk->mode(clk, 1);
246}
247
248int clk_enable(struct clk *clk)
249{
250 unsigned long flags;
251
252 spin_lock_irqsave(&clk_lock, flags);
253 __clk_enable(clk);
254 spin_unlock_irqrestore(&clk_lock, flags);
255 return 0;
256}
257EXPORT_SYMBOL(clk_enable);
258
259static void __clk_disable(struct clk *clk)
260{
261 BUG_ON(clk->users == 0);
262 if (--clk->users == 0 && clk->mode)
263 clk->mode(clk, 0);
264 if (clk->parent)
265 __clk_disable(clk->parent);
266}
267
268void clk_disable(struct clk *clk)
269{
270 unsigned long flags;
271
272 spin_lock_irqsave(&clk_lock, flags);
273 __clk_disable(clk);
274 spin_unlock_irqrestore(&clk_lock, flags);
275}
276EXPORT_SYMBOL(clk_disable);
277
278unsigned long clk_get_rate(struct clk *clk)
279{
280 unsigned long flags;
281 unsigned long rate;
282
283 spin_lock_irqsave(&clk_lock, flags);
284 for (;;) {
285 rate = clk->rate_hz;
286 if (rate || !clk->parent)
287 break;
288 clk = clk->parent;
289 }
290 spin_unlock_irqrestore(&clk_lock, flags);
291 return rate;
292}
293EXPORT_SYMBOL(clk_get_rate);
294
295/*------------------------------------------------------------------------*/
296
297#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
298
299/*
300 * For now, only the programmable clocks support reparenting (MCK could
301 * do this too, with care) or rate changing (the PLLs could do this too,
302 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
303 * a better rate match; we don't.
304 */
305
306long clk_round_rate(struct clk *clk, unsigned long rate)
307{
308 unsigned long flags;
309 unsigned prescale;
310 unsigned long actual;
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100311 unsigned long prev = ULONG_MAX;
SAN People73a59c12006-01-09 17:05:41 +0000312
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100313 if (!clk_is_programmable(clk))
SAN People73a59c12006-01-09 17:05:41 +0000314 return -EINVAL;
315 spin_lock_irqsave(&clk_lock, flags);
316
317 actual = clk->parent->rate_hz;
318 for (prescale = 0; prescale < 7; prescale++) {
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100319 if (actual > rate)
320 prev = actual;
321
322 if (actual && actual <= rate) {
323 if ((prev - rate) < (rate - actual)) {
324 actual = prev;
325 prescale--;
326 }
SAN People73a59c12006-01-09 17:05:41 +0000327 break;
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100328 }
SAN People73a59c12006-01-09 17:05:41 +0000329 actual >>= 1;
330 }
331
332 spin_unlock_irqrestore(&clk_lock, flags);
333 return (prescale < 7) ? actual : -ENOENT;
334}
335EXPORT_SYMBOL(clk_round_rate);
336
337int clk_set_rate(struct clk *clk, unsigned long rate)
338{
339 unsigned long flags;
340 unsigned prescale;
Nicolas Ferre11128722011-03-10 19:08:54 +0100341 unsigned long prescale_offset, css_mask;
SAN People73a59c12006-01-09 17:05:41 +0000342 unsigned long actual;
343
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100344 if (!clk_is_programmable(clk))
SAN People73a59c12006-01-09 17:05:41 +0000345 return -EINVAL;
346 if (clk->users)
347 return -EBUSY;
Nicolas Ferre11128722011-03-10 19:08:54 +0100348
349 if (cpu_has_alt_prescaler()) {
350 prescale_offset = PMC_ALT_PRES_OFFSET;
351 css_mask = AT91_PMC_ALT_PCKR_CSS;
352 } else {
353 prescale_offset = PMC_PRES_OFFSET;
354 css_mask = AT91_PMC_CSS;
355 }
356
SAN People73a59c12006-01-09 17:05:41 +0000357 spin_lock_irqsave(&clk_lock, flags);
358
359 actual = clk->parent->rate_hz;
360 for (prescale = 0; prescale < 7; prescale++) {
361 if (actual && actual <= rate) {
362 u32 pckr;
363
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800364 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
Nicolas Ferre11128722011-03-10 19:08:54 +0100365 pckr &= css_mask; /* keep clock selection */
366 pckr |= prescale << prescale_offset;
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800367 at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
SAN People73a59c12006-01-09 17:05:41 +0000368 clk->rate_hz = actual;
369 break;
370 }
371 actual >>= 1;
372 }
373
374 spin_unlock_irqrestore(&clk_lock, flags);
375 return (prescale < 7) ? actual : -ENOENT;
376}
377EXPORT_SYMBOL(clk_set_rate);
378
379struct clk *clk_get_parent(struct clk *clk)
380{
381 return clk->parent;
382}
383EXPORT_SYMBOL(clk_get_parent);
384
385int clk_set_parent(struct clk *clk, struct clk *parent)
386{
387 unsigned long flags;
388
389 if (clk->users)
390 return -EBUSY;
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100391 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
SAN People73a59c12006-01-09 17:05:41 +0000392 return -EINVAL;
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100393
394 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
395 return -EINVAL;
396
SAN People73a59c12006-01-09 17:05:41 +0000397 spin_lock_irqsave(&clk_lock, flags);
398
399 clk->rate_hz = parent->rate_hz;
400 clk->parent = parent;
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800401 at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
SAN People73a59c12006-01-09 17:05:41 +0000402
403 spin_unlock_irqrestore(&clk_lock, flags);
404 return 0;
405}
406EXPORT_SYMBOL(clk_set_parent);
407
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100408/* establish PCK0..PCKN parentage and rate */
David Brownell72e7ae82008-02-06 22:03:42 +0100409static void __init init_programmable_clock(struct clk *clk)
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100410{
411 struct clk *parent;
412 u32 pckr;
Nicolas Ferre11128722011-03-10 19:08:54 +0100413 unsigned int css_mask;
414
415 if (cpu_has_alt_prescaler())
416 css_mask = AT91_PMC_ALT_PCKR_CSS;
417 else
418 css_mask = AT91_PMC_CSS;
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100419
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800420 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
Nicolas Ferre11128722011-03-10 19:08:54 +0100421 parent = at91_css_to_clk(pckr & css_mask);
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100422 clk->parent = parent;
Nicolas Ferre11128722011-03-10 19:08:54 +0100423 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100424}
425
SAN People73a59c12006-01-09 17:05:41 +0000426#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
427
428/*------------------------------------------------------------------------*/
429
430#ifdef CONFIG_DEBUG_FS
431
432static int at91_clk_show(struct seq_file *s, void *unused)
433{
Stelian Pop53d71682008-04-05 21:14:03 +0100434 u32 scsr, pcsr, uckr = 0, sr;
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100435 struct clk *clk;
SAN People73a59c12006-01-09 17:05:41 +0000436
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800437 scsr = at91_pmc_read(AT91_PMC_SCSR);
438 pcsr = at91_pmc_read(AT91_PMC_PCSR);
439 sr = at91_pmc_read(AT91_PMC_SR);
Nicolas Ferre940192e2012-02-23 09:44:37 +0100440 seq_printf(s, "SCSR = %8x\n", scsr);
441 seq_printf(s, "PCSR = %8x\n", pcsr);
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800442 seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
443 seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
444 seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100445 if (cpu_has_pllb())
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800446 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
Nicolas Ferre940192e2012-02-23 09:44:37 +0100447 if (cpu_has_utmi()) {
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800448 uckr = at91_pmc_read(AT91_CKGR_UCKR);
Nicolas Ferre940192e2012-02-23 09:44:37 +0100449 seq_printf(s, "UCKR = %8x\n", uckr);
450 }
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800451 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100452 if (cpu_has_upll())
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800453 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
Nicolas Ferre940192e2012-02-23 09:44:37 +0100454 seq_printf(s, "SR = %8x\n", sr);
SAN People73a59c12006-01-09 17:05:41 +0000455
456 seq_printf(s, "\n");
457
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100458 list_for_each_entry(clk, &clocks, node) {
459 char *state;
SAN People73a59c12006-01-09 17:05:41 +0000460
461 if (clk->mode == pmc_sys_mode)
462 state = (scsr & clk->pmc_mask) ? "on" : "off";
463 else if (clk->mode == pmc_periph_mode)
464 state = (pcsr & clk->pmc_mask) ? "on" : "off";
Stelian Pop53d71682008-04-05 21:14:03 +0100465 else if (clk->mode == pmc_uckr_mode)
466 state = (uckr & clk->pmc_mask) ? "on" : "off";
SAN People73a59c12006-01-09 17:05:41 +0000467 else if (clk->pmc_mask)
468 state = (sr & clk->pmc_mask) ? "on" : "off";
469 else if (clk == &clk32k || clk == &main_clk)
470 state = "on";
471 else
472 state = "";
473
Andrew Victor69b648a2006-03-22 20:14:14 +0000474 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
SAN People73a59c12006-01-09 17:05:41 +0000475 clk->name, clk->users, state, clk_get_rate(clk),
476 clk->parent ? clk->parent->name : "");
477 }
478 return 0;
479}
480
481static int at91_clk_open(struct inode *inode, struct file *file)
482{
483 return single_open(file, at91_clk_show, NULL);
484}
485
Arjan van de Ven5dfe4c92007-02-12 00:55:31 -0800486static const struct file_operations at91_clk_operations = {
SAN People73a59c12006-01-09 17:05:41 +0000487 .open = at91_clk_open,
488 .read = seq_read,
489 .llseek = seq_lseek,
490 .release = single_release,
491};
492
493static int __init at91_clk_debugfs_init(void)
494{
495 /* /sys/kernel/debug/at91_clk */
496 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
497
498 return 0;
499}
500postcore_initcall(at91_clk_debugfs_init);
501
502#endif
503
504/*------------------------------------------------------------------------*/
505
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100506/* Register a new clock */
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100507static void __init at91_clk_add(struct clk *clk)
508{
509 list_add_tail(&clk->node, &clocks);
510
511 clk->cl.con_id = clk->name;
512 clk->cl.clk = clk;
513 clkdev_add(&clk->cl);
514}
515
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100516int __init clk_register(struct clk *clk)
517{
518 if (clk_is_peripheral(clk)) {
Nicolas Ferre5afddee2010-09-09 19:58:23 +0200519 if (!clk->parent)
520 clk->parent = &mck;
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100521 clk->mode = pmc_periph_mode;
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100522 }
Andrew Victord481f862006-12-01 11:27:31 +0100523 else if (clk_is_sys(clk)) {
524 clk->parent = &mck;
525 clk->mode = pmc_sys_mode;
Andrew Victord481f862006-12-01 11:27:31 +0100526 }
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100527#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
528 else if (clk_is_programmable(clk)) {
529 clk->mode = pmc_sys_mode;
530 init_programmable_clock(clk);
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100531 }
532#endif
533
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100534 at91_clk_add(clk);
535
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100536 return 0;
537}
538
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100539/*------------------------------------------------------------------------*/
540
SAN People73a59c12006-01-09 17:05:41 +0000541static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
542{
543 unsigned mul, div;
544
545 div = reg & 0xff;
546 mul = (reg >> 16) & 0x7ff;
547 if (div && mul) {
548 freq /= div;
549 freq *= mul + 1;
550 } else
551 freq = 0;
Andrew Victor69b648a2006-03-22 20:14:14 +0000552
SAN People73a59c12006-01-09 17:05:41 +0000553 return freq;
554}
555
Andrew Victor69b648a2006-03-22 20:14:14 +0000556static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
557{
558 if (pll == &pllb && (reg & AT91_PMC_USB96M))
559 return freq / 2;
560 else
561 return freq;
562}
563
SAN People73a59c12006-01-09 17:05:41 +0000564static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
565{
566 unsigned i, div = 0, mul = 0, diff = 1 << 30;
567 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
568
569 /* PLL output max 240 MHz (or 180 MHz per errata) */
570 if (out_freq > 240000000)
571 goto fail;
572
573 for (i = 1; i < 256; i++) {
574 int diff1;
575 unsigned input, mul1;
576
577 /*
578 * PLL input between 1MHz and 32MHz per spec, but lower
579 * frequences seem necessary in some cases so allow 100K.
sedji gaouaou61352662008-07-10 10:15:35 +0100580 * Warning: some newer products need 2MHz min.
SAN People73a59c12006-01-09 17:05:41 +0000581 */
582 input = main_freq / i;
sedji gaouaou61352662008-07-10 10:15:35 +0100583 if (cpu_is_at91sam9g20() && input < 2000000)
584 continue;
SAN People73a59c12006-01-09 17:05:41 +0000585 if (input < 100000)
586 continue;
587 if (input > 32000000)
588 continue;
589
590 mul1 = out_freq / input;
sedji gaouaou61352662008-07-10 10:15:35 +0100591 if (cpu_is_at91sam9g20() && mul > 63)
592 continue;
SAN People73a59c12006-01-09 17:05:41 +0000593 if (mul1 > 2048)
594 continue;
595 if (mul1 < 2)
596 goto fail;
597
598 diff1 = out_freq - input * mul1;
599 if (diff1 < 0)
600 diff1 = -diff1;
601 if (diff > diff1) {
602 diff = diff1;
603 div = i;
604 mul = mul1;
605 if (diff == 0)
606 break;
607 }
608 }
609 if (i == 256 && diff > (out_freq >> 5))
610 goto fail;
611 return ret | ((mul - 1) << 16) | div;
612fail:
613 return 0;
614}
615
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100616static struct clk *const standard_pmc_clocks[] __initdata = {
617 /* four primary clocks */
618 &clk32k,
619 &main_clk,
620 &plla,
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100621
622 /* MCK */
623 &mck
624};
625
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100626/* PLLB generated USB full speed clock init */
627static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
628{
629 /*
630 * USB clock init: choose 48 MHz PLLB value,
631 * disable 48MHz clock during usb peripheral suspend.
632 *
633 * REVISIT: assumes MCK doesn't derive from PLLB!
634 */
635 uhpck.parent = &pllb;
636
637 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
638 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
639 if (cpu_is_at91rm9200()) {
640 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
641 udpck.pmc_mask = AT91RM9200_PMC_UDP;
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800642 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
Nicolas Ferreeab41702009-06-26 15:37:00 +0100643 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
644 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
Jean-Christophe PLAGNIOL-VILLARD7a2207a2011-05-17 20:51:14 +0800645 cpu_is_at91sam9g10()) {
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100646 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
647 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100648 }
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800649 at91_pmc_write(AT91_CKGR_PLLBR, 0);
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100650
651 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
652 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
653}
654
655/* UPLL generated USB full speed clock init */
656static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
657{
658 /*
659 * USB clock init: choose 480 MHz from UPLL,
660 */
661 unsigned int usbr = AT91_PMC_USBS_UPLL;
662
663 /* Setup divider by 10 to reach 48 MHz */
664 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
665
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800666 at91_pmc_write(AT91_PMC_USB, usbr);
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100667
668 /* Now set uhpck values */
669 uhpck.parent = &utmi_clk;
670 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
Ryan Mallon82515442010-06-02 12:55:36 +1200671 uhpck.rate_hz = utmi_clk.rate_hz;
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800672 uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100673}
674
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +0800675static int __init at91_pmc_init(unsigned long main_clock)
SAN People73a59c12006-01-09 17:05:41 +0000676{
677 unsigned tmp, freq, mckr;
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100678 int i;
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100679 int pll_overclock = false;
SAN People73a59c12006-01-09 17:05:41 +0000680
681 /*
682 * When the bootloader initialized the main oscillator correctly,
683 * there's no problem using the cycle counter. But if it didn't,
684 * or when using oscillator bypass mode, we must be told the speed
685 * of the main clock.
686 */
687 if (!main_clock) {
688 do {
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800689 tmp = at91_pmc_read(AT91_CKGR_MCFR);
Andrew Victor69b648a2006-03-22 20:14:14 +0000690 } while (!(tmp & AT91_PMC_MAINRDY));
691 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
SAN People73a59c12006-01-09 17:05:41 +0000692 }
693 main_clk.rate_hz = main_clock;
694
695 /* report if PLLA is more than mildly overclocked */
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800696 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100697 if (cpu_has_300M_plla()) {
698 if (plla.rate_hz > 300000000)
699 pll_overclock = true;
700 } else if (cpu_has_800M_plla()) {
701 if (plla.rate_hz > 800000000)
702 pll_overclock = true;
703 } else {
704 if (plla.rate_hz > 209000000)
705 pll_overclock = true;
706 }
707 if (pll_overclock)
SAN People73a59c12006-01-09 17:05:41 +0000708 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
709
Nicolas Ferre11128722011-03-10 19:08:54 +0100710 if (cpu_has_plladiv2()) {
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800711 mckr = at91_pmc_read(AT91_PMC_MCKR);
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100712 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
713 }
SAN People73a59c12006-01-09 17:05:41 +0000714
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100715 if (!cpu_has_pllb() && cpu_has_upll()) {
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100716 /* setup UTMI clock as the fourth primary clock
717 * (instead of pllb) */
718 utmi_clk.type |= CLK_TYPE_PRIMARY;
719 utmi_clk.id = 3;
720 }
721
Andrew Victor69b648a2006-03-22 20:14:14 +0000722
SAN People73a59c12006-01-09 17:05:41 +0000723 /*
Stelian Pop53d71682008-04-05 21:14:03 +0100724 * USB HS clock init
725 */
Andrew Victor5e38efa2009-12-15 21:57:27 +0100726 if (cpu_has_utmi()) {
Stelian Pop53d71682008-04-05 21:14:03 +0100727 /*
728 * multiplier is hard-wired to 40
729 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
730 */
731 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
Nicolas Ferre11128722011-03-10 19:08:54 +0100732
733 /* UTMI bias and PLL are managed at the same time */
734 if (cpu_has_upll())
735 utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
Andrew Victor5e38efa2009-12-15 21:57:27 +0100736 }
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100737
738 /*
739 * USB FS clock init
740 */
741 if (cpu_has_pllb())
742 at91_pllb_usbfs_clock_init(main_clock);
743 if (cpu_has_upll())
744 /* assumes that we choose UPLL for USB and not PLLA */
745 at91_upll_usbfs_clock_init(main_clock);
Stelian Pop53d71682008-04-05 21:14:03 +0100746
747 /*
SAN People73a59c12006-01-09 17:05:41 +0000748 * MCK and CPU derive from one of those primary clocks.
749 * For now, assume this parentage won't change.
750 */
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800751 mckr = at91_pmc_read(AT91_PMC_MCKR);
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100752 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
SAN People73a59c12006-01-09 17:05:41 +0000753 freq = mck.parent->rate_hz;
Nicolas Ferre11128722011-03-10 19:08:54 +0100754 freq /= pmc_prescaler_divider(mckr); /* prescale */
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100755 if (cpu_is_at91rm9200()) {
Andrew Victora95c7292007-11-19 11:52:09 +0100756 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100757 } else if (cpu_is_at91sam9g20()) {
sedji gaouaou61352662008-07-10 10:15:35 +0100758 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
759 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
760 if (mckr & AT91_PMC_PDIV)
761 freq /= 2; /* processor clock division */
Nicolas Ferre11128722011-03-10 19:08:54 +0100762 } else if (cpu_has_mdiv3()) {
Nicolas Ferre2ef9df72009-06-26 15:36:57 +0100763 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
764 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100765 } else {
Andrew Victor5e38efa2009-12-15 21:57:27 +0100766 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100767 }
SAN People73a59c12006-01-09 17:05:41 +0000768
Nicolas Ferre11128722011-03-10 19:08:54 +0100769 if (cpu_has_alt_prescaler()) {
770 /* Programmable clocks can use MCK */
771 mck.type |= CLK_TYPE_PRIMARY;
772 mck.id = 4;
773 }
774
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100775 /* Register the PMC's standard clocks */
776 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100777 at91_clk_add(standard_pmc_clocks[i]);
Andrew Victor2eeaaa22006-09-27 10:50:59 +0100778
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100779 if (cpu_has_pllb())
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100780 at91_clk_add(&pllb);
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100781
782 if (cpu_has_uhp())
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100783 at91_clk_add(&uhpck);
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100784
785 if (cpu_has_udpfs())
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100786 at91_clk_add(&udpck);
Nicolas Ferre6d0485a2009-03-31 17:13:15 +0100787
788 if (cpu_has_utmi())
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100789 at91_clk_add(&utmi_clk);
Stelian Pop53d71682008-04-05 21:14:03 +0100790
Andrew Victor91f8ed82006-06-19 13:20:23 +0100791 /* MCK and CPU clock are "always on" */
792 clk_enable(&mck);
793
SAN People73a59c12006-01-09 17:05:41 +0000794 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
795 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
796 (unsigned) main_clock / 1000000,
797 ((unsigned) main_clock % 1000000) / 1000);
798
Andrew Victorc9b75d12007-02-08 17:36:34 +0100799 return 0;
800}
Andrew Victor91f8ed82006-06-19 13:20:23 +0100801
Jean-Christophe PLAGNIOL-VILLARDeb5e76f2012-03-02 20:44:23 +0800802#if defined(CONFIG_OF)
803static struct of_device_id pmc_ids[] = {
804 { .compatible = "atmel,at91rm9200-pmc" },
805 { /*sentinel*/ }
806};
807
808static struct of_device_id osc_ids[] = {
809 { .compatible = "atmel,osc" },
810 { /*sentinel*/ }
811};
812
813int __init at91_dt_clock_init(void)
814{
815 struct device_node *np;
816 u32 main_clock = 0;
817
818 np = of_find_matching_node(NULL, pmc_ids);
819 if (!np)
820 panic("unable to find compatible pmc node in dtb\n");
821
822 at91_pmc_base = of_iomap(np, 0);
823 if (!at91_pmc_base)
824 panic("unable to map pmc cpu registers\n");
825
826 of_node_put(np);
827
828 /* retrieve the freqency of fixed clocks from device tree */
829 np = of_find_matching_node(NULL, osc_ids);
830 if (np) {
831 u32 rate;
832 if (!of_property_read_u32(np, "clock-frequency", &rate))
833 main_clock = rate;
834 }
835
836 of_node_put(np);
837
838 return at91_pmc_init(main_clock);
839}
840#endif
841
842int __init at91_clock_init(unsigned long main_clock)
843{
844 at91_pmc_base = ioremap(AT91_PMC, 256);
845 if (!at91_pmc_base)
846 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
847
848 return at91_pmc_init(main_clock);
849}
850
Andrew Victorc9b75d12007-02-08 17:36:34 +0100851/*
852 * Several unused clocks may be active. Turn them off.
853 */
854static int __init at91_clock_reset(void)
855{
856 unsigned long pcdr = 0;
857 unsigned long scdr = 0;
858 struct clk *clk;
859
860 list_for_each_entry(clk, &clocks, node) {
861 if (clk->users > 0)
862 continue;
863
864 if (clk->mode == pmc_periph_mode)
865 pcdr |= clk->pmc_mask;
866
867 if (clk->mode == pmc_sys_mode)
868 scdr |= clk->pmc_mask;
869
870 pr_debug("Clocks: disable unused %s\n", clk->name);
871 }
872
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800873 at91_pmc_write(AT91_PMC_PCDR, pcdr);
874 at91_pmc_write(AT91_PMC_SCDR, scdr);
SAN People73a59c12006-01-09 17:05:41 +0000875
876 return 0;
877}
Andrew Victorc9b75d12007-02-08 17:36:34 +0100878late_initcall(at91_clock_reset);
Jean-Christophe PLAGNIOL-VILLARD0d781712012-02-05 20:25:32 +0800879
880void at91sam9_idle(void)
881{
Jean-Christophe PLAGNIOL-VILLARDb5514952011-11-25 09:59:46 +0800882 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
Jean-Christophe PLAGNIOL-VILLARD0d781712012-02-05 20:25:32 +0800883 cpu_do_idle();
884}