blob: 5d3d5dd62daafb42991a2e219100ebd51bd15321 [file] [log] [blame]
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -03001/*
2 Driver for M88RS2000 demodulator and tuner
3
4 Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com)
5 Beta Driver
6
7 Include various calculation code from DS3000 driver.
8 Copyright (C) 2009 Konstantin Dimitrov.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23
24*/
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/jiffies.h>
29#include <linux/string.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32
33
34#include "dvb_frontend.h"
35#include "m88rs2000.h"
36
37struct m88rs2000_state {
38 struct i2c_adapter *i2c;
39 const struct m88rs2000_config *config;
40 struct dvb_frontend frontend;
41 u8 no_lock_count;
42 u32 tuner_frequency;
43 u32 symbol_rate;
44 fe_code_rate_t fec_inner;
45 u8 tuner_level;
46 int errmode;
47};
48
49static int m88rs2000_debug;
50
51module_param_named(debug, m88rs2000_debug, int, 0644);
52MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
53
54#define dprintk(level, args...) do { \
55 if (level & m88rs2000_debug) \
56 printk(KERN_DEBUG "m88rs2000-fe: " args); \
57} while (0)
58
59#define deb_info(args...) dprintk(0x01, args)
60#define info(format, arg...) \
61 printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg)
62
63static int m88rs2000_writereg(struct m88rs2000_state *state, u8 tuner,
64 u8 reg, u8 data)
65{
66 int ret;
67 u8 addr = (tuner == 0) ? state->config->tuner_addr :
68 state->config->demod_addr;
69 u8 buf[] = { reg, data };
70 struct i2c_msg msg = {
71 .addr = addr,
72 .flags = 0,
73 .buf = buf,
74 .len = 2
75 };
76
77 ret = i2c_transfer(state->i2c, &msg, 1);
78
79 if (ret != 1)
80 deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, "
81 "ret == %i)\n", __func__, reg, data, ret);
82
83 return (ret != 1) ? -EREMOTEIO : 0;
84}
85
86static int m88rs2000_demod_write(struct m88rs2000_state *state, u8 reg, u8 data)
87{
88 return m88rs2000_writereg(state, 1, reg, data);
89}
90
91static int m88rs2000_tuner_write(struct m88rs2000_state *state, u8 reg, u8 data)
92{
93 m88rs2000_demod_write(state, 0x81, 0x84);
94 udelay(10);
95 return m88rs2000_writereg(state, 0, reg, data);
96
97}
98
99static int m88rs2000_write(struct dvb_frontend *fe, const u8 buf[], int len)
100{
101 struct m88rs2000_state *state = fe->demodulator_priv;
102
103 if (len != 2)
104 return -EINVAL;
105
106 return m88rs2000_writereg(state, 1, buf[0], buf[1]);
107}
108
109static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 tuner, u8 reg)
110{
111 int ret;
112 u8 b0[] = { reg };
113 u8 b1[] = { 0 };
114 u8 addr = (tuner == 0) ? state->config->tuner_addr :
115 state->config->demod_addr;
116 struct i2c_msg msg[] = {
117 {
118 .addr = addr,
119 .flags = 0,
120 .buf = b0,
121 .len = 1
122 }, {
123 .addr = addr,
124 .flags = I2C_M_RD,
125 .buf = b1,
126 .len = 1
127 }
128 };
129
130 ret = i2c_transfer(state->i2c, msg, 2);
131
132 if (ret != 2)
133 deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",
134 __func__, reg, ret);
135
136 return b1[0];
137}
138
139static u8 m88rs2000_demod_read(struct m88rs2000_state *state, u8 reg)
140{
141 return m88rs2000_readreg(state, 1, reg);
142}
143
144static u8 m88rs2000_tuner_read(struct m88rs2000_state *state, u8 reg)
145{
146 m88rs2000_demod_write(state, 0x81, 0x85);
147 udelay(10);
148 return m88rs2000_readreg(state, 0, reg);
149}
150
151static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate)
152{
153 struct m88rs2000_state *state = fe->demodulator_priv;
154 int ret;
155 u32 temp;
156 u8 b[3];
157
158 if ((srate < 1000000) || (srate > 45000000))
159 return -EINVAL;
160
161 temp = srate / 1000;
162 temp *= 11831;
163 temp /= 68;
164 temp -= 3;
165
166 b[0] = (u8) (temp >> 16) & 0xff;
167 b[1] = (u8) (temp >> 8) & 0xff;
168 b[2] = (u8) temp & 0xff;
169 ret = m88rs2000_demod_write(state, 0x93, b[2]);
170 ret |= m88rs2000_demod_write(state, 0x94, b[1]);
171 ret |= m88rs2000_demod_write(state, 0x95, b[0]);
172
173 deb_info("m88rs2000: m88rs2000_set_symbolrate\n");
174 return ret;
175}
176
177static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe,
178 struct dvb_diseqc_master_cmd *m)
179{
180 struct m88rs2000_state *state = fe->demodulator_priv;
181
182 int i;
183 u8 reg;
184 deb_info("%s\n", __func__);
185 m88rs2000_demod_write(state, 0x9a, 0x30);
186 reg = m88rs2000_demod_read(state, 0xb2);
187 reg &= 0x3f;
188 m88rs2000_demod_write(state, 0xb2, reg);
189 for (i = 0; i < m->msg_len; i++)
190 m88rs2000_demod_write(state, 0xb3 + i, m->msg[i]);
191
192 reg = m88rs2000_demod_read(state, 0xb1);
193 reg &= 0x87;
194 reg |= ((m->msg_len - 1) << 3) | 0x07;
195 reg &= 0x7f;
196 m88rs2000_demod_write(state, 0xb1, reg);
197
198 for (i = 0; i < 15; i++) {
199 if ((m88rs2000_demod_read(state, 0xb1) & 0x40) == 0x0)
200 break;
201 msleep(20);
202 }
203
204 reg = m88rs2000_demod_read(state, 0xb1);
205 if ((reg & 0x40) > 0x0) {
206 reg &= 0x7f;
207 reg |= 0x40;
208 m88rs2000_demod_write(state, 0xb1, reg);
209 }
210
211 reg = m88rs2000_demod_read(state, 0xb2);
212 reg &= 0x3f;
213 reg |= 0x80;
214 m88rs2000_demod_write(state, 0xb2, reg);
215 m88rs2000_demod_write(state, 0x9a, 0xb0);
216
217
218 return 0;
219}
220
221static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe,
222 fe_sec_mini_cmd_t burst)
223{
224 struct m88rs2000_state *state = fe->demodulator_priv;
225 u8 reg0, reg1;
226 deb_info("%s\n", __func__);
227 m88rs2000_demod_write(state, 0x9a, 0x30);
228 msleep(50);
229 reg0 = m88rs2000_demod_read(state, 0xb1);
230 reg1 = m88rs2000_demod_read(state, 0xb2);
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300231 /* TODO complete this section */
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300232 m88rs2000_demod_write(state, 0xb2, reg1);
233 m88rs2000_demod_write(state, 0xb1, reg0);
234 m88rs2000_demod_write(state, 0x9a, 0xb0);
235
236 return 0;
237}
238
239static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
240{
241 struct m88rs2000_state *state = fe->demodulator_priv;
242 u8 reg0, reg1;
243 m88rs2000_demod_write(state, 0x9a, 0x30);
244 reg0 = m88rs2000_demod_read(state, 0xb1);
245 reg1 = m88rs2000_demod_read(state, 0xb2);
246
247 reg1 &= 0x3f;
248
249 switch (tone) {
250 case SEC_TONE_ON:
251 reg0 |= 0x4;
252 reg0 &= 0xbc;
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300253 break;
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300254 case SEC_TONE_OFF:
255 reg1 |= 0x80;
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300256 break;
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300257 default:
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300258 break;
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300259 }
260 m88rs2000_demod_write(state, 0xb2, reg1);
261 m88rs2000_demod_write(state, 0xb1, reg0);
262 m88rs2000_demod_write(state, 0x9a, 0xb0);
263 return 0;
264}
265
266struct inittab {
267 u8 cmd;
268 u8 reg;
269 u8 val;
270};
271
272struct inittab m88rs2000_setup[] = {
273 {DEMOD_WRITE, 0x9a, 0x30},
274 {DEMOD_WRITE, 0x00, 0x01},
275 {WRITE_DELAY, 0x19, 0x00},
276 {DEMOD_WRITE, 0x00, 0x00},
277 {DEMOD_WRITE, 0x9a, 0xb0},
278 {DEMOD_WRITE, 0x81, 0xc1},
279 {TUNER_WRITE, 0x42, 0x73},
280 {TUNER_WRITE, 0x05, 0x07},
281 {TUNER_WRITE, 0x20, 0x27},
282 {TUNER_WRITE, 0x07, 0x02},
283 {TUNER_WRITE, 0x11, 0xff},
284 {TUNER_WRITE, 0x60, 0xf9},
285 {TUNER_WRITE, 0x08, 0x01},
286 {TUNER_WRITE, 0x00, 0x41},
287 {DEMOD_WRITE, 0x81, 0x81},
288 {DEMOD_WRITE, 0x86, 0xc6},
289 {DEMOD_WRITE, 0x9a, 0x30},
290 {DEMOD_WRITE, 0xf0, 0x22},
291 {DEMOD_WRITE, 0xf1, 0xbf},
292 {DEMOD_WRITE, 0xb0, 0x45},
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300293 {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300294 {DEMOD_WRITE, 0x9a, 0xb0},
295 {0xff, 0xaa, 0xff}
296};
297
298struct inittab m88rs2000_shutdown[] = {
299 {DEMOD_WRITE, 0x9a, 0x30},
300 {DEMOD_WRITE, 0xb0, 0x00},
301 {DEMOD_WRITE, 0xf1, 0x89},
302 {DEMOD_WRITE, 0x00, 0x01},
303 {DEMOD_WRITE, 0x9a, 0xb0},
304 {TUNER_WRITE, 0x00, 0x40},
305 {DEMOD_WRITE, 0x81, 0x81},
306 {0xff, 0xaa, 0xff}
307};
308
309struct inittab tuner_reset[] = {
310 {TUNER_WRITE, 0x42, 0x73},
311 {TUNER_WRITE, 0x05, 0x07},
312 {TUNER_WRITE, 0x20, 0x27},
313 {TUNER_WRITE, 0x07, 0x02},
314 {TUNER_WRITE, 0x11, 0xff},
315 {TUNER_WRITE, 0x60, 0xf9},
316 {TUNER_WRITE, 0x08, 0x01},
317 {TUNER_WRITE, 0x00, 0x41},
318 {0xff, 0xaa, 0xff}
319};
320
321struct inittab fe_reset[] = {
322 {DEMOD_WRITE, 0x00, 0x01},
323 {DEMOD_WRITE, 0xf1, 0xbf},
324 {DEMOD_WRITE, 0x00, 0x01},
325 {DEMOD_WRITE, 0x20, 0x81},
326 {DEMOD_WRITE, 0x21, 0x80},
327 {DEMOD_WRITE, 0x10, 0x33},
328 {DEMOD_WRITE, 0x11, 0x44},
329 {DEMOD_WRITE, 0x12, 0x07},
330 {DEMOD_WRITE, 0x18, 0x20},
331 {DEMOD_WRITE, 0x28, 0x04},
332 {DEMOD_WRITE, 0x29, 0x8e},
333 {DEMOD_WRITE, 0x3b, 0xff},
334 {DEMOD_WRITE, 0x32, 0x10},
335 {DEMOD_WRITE, 0x33, 0x02},
336 {DEMOD_WRITE, 0x34, 0x30},
337 {DEMOD_WRITE, 0x35, 0xff},
338 {DEMOD_WRITE, 0x38, 0x50},
339 {DEMOD_WRITE, 0x39, 0x68},
340 {DEMOD_WRITE, 0x3c, 0x7f},
341 {DEMOD_WRITE, 0x3d, 0x0f},
342 {DEMOD_WRITE, 0x45, 0x20},
343 {DEMOD_WRITE, 0x46, 0x24},
344 {DEMOD_WRITE, 0x47, 0x7c},
345 {DEMOD_WRITE, 0x48, 0x16},
346 {DEMOD_WRITE, 0x49, 0x04},
347 {DEMOD_WRITE, 0x4a, 0x01},
348 {DEMOD_WRITE, 0x4b, 0x78},
349 {DEMOD_WRITE, 0X4d, 0xd2},
350 {DEMOD_WRITE, 0x4e, 0x6d},
351 {DEMOD_WRITE, 0x50, 0x30},
352 {DEMOD_WRITE, 0x51, 0x30},
353 {DEMOD_WRITE, 0x54, 0x7b},
354 {DEMOD_WRITE, 0x56, 0x09},
355 {DEMOD_WRITE, 0x58, 0x59},
356 {DEMOD_WRITE, 0x59, 0x37},
357 {DEMOD_WRITE, 0x63, 0xfa},
358 {0xff, 0xaa, 0xff}
359};
360
361struct inittab fe_trigger[] = {
362 {DEMOD_WRITE, 0x97, 0x04},
363 {DEMOD_WRITE, 0x99, 0x77},
364 {DEMOD_WRITE, 0x9b, 0x64},
365 {DEMOD_WRITE, 0x9e, 0x00},
366 {DEMOD_WRITE, 0x9f, 0xf8},
367 {DEMOD_WRITE, 0xa0, 0x20},
368 {DEMOD_WRITE, 0xa1, 0xe0},
369 {DEMOD_WRITE, 0xa3, 0x38},
370 {DEMOD_WRITE, 0x98, 0xff},
371 {DEMOD_WRITE, 0xc0, 0x0f},
372 {DEMOD_WRITE, 0x89, 0x01},
373 {DEMOD_WRITE, 0x00, 0x00},
374 {WRITE_DELAY, 0x0a, 0x00},
375 {DEMOD_WRITE, 0x00, 0x01},
376 {DEMOD_WRITE, 0x00, 0x00},
377 {DEMOD_WRITE, 0x9a, 0xb0},
378 {0xff, 0xaa, 0xff}
379};
380
381static int m88rs2000_tab_set(struct m88rs2000_state *state,
382 struct inittab *tab)
383{
384 int ret = 0;
385 u8 i;
386 if (tab == NULL)
387 return -EINVAL;
388
389 for (i = 0; i < 255; i++) {
390 switch (tab[i].cmd) {
391 case 0x01:
392 ret = m88rs2000_demod_write(state, tab[i].reg,
393 tab[i].val);
394 break;
395 case 0x02:
396 ret = m88rs2000_tuner_write(state, tab[i].reg,
397 tab[i].val);
398 break;
399 case 0x10:
400 if (tab[i].reg > 0)
401 mdelay(tab[i].reg);
402 break;
403 case 0xff:
404 if (tab[i].reg == 0xaa && tab[i].val == 0xff)
405 return 0;
406 case 0x00:
407 break;
408 default:
409 return -EINVAL;
410 }
411 if (ret < 0)
412 return -ENODEV;
413 }
414 return 0;
415}
416
417static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt)
418{
Igor M. Liplianin38431a92012-05-08 04:25:24 -0300419 struct m88rs2000_state *state = fe->demodulator_priv;
420 u8 data;
421
422 data = m88rs2000_demod_read(state, 0xb2);
423 data |= 0x03; /* bit0 V/H, bit1 off/on */
424
425 switch (volt) {
426 case SEC_VOLTAGE_18:
427 data &= ~0x03;
428 break;
429 case SEC_VOLTAGE_13:
430 data &= ~0x03;
431 data |= 0x01;
432 break;
433 case SEC_VOLTAGE_OFF:
434 break;
435 }
436
437 m88rs2000_demod_write(state, 0xb2, data);
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300438
439 return 0;
440}
441
442static int m88rs2000_startup(struct m88rs2000_state *state)
443{
444 int ret = 0;
445 u8 reg;
446
447 reg = m88rs2000_tuner_read(state, 0x00);
448 if ((reg & 0x40) == 0)
449 ret = -ENODEV;
450
451 return ret;
452}
453
454static int m88rs2000_init(struct dvb_frontend *fe)
455{
456 struct m88rs2000_state *state = fe->demodulator_priv;
457 int ret;
458
459 deb_info("m88rs2000: init chip\n");
460 /* Setup frontend from shutdown/cold */
Igor M. Liplianin081416e2012-05-08 04:08:04 -0300461 if (state->config->inittab)
462 ret = m88rs2000_tab_set(state,
463 (struct inittab *)state->config->inittab);
464 else
465 ret = m88rs2000_tab_set(state, m88rs2000_setup);
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300466
467 return ret;
468}
469
470static int m88rs2000_sleep(struct dvb_frontend *fe)
471{
472 struct m88rs2000_state *state = fe->demodulator_priv;
473 int ret;
474 /* Shutdown the frondend */
475 ret = m88rs2000_tab_set(state, m88rs2000_shutdown);
476 return ret;
477}
478
479static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status)
480{
481 struct m88rs2000_state *state = fe->demodulator_priv;
482 u8 reg = m88rs2000_demod_read(state, 0x8c);
483
484 *status = 0;
485
486 if ((reg & 0x7) == 0x7) {
487 *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI
Antti Palosaariff542982012-08-06 18:35:26 -0300488 | FE_HAS_SYNC | FE_HAS_LOCK;
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300489 if (state->config->set_ts_params)
490 state->config->set_ts_params(fe, CALL_IS_READ);
491 }
492 return 0;
493}
494
495/* Extact code for these unknown but lmedm04 driver uses interupt callbacks */
496
497static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber)
498{
499 deb_info("m88rs2000_read_ber %d\n", *ber);
500 *ber = 0;
501 return 0;
502}
503
504static int m88rs2000_read_signal_strength(struct dvb_frontend *fe,
505 u16 *strength)
506{
507 *strength = 0;
508 return 0;
509}
510
511static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr)
512{
513 deb_info("m88rs2000_read_snr %d\n", *snr);
514 *snr = 0;
515 return 0;
516}
517
518static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
519{
520 deb_info("m88rs2000_read_ber %d\n", *ucblocks);
521 *ucblocks = 0;
522 return 0;
523}
524
525static int m88rs2000_tuner_gate_ctrl(struct m88rs2000_state *state, u8 offset)
526{
527 int ret;
528 ret = m88rs2000_tuner_write(state, 0x51, 0x1f - offset);
529 ret |= m88rs2000_tuner_write(state, 0x51, 0x1f);
530 ret |= m88rs2000_tuner_write(state, 0x50, offset);
531 ret |= m88rs2000_tuner_write(state, 0x50, 0x00);
532 msleep(20);
533 return ret;
534}
535
536static int m88rs2000_set_tuner_rf(struct dvb_frontend *fe)
537{
538 struct m88rs2000_state *state = fe->demodulator_priv;
539 int reg;
540 reg = m88rs2000_tuner_read(state, 0x3d);
541 reg &= 0x7f;
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300542 if (reg < 0x16)
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300543 reg = 0xa1;
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300544 else if (reg == 0x16)
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300545 reg = 0x99;
546 else
547 reg = 0xf9;
548
549 m88rs2000_tuner_write(state, 0x60, reg);
550 reg = m88rs2000_tuner_gate_ctrl(state, 0x08);
551
552 if (fe->ops.i2c_gate_ctrl)
553 fe->ops.i2c_gate_ctrl(fe, 0);
554 return reg;
555}
556
557static int m88rs2000_set_tuner(struct dvb_frontend *fe, u16 *offset)
558{
559 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
560 struct m88rs2000_state *state = fe->demodulator_priv;
561 int ret;
562 u32 frequency = c->frequency;
563 s32 offset_khz;
564 s32 tmp;
565 u32 symbol_rate = (c->symbol_rate / 1000);
566 u32 f3db, gdiv28;
567 u16 value, ndiv, lpf_coeff;
568 u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf;
569 u8 lo = 0x01, div4 = 0x0;
570
571 /* Reset Tuner */
572 ret = m88rs2000_tab_set(state, tuner_reset);
573
574 /* Calculate frequency divider */
575 if (frequency < 1060000) {
576 lo |= 0x10;
577 div4 = 0x1;
578 ndiv = (frequency * 14 * 4) / FE_CRYSTAL_KHZ;
579 } else
580 ndiv = (frequency * 14 * 2) / FE_CRYSTAL_KHZ;
581 ndiv = ndiv + ndiv % 2;
582 ndiv = ndiv - 1024;
583
584 ret = m88rs2000_tuner_write(state, 0x10, 0x80 | lo);
585
586 /* Set frequency divider */
587 ret |= m88rs2000_tuner_write(state, 0x01, (ndiv >> 8) & 0xf);
588 ret |= m88rs2000_tuner_write(state, 0x02, ndiv & 0xff);
589
590 ret |= m88rs2000_tuner_write(state, 0x03, 0x06);
591 ret |= m88rs2000_tuner_gate_ctrl(state, 0x10);
592 if (ret < 0)
593 return -ENODEV;
594
595 /* Tuner Frequency Range */
596 ret = m88rs2000_tuner_write(state, 0x10, lo);
597
598 ret |= m88rs2000_tuner_gate_ctrl(state, 0x08);
599
600 /* Tuner RF */
601 ret |= m88rs2000_set_tuner_rf(fe);
602
603 gdiv28 = (FE_CRYSTAL_KHZ / 1000 * 1694 + 500) / 1000;
604 ret |= m88rs2000_tuner_write(state, 0x04, gdiv28 & 0xff);
605 ret |= m88rs2000_tuner_gate_ctrl(state, 0x04);
606 if (ret < 0)
607 return -ENODEV;
608
609 value = m88rs2000_tuner_read(state, 0x26);
610
611 f3db = (symbol_rate * 135) / 200 + 2000;
612 f3db += FREQ_OFFSET_LOW_SYM_RATE;
613 if (f3db < 7000)
614 f3db = 7000;
615 if (f3db > 40000)
616 f3db = 40000;
617
618 gdiv28 = gdiv28 * 207 / (value * 2 + 151);
619 mlpf_max = gdiv28 * 135 / 100;
620 mlpf_min = gdiv28 * 78 / 100;
621 if (mlpf_max > 63)
622 mlpf_max = 63;
623
624 lpf_coeff = 2766;
625
626 nlpf = (f3db * gdiv28 * 2 / lpf_coeff /
627 (FE_CRYSTAL_KHZ / 1000) + 1) / 2;
628 if (nlpf > 23)
629 nlpf = 23;
630 if (nlpf < 1)
631 nlpf = 1;
632
633 lpf_mxdiv = (nlpf * (FE_CRYSTAL_KHZ / 1000)
634 * lpf_coeff * 2 / f3db + 1) / 2;
635
636 if (lpf_mxdiv < mlpf_min) {
637 nlpf++;
638 lpf_mxdiv = (nlpf * (FE_CRYSTAL_KHZ / 1000)
639 * lpf_coeff * 2 / f3db + 1) / 2;
640 }
641
642 if (lpf_mxdiv > mlpf_max)
643 lpf_mxdiv = mlpf_max;
644
645 ret = m88rs2000_tuner_write(state, 0x04, lpf_mxdiv);
646 ret |= m88rs2000_tuner_write(state, 0x06, nlpf);
647
648 ret |= m88rs2000_tuner_gate_ctrl(state, 0x04);
649
650 ret |= m88rs2000_tuner_gate_ctrl(state, 0x01);
651
652 msleep(80);
653 /* calculate offset assuming 96000kHz*/
654 offset_khz = (ndiv - ndiv % 2 + 1024) * FE_CRYSTAL_KHZ
655 / 14 / (div4 + 1) / 2;
656
657 offset_khz -= frequency;
658
659 tmp = offset_khz;
660 tmp *= 65536;
661
662 tmp = (2 * tmp + 96000) / (2 * 96000);
663 if (tmp < 0)
664 tmp += 65536;
665
666 *offset = tmp & 0xffff;
667
668 if (fe->ops.i2c_gate_ctrl)
669 fe->ops.i2c_gate_ctrl(fe, 0);
670
671 return (ret < 0) ? -EINVAL : 0;
672}
673
674static int m88rs2000_set_fec(struct m88rs2000_state *state,
675 fe_code_rate_t fec)
676{
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300677 u16 fec_set;
678 switch (fec) {
679 /* This is not confirmed kept for reference */
680/* case FEC_1_2:
681 fec_set = 0x88;
682 break;
683 case FEC_2_3:
684 fec_set = 0x68;
685 break;
686 case FEC_3_4:
687 fec_set = 0x48;
688 break;
689 case FEC_5_6:
690 fec_set = 0x28;
691 break;
692 case FEC_7_8:
693 fec_set = 0x18;
694 break; */
695 case FEC_AUTO:
696 default:
697 fec_set = 0x08;
698 }
Hans Verkuilfdf07b02012-04-20 08:04:48 -0300699 m88rs2000_demod_write(state, 0x76, fec_set);
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300700
701 return 0;
702}
703
704
705static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state)
706{
707 u8 reg;
708 m88rs2000_demod_write(state, 0x9a, 0x30);
709 reg = m88rs2000_demod_read(state, 0x76);
710 m88rs2000_demod_write(state, 0x9a, 0xb0);
711
712 switch (reg) {
713 case 0x88:
714 return FEC_1_2;
715 case 0x68:
716 return FEC_2_3;
717 case 0x48:
718 return FEC_3_4;
719 case 0x28:
720 return FEC_5_6;
721 case 0x18:
722 return FEC_7_8;
723 case 0x08:
724 default:
725 break;
726 }
727
728 return FEC_AUTO;
729}
730
731static int m88rs2000_set_frontend(struct dvb_frontend *fe)
732{
733 struct m88rs2000_state *state = fe->demodulator_priv;
734 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
735 fe_status_t status;
736 int i, ret;
737 u16 offset = 0;
738 u8 reg;
739
740 state->no_lock_count = 0;
741
742 if (c->delivery_system != SYS_DVBS) {
743 deb_info("%s: unsupported delivery "
744 "system selected (%d)\n",
745 __func__, c->delivery_system);
746 return -EOPNOTSUPP;
747 }
748
749 /* Set Tuner */
750 ret = m88rs2000_set_tuner(fe, &offset);
751 if (ret < 0)
752 return -ENODEV;
753
754 ret = m88rs2000_demod_write(state, 0x9a, 0x30);
755 /* Unknown usually 0xc6 sometimes 0xc1 */
756 reg = m88rs2000_demod_read(state, 0x86);
757 ret |= m88rs2000_demod_write(state, 0x86, reg);
758 /* Offset lower nibble always 0 */
759 ret |= m88rs2000_demod_write(state, 0x9c, (offset >> 8));
760 ret |= m88rs2000_demod_write(state, 0x9d, offset & 0xf0);
761
762
763 /* Reset Demod */
764 ret = m88rs2000_tab_set(state, fe_reset);
765 if (ret < 0)
766 return -ENODEV;
767
768 /* Unknown */
769 reg = m88rs2000_demod_read(state, 0x70);
770 ret = m88rs2000_demod_write(state, 0x70, reg);
771
772 /* Set FEC */
773 ret |= m88rs2000_set_fec(state, c->fec_inner);
774 ret |= m88rs2000_demod_write(state, 0x85, 0x1);
775 ret |= m88rs2000_demod_write(state, 0x8a, 0xbf);
776 ret |= m88rs2000_demod_write(state, 0x8d, 0x1e);
777 ret |= m88rs2000_demod_write(state, 0x90, 0xf1);
778 ret |= m88rs2000_demod_write(state, 0x91, 0x08);
779
780 if (ret < 0)
781 return -ENODEV;
782
783 /* Set Symbol Rate */
784 ret = m88rs2000_set_symbolrate(fe, c->symbol_rate);
785 if (ret < 0)
786 return -ENODEV;
787
788 /* Set up Demod */
789 ret = m88rs2000_tab_set(state, fe_trigger);
790 if (ret < 0)
791 return -ENODEV;
792
793 for (i = 0; i < 25; i++) {
Malcolm Priestleye58c11f2012-05-14 16:43:50 -0300794 reg = m88rs2000_demod_read(state, 0x8c);
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300795 if ((reg & 0x7) == 0x7) {
796 status = FE_HAS_LOCK;
797 break;
798 }
799 state->no_lock_count++;
Malcolm Priestleye58c11f2012-05-14 16:43:50 -0300800 if (state->no_lock_count == 15) {
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300801 reg = m88rs2000_demod_read(state, 0x70);
802 reg ^= 0x4;
803 m88rs2000_demod_write(state, 0x70, reg);
804 state->no_lock_count = 0;
805 }
806 if (state->no_lock_count == 20)
807 m88rs2000_set_tuner_rf(fe);
808 msleep(20);
809 }
810
811 if (status & FE_HAS_LOCK) {
812 state->fec_inner = m88rs2000_get_fec(state);
813 /* Uknown suspect SNR level */
814 reg = m88rs2000_demod_read(state, 0x65);
815 }
816
817 state->tuner_frequency = c->frequency;
818 state->symbol_rate = c->symbol_rate;
819 return 0;
820}
821
822static int m88rs2000_get_frontend(struct dvb_frontend *fe)
823{
824 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
825 struct m88rs2000_state *state = fe->demodulator_priv;
826 c->fec_inner = state->fec_inner;
827 c->frequency = state->tuner_frequency;
828 c->symbol_rate = state->symbol_rate;
829 return 0;
830}
831
832static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
833{
834 struct m88rs2000_state *state = fe->demodulator_priv;
835
836 if (enable)
837 m88rs2000_demod_write(state, 0x81, 0x84);
838 else
839 m88rs2000_demod_write(state, 0x81, 0x81);
840 udelay(10);
841 return 0;
842}
843
844static void m88rs2000_release(struct dvb_frontend *fe)
845{
846 struct m88rs2000_state *state = fe->demodulator_priv;
847 kfree(state);
848}
849
850static struct dvb_frontend_ops m88rs2000_ops = {
851 .delsys = { SYS_DVBS },
852 .info = {
853 .name = "M88RS2000 DVB-S",
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300854 .frequency_min = 950000,
855 .frequency_max = 2150000,
856 .frequency_stepsize = 1000, /* kHz for QPSK frontends */
857 .frequency_tolerance = 5000,
858 .symbol_rate_min = 1000000,
859 .symbol_rate_max = 45000000,
860 .symbol_rate_tolerance = 500, /* ppm */
861 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
862 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
863 FE_CAN_QPSK |
864 FE_CAN_FEC_AUTO
865 },
866
867 .release = m88rs2000_release,
868 .init = m88rs2000_init,
869 .sleep = m88rs2000_sleep,
870 .write = m88rs2000_write,
871 .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl,
872 .read_status = m88rs2000_read_status,
873 .read_ber = m88rs2000_read_ber,
874 .read_signal_strength = m88rs2000_read_signal_strength,
875 .read_snr = m88rs2000_read_snr,
876 .read_ucblocks = m88rs2000_read_ucblocks,
877 .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg,
878 .diseqc_send_burst = m88rs2000_send_diseqc_burst,
879 .set_tone = m88rs2000_set_tone,
880 .set_voltage = m88rs2000_set_voltage,
881
882 .set_frontend = m88rs2000_set_frontend,
883 .get_frontend = m88rs2000_get_frontend,
884};
885
886struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config,
887 struct i2c_adapter *i2c)
888{
889 struct m88rs2000_state *state = NULL;
890
891 /* allocate memory for the internal state */
892 state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL);
893 if (state == NULL)
894 goto error;
895
896 /* setup the state */
897 state->config = config;
898 state->i2c = i2c;
899 state->tuner_frequency = 0;
900 state->symbol_rate = 0;
901 state->fec_inner = 0;
902
903 if (m88rs2000_startup(state) < 0)
904 goto error;
905
906 /* create dvb_frontend */
907 memcpy(&state->frontend.ops, &m88rs2000_ops,
908 sizeof(struct dvb_frontend_ops));
909 state->frontend.demodulator_priv = state;
910 return &state->frontend;
911
912error:
913 kfree(state);
914
915 return NULL;
916}
917EXPORT_SYMBOL(m88rs2000_attach);
918
919MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver");
920MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
921MODULE_LICENSE("GPL");
Malcolm Priestley593a2ce02012-03-14 16:31:26 -0300922MODULE_VERSION("1.13");
Malcolm Priestleyae8dc8ee2012-03-07 18:11:03 -0300923