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Marc Zyngier1a89dd92013-01-21 19:36:12 -05001/*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
Marc Zyngier01ac5e32013-01-21 19:36:16 -050019#include <linux/cpu.h>
Marc Zyngier1a89dd92013-01-21 19:36:12 -050020#include <linux/kvm.h>
21#include <linux/kvm_host.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
Marc Zyngier01ac5e32013-01-21 19:36:16 -050024#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
Christoffer Dall312c4942014-02-02 13:41:02 -080027#include <linux/uaccess.h>
Marc Zyngier01ac5e32013-01-21 19:36:16 -050028
29#include <linux/irqchip/arm-gic.h>
30
Marc Zyngier1a89dd92013-01-21 19:36:12 -050031#include <asm/kvm_emulate.h>
Marc Zyngier01ac5e32013-01-21 19:36:16 -050032#include <asm/kvm_arm.h>
33#include <asm/kvm_mmu.h>
Marc Zyngier1a89dd92013-01-21 19:36:12 -050034
Marc Zyngierb47ef922013-01-21 19:36:14 -050035/*
36 * How the whole thing works (courtesy of Christoffer Dall):
37 *
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
Christoffer Dallce492b12014-06-14 22:34:04 +020039 * something is pending on the CPU interface.
40 * - Interrupts that are pending on the distributor are stored on the
41 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
42 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
43 * arch. timers).
Marc Zyngierb47ef922013-01-21 19:36:14 -050044 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
45 * recalculated
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
Christoffer Dallfa0603d2014-06-09 12:27:18 +020048 * - PPI: dist->irq_pending & dist->irq_enable
49 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
Christoffer Dallce492b12014-06-14 22:34:04 +020050 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
Marc Zyngierb47ef922013-01-21 19:36:14 -050051 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
Christoffer Dallce492b12014-06-14 22:34:04 +020054 * - If any of the above state changes, we must recalculate the oracle.
Marc Zyngierb47ef922013-01-21 19:36:14 -050055 * - The same is true when injecting an interrupt, except that we only
56 * consider a single interrupt at a time. The irq_spi_cpu array
57 * contains the target CPU for each SPI.
58 *
59 * The handling of level interrupts adds some extra complexity. We
60 * need to track when the interrupt has been EOIed, so we can sample
61 * the 'line' again. This is achieved as such:
62 *
63 * - When a level interrupt is moved onto a vcpu, the corresponding
Christoffer Dall25b3fb82014-06-09 12:55:13 +020064 * bit in irq_queued is set. As long as this bit is set, the line
Marc Zyngierb47ef922013-01-21 19:36:14 -050065 * will be ignored for further interrupts. The interrupt is injected
66 * into the vcpu with the GICH_LR_EOI bit set (generate a
67 * maintenance interrupt on EOI).
68 * - When the interrupt is EOIed, the maintenance interrupt fires,
Christoffer Dall25b3fb82014-06-09 12:55:13 +020069 * and clears the corresponding bit in irq_queued. This allows the
Marc Zyngierb47ef922013-01-21 19:36:14 -050070 * interrupt line to be sampled again.
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +020071 * - Note that level-triggered interrupts can also be set to pending from
72 * writes to GICD_ISPENDRn and lowering the external input line does not
73 * cause the interrupt to become inactive in such a situation.
74 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
75 * inactive as long as the external input line is held high.
Marc Zyngierb47ef922013-01-21 19:36:14 -050076 */
77
Christoffer Dall330690c2013-01-21 19:36:13 -050078#define VGIC_ADDR_UNDEF (-1)
79#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
80
Christoffer Dalla0a11ba2013-09-23 14:55:57 -070081#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
82#define IMPLEMENTER_ARM 0x43b
83#define GICC_ARCH_VERSION_V2 0x2
84
Marc Zyngier1a89dd92013-01-21 19:36:12 -050085#define ACCESS_READ_VALUE (1 << 0)
86#define ACCESS_READ_RAZ (0 << 0)
87#define ACCESS_READ_MASK(x) ((x) & (1 << 0))
88#define ACCESS_WRITE_IGNORED (0 << 1)
89#define ACCESS_WRITE_SETBIT (1 << 1)
90#define ACCESS_WRITE_CLEARBIT (2 << 1)
91#define ACCESS_WRITE_VALUE (3 << 1)
92#define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
93
Marc Zyngiera1fcb442013-01-21 19:36:15 -050094static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
Marc Zyngier9f92df72013-06-03 15:55:02 +010095static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
Marc Zyngierb47ef922013-01-21 19:36:14 -050096static void vgic_update_state(struct kvm *kvm);
Marc Zyngier5863c2c2013-01-21 19:36:15 -050097static void vgic_kick_vcpus(struct kvm *kvm);
Marc Zyngier38cb2f72014-07-08 12:09:01 +010098static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi);
Marc Zyngierb47ef922013-01-21 19:36:14 -050099static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
Marc Zyngier9f92df72013-06-03 15:55:02 +0100100static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
101static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
Marc Zyngier32a0e352014-02-04 17:48:10 +0000102static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
103static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
Marc Zyngier01ac5e32013-01-21 19:36:16 -0500104
Marc Zyngierab8bb402014-02-04 18:13:03 +0000105static const struct vgic_ops *vgic_ops;
106static const struct vgic_params *vgic;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500107
Victor Kamenskydf032d72014-06-12 09:30:10 -0700108/*
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100109 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
110 * extracts u32s out of them.
Victor Kamenskydf032d72014-06-12 09:30:10 -0700111 *
112 * This does not work on 64-bit BE systems, because the bitmap access
113 * will store two consecutive 32-bit words with the higher-addressed
114 * register's bits at the lower index and the lower-addressed register's
115 * bits at the higher index.
116 *
117 * Therefore, swizzle the register index when accessing the 32-bit word
118 * registers to access the right register's value.
119 */
120#if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
121#define REG_OFFSET_SWIZZLE 1
122#else
123#define REG_OFFSET_SWIZZLE 0
124#endif
125
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100126static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs)
127{
128 int nr_longs;
129
130 nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS);
131
132 b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL);
133 if (!b->private)
134 return -ENOMEM;
135
136 b->shared = b->private + nr_cpus;
137
138 return 0;
139}
140
141static void vgic_free_bitmap(struct vgic_bitmap *b)
142{
143 kfree(b->private);
144 b->private = NULL;
145 b->shared = NULL;
146}
147
Marc Zyngierb47ef922013-01-21 19:36:14 -0500148static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
149 int cpuid, u32 offset)
150{
151 offset >>= 2;
152 if (!offset)
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100153 return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500154 else
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100155 return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500156}
157
158static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
159 int cpuid, int irq)
160{
161 if (irq < VGIC_NR_PRIVATE_IRQS)
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100162 return test_bit(irq, x->private + cpuid);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500163
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100164 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500165}
166
167static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
168 int irq, int val)
169{
170 unsigned long *reg;
171
172 if (irq < VGIC_NR_PRIVATE_IRQS) {
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100173 reg = x->private + cpuid;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500174 } else {
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100175 reg = x->shared;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500176 irq -= VGIC_NR_PRIVATE_IRQS;
177 }
178
179 if (val)
180 set_bit(irq, reg);
181 else
182 clear_bit(irq, reg);
183}
184
185static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
186{
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100187 return x->private + cpuid;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500188}
189
190static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
191{
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100192 return x->shared;
193}
194
195static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs)
196{
197 int size;
198
199 size = nr_cpus * VGIC_NR_PRIVATE_IRQS;
200 size += nr_irqs - VGIC_NR_PRIVATE_IRQS;
201
202 x->private = kzalloc(size, GFP_KERNEL);
203 if (!x->private)
204 return -ENOMEM;
205
206 x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32);
207 return 0;
208}
209
210static void vgic_free_bytemap(struct vgic_bytemap *b)
211{
212 kfree(b->private);
213 b->private = NULL;
214 b->shared = NULL;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500215}
216
217static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
218{
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100219 u32 *reg;
220
221 if (offset < VGIC_NR_PRIVATE_IRQS) {
222 reg = x->private;
223 offset += cpuid * VGIC_NR_PRIVATE_IRQS;
224 } else {
225 reg = x->shared;
226 offset -= VGIC_NR_PRIVATE_IRQS;
227 }
228
229 return reg + (offset / sizeof(u32));
Marc Zyngierb47ef922013-01-21 19:36:14 -0500230}
231
232#define VGIC_CFG_LEVEL 0
233#define VGIC_CFG_EDGE 1
234
235static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
236{
237 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
238 int irq_val;
239
240 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
241 return irq_val == VGIC_CFG_EDGE;
242}
243
244static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
245{
246 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
247
248 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
249}
250
Christoffer Dall25b3fb82014-06-09 12:55:13 +0200251static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq)
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500252{
253 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
254
Christoffer Dall25b3fb82014-06-09 12:55:13 +0200255 return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500256}
257
Christoffer Dall25b3fb82014-06-09 12:55:13 +0200258static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq)
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500259{
260 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
261
Christoffer Dall25b3fb82014-06-09 12:55:13 +0200262 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1);
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500263}
264
Christoffer Dall25b3fb82014-06-09 12:55:13 +0200265static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq)
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500266{
267 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
268
Christoffer Dall25b3fb82014-06-09 12:55:13 +0200269 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0);
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500270}
271
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200272static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq)
273{
274 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
275
276 return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq);
277}
278
279static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq)
280{
281 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
282
283 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1);
284}
285
286static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq)
287{
288 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
289
290 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0);
291}
292
293static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq)
294{
295 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
296
297 return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq);
298}
299
300static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq)
301{
302 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
303
304 vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0);
305}
306
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500307static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
308{
309 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
310
Christoffer Dallfa0603d2014-06-09 12:27:18 +0200311 return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -0500312}
313
Christoffer Dallfa0603d2014-06-09 12:27:18 +0200314static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq)
Marc Zyngierb47ef922013-01-21 19:36:14 -0500315{
316 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
317
Christoffer Dallfa0603d2014-06-09 12:27:18 +0200318 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500319}
320
Christoffer Dallfa0603d2014-06-09 12:27:18 +0200321static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq)
Marc Zyngierb47ef922013-01-21 19:36:14 -0500322{
323 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
324
Christoffer Dallfa0603d2014-06-09 12:27:18 +0200325 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500326}
327
328static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
329{
330 if (irq < VGIC_NR_PRIVATE_IRQS)
331 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
332 else
333 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
334 vcpu->arch.vgic_cpu.pending_shared);
335}
336
337static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
338{
339 if (irq < VGIC_NR_PRIVATE_IRQS)
340 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
341 else
342 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
343 vcpu->arch.vgic_cpu.pending_shared);
344}
345
Christoffer Dall25b3fb82014-06-09 12:55:13 +0200346static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq)
347{
348 return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq);
349}
350
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500351static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
352{
Victor Kamenskydf5bce92014-06-12 09:30:04 -0700353 return le32_to_cpu(*((u32 *)mmio->data)) & mask;
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500354}
355
356static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
357{
Victor Kamenskydf5bce92014-06-12 09:30:04 -0700358 *((u32 *)mmio->data) = cpu_to_le32(value) & mask;
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500359}
360
361/**
362 * vgic_reg_access - access vgic register
363 * @mmio: pointer to the data describing the mmio access
364 * @reg: pointer to the virtual backing of vgic distributor data
365 * @offset: least significant 2 bits used for word offset
366 * @mode: ACCESS_ mode (see defines above)
367 *
368 * Helper to make vgic register access easier using one of the access
369 * modes defined for vgic register access
370 * (read,raz,write-ignored,setbit,clearbit,write)
371 */
372static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
373 phys_addr_t offset, int mode)
374{
375 int word_offset = (offset & 3) * 8;
376 u32 mask = (1UL << (mmio->len * 8)) - 1;
377 u32 regval;
378
379 /*
380 * Any alignment fault should have been delivered to the guest
381 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
382 */
383
384 if (reg) {
385 regval = *reg;
386 } else {
387 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
388 regval = 0;
389 }
390
391 if (mmio->is_write) {
392 u32 data = mmio_data_read(mmio, mask) << word_offset;
393 switch (ACCESS_WRITE_MASK(mode)) {
394 case ACCESS_WRITE_IGNORED:
395 return;
396
397 case ACCESS_WRITE_SETBIT:
398 regval |= data;
399 break;
400
401 case ACCESS_WRITE_CLEARBIT:
402 regval &= ~data;
403 break;
404
405 case ACCESS_WRITE_VALUE:
406 regval = (regval & ~(mask << word_offset)) | data;
407 break;
408 }
409 *reg = regval;
410 } else {
411 switch (ACCESS_READ_MASK(mode)) {
412 case ACCESS_READ_RAZ:
413 regval = 0;
414 /* fall through */
415
416 case ACCESS_READ_VALUE:
417 mmio_data_write(mmio, mask, regval >> word_offset);
418 }
419 }
420}
421
Marc Zyngierb47ef922013-01-21 19:36:14 -0500422static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
423 struct kvm_exit_mmio *mmio, phys_addr_t offset)
424{
425 u32 reg;
426 u32 word_offset = offset & 3;
427
428 switch (offset & ~3) {
Christoffer Dalla0a11ba2013-09-23 14:55:57 -0700429 case 0: /* GICD_CTLR */
Marc Zyngierb47ef922013-01-21 19:36:14 -0500430 reg = vcpu->kvm->arch.vgic.enabled;
431 vgic_reg_access(mmio, &reg, word_offset,
432 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
433 if (mmio->is_write) {
434 vcpu->kvm->arch.vgic.enabled = reg & 1;
435 vgic_update_state(vcpu->kvm);
436 return true;
437 }
438 break;
439
Christoffer Dalla0a11ba2013-09-23 14:55:57 -0700440 case 4: /* GICD_TYPER */
Marc Zyngierb47ef922013-01-21 19:36:14 -0500441 reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
442 reg |= (VGIC_NR_IRQS >> 5) - 1;
443 vgic_reg_access(mmio, &reg, word_offset,
444 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
445 break;
446
Christoffer Dalla0a11ba2013-09-23 14:55:57 -0700447 case 8: /* GICD_IIDR */
448 reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500449 vgic_reg_access(mmio, &reg, word_offset,
450 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
451 break;
452 }
453
454 return false;
455}
456
457static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
458 struct kvm_exit_mmio *mmio, phys_addr_t offset)
459{
460 vgic_reg_access(mmio, NULL, offset,
461 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
462 return false;
463}
464
465static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
466 struct kvm_exit_mmio *mmio,
467 phys_addr_t offset)
468{
469 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
470 vcpu->vcpu_id, offset);
471 vgic_reg_access(mmio, reg, offset,
472 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
473 if (mmio->is_write) {
474 vgic_update_state(vcpu->kvm);
475 return true;
476 }
477
478 return false;
479}
480
481static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
482 struct kvm_exit_mmio *mmio,
483 phys_addr_t offset)
484{
485 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
486 vcpu->vcpu_id, offset);
487 vgic_reg_access(mmio, reg, offset,
488 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
489 if (mmio->is_write) {
490 if (offset < 4) /* Force SGI enabled */
491 *reg |= 0xffff;
Marc Zyngiera1fcb442013-01-21 19:36:15 -0500492 vgic_retire_disabled_irqs(vcpu);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500493 vgic_update_state(vcpu->kvm);
494 return true;
495 }
496
497 return false;
498}
499
500static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
501 struct kvm_exit_mmio *mmio,
502 phys_addr_t offset)
503{
Christoffer Dalldd684bc2014-06-14 22:30:45 +0200504 u32 *reg, orig;
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200505 u32 level_mask;
506 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
507
508 reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu->vcpu_id, offset);
509 level_mask = (~(*reg));
510
511 /* Mark both level and edge triggered irqs as pending */
512 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
Christoffer Dalldd684bc2014-06-14 22:30:45 +0200513 orig = *reg;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500514 vgic_reg_access(mmio, reg, offset,
515 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200516
Marc Zyngierb47ef922013-01-21 19:36:14 -0500517 if (mmio->is_write) {
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200518 /* Set the soft-pending flag only for level-triggered irqs */
519 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
520 vcpu->vcpu_id, offset);
521 vgic_reg_access(mmio, reg, offset,
522 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
523 *reg &= level_mask;
524
Christoffer Dalldd684bc2014-06-14 22:30:45 +0200525 /* Ignore writes to SGIs */
526 if (offset < 2) {
527 *reg &= ~0xffff;
528 *reg |= orig & 0xffff;
529 }
530
Marc Zyngierb47ef922013-01-21 19:36:14 -0500531 vgic_update_state(vcpu->kvm);
532 return true;
533 }
534
535 return false;
536}
537
538static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
539 struct kvm_exit_mmio *mmio,
540 phys_addr_t offset)
541{
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200542 u32 *level_active;
Christoffer Dalldd684bc2014-06-14 22:30:45 +0200543 u32 *reg, orig;
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200544 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
545
546 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
Christoffer Dalldd684bc2014-06-14 22:30:45 +0200547 orig = *reg;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500548 vgic_reg_access(mmio, reg, offset,
549 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
550 if (mmio->is_write) {
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200551 /* Re-set level triggered level-active interrupts */
552 level_active = vgic_bitmap_get_reg(&dist->irq_level,
553 vcpu->vcpu_id, offset);
554 reg = vgic_bitmap_get_reg(&dist->irq_pending,
555 vcpu->vcpu_id, offset);
556 *reg |= *level_active;
557
Christoffer Dalldd684bc2014-06-14 22:30:45 +0200558 /* Ignore writes to SGIs */
559 if (offset < 2) {
560 *reg &= ~0xffff;
561 *reg |= orig & 0xffff;
562 }
563
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +0200564 /* Clear soft-pending flags */
565 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
566 vcpu->vcpu_id, offset);
567 vgic_reg_access(mmio, reg, offset,
568 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
569
Marc Zyngierb47ef922013-01-21 19:36:14 -0500570 vgic_update_state(vcpu->kvm);
571 return true;
572 }
573
574 return false;
575}
576
577static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
578 struct kvm_exit_mmio *mmio,
579 phys_addr_t offset)
580{
581 u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
582 vcpu->vcpu_id, offset);
583 vgic_reg_access(mmio, reg, offset,
584 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
585 return false;
586}
587
588#define GICD_ITARGETSR_SIZE 32
589#define GICD_CPUTARGETS_BITS 8
590#define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
591static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
592{
593 struct vgic_dist *dist = &kvm->arch.vgic;
Marc Zyngier1752d0c2013-08-29 11:08:22 +0100594 int i;
Marc Zyngierb47ef922013-01-21 19:36:14 -0500595 u32 val = 0;
596
597 irq -= VGIC_NR_PRIVATE_IRQS;
598
Marc Zyngier1752d0c2013-08-29 11:08:22 +0100599 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
600 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
Marc Zyngierb47ef922013-01-21 19:36:14 -0500601
602 return val;
603}
604
605static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
606{
607 struct vgic_dist *dist = &kvm->arch.vgic;
608 struct kvm_vcpu *vcpu;
609 int i, c;
610 unsigned long *bmap;
611 u32 target;
612
613 irq -= VGIC_NR_PRIVATE_IRQS;
614
615 /*
616 * Pick the LSB in each byte. This ensures we target exactly
617 * one vcpu per IRQ. If the byte is null, assume we target
618 * CPU0.
619 */
620 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
621 int shift = i * GICD_CPUTARGETS_BITS;
622 target = ffs((val >> shift) & 0xffU);
623 target = target ? (target - 1) : 0;
624 dist->irq_spi_cpu[irq + i] = target;
625 kvm_for_each_vcpu(c, vcpu, kvm) {
626 bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
627 if (c == target)
628 set_bit(irq + i, bmap);
629 else
630 clear_bit(irq + i, bmap);
631 }
632 }
633}
634
635static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
636 struct kvm_exit_mmio *mmio,
637 phys_addr_t offset)
638{
639 u32 reg;
640
641 /* We treat the banked interrupts targets as read-only */
642 if (offset < 32) {
643 u32 roreg = 1 << vcpu->vcpu_id;
644 roreg |= roreg << 8;
645 roreg |= roreg << 16;
646
647 vgic_reg_access(mmio, &roreg, offset,
648 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
649 return false;
650 }
651
652 reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
653 vgic_reg_access(mmio, &reg, offset,
654 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
655 if (mmio->is_write) {
656 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
657 vgic_update_state(vcpu->kvm);
658 return true;
659 }
660
661 return false;
662}
663
664static u32 vgic_cfg_expand(u16 val)
665{
666 u32 res = 0;
667 int i;
668
669 /*
670 * Turn a 16bit value like abcd...mnop into a 32bit word
671 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
672 */
673 for (i = 0; i < 16; i++)
674 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
675
676 return res;
677}
678
679static u16 vgic_cfg_compress(u32 val)
680{
681 u16 res = 0;
682 int i;
683
684 /*
685 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
686 * abcd...mnop which is what we really care about.
687 */
688 for (i = 0; i < 16; i++)
689 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
690
691 return res;
692}
693
694/*
695 * The distributor uses 2 bits per IRQ for the CFG register, but the
696 * LSB is always 0. As such, we only keep the upper bit, and use the
697 * two above functions to compress/expand the bits
698 */
699static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
700 struct kvm_exit_mmio *mmio, phys_addr_t offset)
701{
702 u32 val;
Marc Zyngier635c8872013-08-29 11:08:23 +0100703 u32 *reg;
704
Marc Zyngier635c8872013-08-29 11:08:23 +0100705 reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
Andre Przywarabc38de22014-04-11 00:07:18 +0200706 vcpu->vcpu_id, offset >> 1);
Marc Zyngier635c8872013-08-29 11:08:23 +0100707
Andre Przywarabc38de22014-04-11 00:07:18 +0200708 if (offset & 4)
Marc Zyngierb47ef922013-01-21 19:36:14 -0500709 val = *reg >> 16;
710 else
711 val = *reg & 0xffff;
712
713 val = vgic_cfg_expand(val);
714 vgic_reg_access(mmio, &val, offset,
715 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
716 if (mmio->is_write) {
Andre Przywarabc38de22014-04-11 00:07:18 +0200717 if (offset < 8) {
Marc Zyngierb47ef922013-01-21 19:36:14 -0500718 *reg = ~0U; /* Force PPIs/SGIs to 1 */
719 return false;
720 }
721
722 val = vgic_cfg_compress(val);
Andre Przywarabc38de22014-04-11 00:07:18 +0200723 if (offset & 4) {
Marc Zyngierb47ef922013-01-21 19:36:14 -0500724 *reg &= 0xffff;
725 *reg |= val << 16;
726 } else {
727 *reg &= 0xffff << 16;
728 *reg |= val;
729 }
730 }
731
732 return false;
733}
734
735static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
736 struct kvm_exit_mmio *mmio, phys_addr_t offset)
737{
738 u32 reg;
739 vgic_reg_access(mmio, &reg, offset,
740 ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
741 if (mmio->is_write) {
742 vgic_dispatch_sgi(vcpu, reg);
743 vgic_update_state(vcpu->kvm);
744 return true;
745 }
746
747 return false;
748}
749
Christoffer Dall944b8a62013-11-15 20:51:31 -0800750/**
751 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
752 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
753 *
754 * Move any pending IRQs that have already been assigned to LRs back to the
755 * emulated distributor state so that the complete emulated state can be read
756 * from the main emulation structures without investigating the LRs.
757 *
758 * Note that IRQs in the active state in the LRs get their pending state moved
759 * to the distributor but the active state stays in the LRs, because we don't
760 * track the active state on the distributor side.
761 */
762static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
763{
764 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
765 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
766 int vcpu_id = vcpu->vcpu_id;
Marc Zyngier9f92df72013-06-03 15:55:02 +0100767 int i;
Christoffer Dall944b8a62013-11-15 20:51:31 -0800768
769 for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
Marc Zyngier9f92df72013-06-03 15:55:02 +0100770 struct vgic_lr lr = vgic_get_lr(vcpu, i);
Christoffer Dall944b8a62013-11-15 20:51:31 -0800771
772 /*
773 * There are three options for the state bits:
774 *
775 * 01: pending
776 * 10: active
777 * 11: pending and active
778 *
779 * If the LR holds only an active interrupt (not pending) then
780 * just leave it alone.
781 */
Marc Zyngier9f92df72013-06-03 15:55:02 +0100782 if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE)
Christoffer Dall944b8a62013-11-15 20:51:31 -0800783 continue;
784
785 /*
786 * Reestablish the pending state on the distributor and the
787 * CPU interface. It may have already been pending, but that
788 * is fine, then we are only setting a few bits that were
789 * already set.
790 */
Christoffer Dallfa0603d2014-06-09 12:27:18 +0200791 vgic_dist_irq_set_pending(vcpu, lr.irq);
Marc Zyngier9f92df72013-06-03 15:55:02 +0100792 if (lr.irq < VGIC_NR_SGIS)
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100793 *vgic_get_sgi_sources(dist, vcpu_id, lr.irq) |= 1 << lr.source;
Marc Zyngier9f92df72013-06-03 15:55:02 +0100794 lr.state &= ~LR_STATE_PENDING;
795 vgic_set_lr(vcpu, i, lr);
Christoffer Dall944b8a62013-11-15 20:51:31 -0800796
797 /*
798 * If there's no state left on the LR (it could still be
799 * active), then the LR does not hold any useful info and can
800 * be marked as free for other use.
801 */
Christoffer Dall520445a2014-06-14 22:37:33 +0200802 if (!(lr.state & LR_STATE_MASK)) {
Marc Zyngier9f92df72013-06-03 15:55:02 +0100803 vgic_retire_lr(i, lr.irq, vcpu);
Christoffer Dall520445a2014-06-14 22:37:33 +0200804 vgic_irq_clear_queued(vcpu, lr.irq);
805 }
Christoffer Dall944b8a62013-11-15 20:51:31 -0800806
807 /* Finally update the VGIC state. */
808 vgic_update_state(vcpu->kvm);
809 }
810}
811
Christoffer Dall8a280d12013-10-25 21:22:31 +0100812/* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
813static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
814 struct kvm_exit_mmio *mmio,
815 phys_addr_t offset)
Christoffer Dall0b3a5402013-10-25 21:17:31 +0100816{
Christoffer Dall8a280d12013-10-25 21:22:31 +0100817 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
818 int sgi;
819 int min_sgi = (offset & ~0x3) * 4;
820 int max_sgi = min_sgi + 3;
821 int vcpu_id = vcpu->vcpu_id;
822 u32 reg = 0;
823
824 /* Copy source SGIs from distributor side */
825 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
826 int shift = 8 * (sgi - min_sgi);
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100827 reg |= ((u32)*vgic_get_sgi_sources(dist, vcpu_id, sgi)) << shift;
Christoffer Dall8a280d12013-10-25 21:22:31 +0100828 }
829
830 mmio_data_write(mmio, ~0, reg);
Christoffer Dall0b3a5402013-10-25 21:17:31 +0100831 return false;
832}
833
Christoffer Dall8a280d12013-10-25 21:22:31 +0100834static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
835 struct kvm_exit_mmio *mmio,
836 phys_addr_t offset, bool set)
837{
838 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
839 int sgi;
840 int min_sgi = (offset & ~0x3) * 4;
841 int max_sgi = min_sgi + 3;
842 int vcpu_id = vcpu->vcpu_id;
843 u32 reg;
844 bool updated = false;
845
846 reg = mmio_data_read(mmio, ~0);
847
848 /* Clear pending SGIs on the distributor */
849 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
850 u8 mask = reg >> (8 * (sgi - min_sgi));
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100851 u8 *src = vgic_get_sgi_sources(dist, vcpu_id, sgi);
Christoffer Dall8a280d12013-10-25 21:22:31 +0100852 if (set) {
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100853 if ((*src & mask) != mask)
Christoffer Dall8a280d12013-10-25 21:22:31 +0100854 updated = true;
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100855 *src |= mask;
Christoffer Dall8a280d12013-10-25 21:22:31 +0100856 } else {
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100857 if (*src & mask)
Christoffer Dall8a280d12013-10-25 21:22:31 +0100858 updated = true;
Marc Zyngier38cb2f72014-07-08 12:09:01 +0100859 *src &= ~mask;
Christoffer Dall8a280d12013-10-25 21:22:31 +0100860 }
861 }
862
863 if (updated)
864 vgic_update_state(vcpu->kvm);
865
866 return updated;
867}
868
Christoffer Dall0b3a5402013-10-25 21:17:31 +0100869static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
870 struct kvm_exit_mmio *mmio,
871 phys_addr_t offset)
872{
Christoffer Dall8a280d12013-10-25 21:22:31 +0100873 if (!mmio->is_write)
874 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
875 else
876 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true);
877}
878
879static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
880 struct kvm_exit_mmio *mmio,
881 phys_addr_t offset)
882{
883 if (!mmio->is_write)
884 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
885 else
886 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false);
Christoffer Dall0b3a5402013-10-25 21:17:31 +0100887}
888
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500889/*
890 * I would have liked to use the kvm_bus_io_*() API instead, but it
891 * cannot cope with banked registers (only the VM pointer is passed
892 * around, and we need the vcpu). One of these days, someone please
893 * fix it!
894 */
895struct mmio_range {
896 phys_addr_t base;
897 unsigned long len;
898 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
899 phys_addr_t offset);
900};
901
Christoffer Dall405003b2013-09-23 14:55:56 -0700902static const struct mmio_range vgic_dist_ranges[] = {
Marc Zyngierb47ef922013-01-21 19:36:14 -0500903 {
904 .base = GIC_DIST_CTRL,
905 .len = 12,
906 .handle_mmio = handle_mmio_misc,
907 },
908 {
909 .base = GIC_DIST_IGROUP,
910 .len = VGIC_NR_IRQS / 8,
911 .handle_mmio = handle_mmio_raz_wi,
912 },
913 {
914 .base = GIC_DIST_ENABLE_SET,
915 .len = VGIC_NR_IRQS / 8,
916 .handle_mmio = handle_mmio_set_enable_reg,
917 },
918 {
919 .base = GIC_DIST_ENABLE_CLEAR,
920 .len = VGIC_NR_IRQS / 8,
921 .handle_mmio = handle_mmio_clear_enable_reg,
922 },
923 {
924 .base = GIC_DIST_PENDING_SET,
925 .len = VGIC_NR_IRQS / 8,
926 .handle_mmio = handle_mmio_set_pending_reg,
927 },
928 {
929 .base = GIC_DIST_PENDING_CLEAR,
930 .len = VGIC_NR_IRQS / 8,
931 .handle_mmio = handle_mmio_clear_pending_reg,
932 },
933 {
934 .base = GIC_DIST_ACTIVE_SET,
935 .len = VGIC_NR_IRQS / 8,
936 .handle_mmio = handle_mmio_raz_wi,
937 },
938 {
939 .base = GIC_DIST_ACTIVE_CLEAR,
940 .len = VGIC_NR_IRQS / 8,
941 .handle_mmio = handle_mmio_raz_wi,
942 },
943 {
944 .base = GIC_DIST_PRI,
945 .len = VGIC_NR_IRQS,
946 .handle_mmio = handle_mmio_priority_reg,
947 },
948 {
949 .base = GIC_DIST_TARGET,
950 .len = VGIC_NR_IRQS,
951 .handle_mmio = handle_mmio_target_reg,
952 },
953 {
954 .base = GIC_DIST_CONFIG,
955 .len = VGIC_NR_IRQS / 4,
956 .handle_mmio = handle_mmio_cfg_reg,
957 },
958 {
959 .base = GIC_DIST_SOFTINT,
960 .len = 4,
961 .handle_mmio = handle_mmio_sgi_reg,
962 },
Christoffer Dall0b3a5402013-10-25 21:17:31 +0100963 {
964 .base = GIC_DIST_SGI_PENDING_CLEAR,
965 .len = VGIC_NR_SGIS,
966 .handle_mmio = handle_mmio_sgi_clear,
967 },
968 {
969 .base = GIC_DIST_SGI_PENDING_SET,
970 .len = VGIC_NR_SGIS,
971 .handle_mmio = handle_mmio_sgi_set,
972 },
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500973 {}
974};
975
976static const
977struct mmio_range *find_matching_range(const struct mmio_range *ranges,
978 struct kvm_exit_mmio *mmio,
Christoffer Dall405003b2013-09-23 14:55:56 -0700979 phys_addr_t offset)
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500980{
981 const struct mmio_range *r = ranges;
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500982
983 while (r->len) {
Christoffer Dall405003b2013-09-23 14:55:56 -0700984 if (offset >= r->base &&
985 (offset + mmio->len) <= (r->base + r->len))
Marc Zyngier1a89dd92013-01-21 19:36:12 -0500986 return r;
987 r++;
988 }
989
990 return NULL;
991}
992
993/**
994 * vgic_handle_mmio - handle an in-kernel MMIO access
995 * @vcpu: pointer to the vcpu performing the access
996 * @run: pointer to the kvm_run structure
997 * @mmio: pointer to the data describing the access
998 *
999 * returns true if the MMIO access has been performed in kernel space,
1000 * and false if it needs to be emulated in user space.
1001 */
1002bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
1003 struct kvm_exit_mmio *mmio)
1004{
Marc Zyngierb47ef922013-01-21 19:36:14 -05001005 const struct mmio_range *range;
1006 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1007 unsigned long base = dist->vgic_dist_base;
1008 bool updated_state;
1009 unsigned long offset;
1010
1011 if (!irqchip_in_kernel(vcpu->kvm) ||
1012 mmio->phys_addr < base ||
1013 (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
1014 return false;
1015
1016 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
1017 if (mmio->len > 4) {
1018 kvm_inject_dabt(vcpu, mmio->phys_addr);
1019 return true;
1020 }
1021
Christoffer Dall405003b2013-09-23 14:55:56 -07001022 offset = mmio->phys_addr - base;
1023 range = find_matching_range(vgic_dist_ranges, mmio, offset);
Marc Zyngierb47ef922013-01-21 19:36:14 -05001024 if (unlikely(!range || !range->handle_mmio)) {
1025 pr_warn("Unhandled access %d %08llx %d\n",
1026 mmio->is_write, mmio->phys_addr, mmio->len);
1027 return false;
1028 }
1029
1030 spin_lock(&vcpu->kvm->arch.vgic.lock);
1031 offset = mmio->phys_addr - range->base - base;
1032 updated_state = range->handle_mmio(vcpu, mmio, offset);
1033 spin_unlock(&vcpu->kvm->arch.vgic.lock);
1034 kvm_prepare_mmio(run, mmio);
1035 kvm_handle_mmio_return(vcpu, run);
1036
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001037 if (updated_state)
1038 vgic_kick_vcpus(vcpu->kvm);
1039
Marc Zyngierb47ef922013-01-21 19:36:14 -05001040 return true;
1041}
1042
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001043static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi)
1044{
1045 return dist->irq_sgi_sources + vcpu_id * VGIC_NR_SGIS + sgi;
1046}
1047
Marc Zyngierb47ef922013-01-21 19:36:14 -05001048static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
1049{
1050 struct kvm *kvm = vcpu->kvm;
1051 struct vgic_dist *dist = &kvm->arch.vgic;
1052 int nrcpus = atomic_read(&kvm->online_vcpus);
1053 u8 target_cpus;
1054 int sgi, mode, c, vcpu_id;
1055
1056 vcpu_id = vcpu->vcpu_id;
1057
1058 sgi = reg & 0xf;
1059 target_cpus = (reg >> 16) & 0xff;
1060 mode = (reg >> 24) & 3;
1061
1062 switch (mode) {
1063 case 0:
1064 if (!target_cpus)
1065 return;
Haibin Wang738a77a2014-04-10 13:14:32 +01001066 break;
Marc Zyngierb47ef922013-01-21 19:36:14 -05001067
1068 case 1:
1069 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
1070 break;
1071
1072 case 2:
1073 target_cpus = 1 << vcpu_id;
1074 break;
1075 }
1076
1077 kvm_for_each_vcpu(c, vcpu, kvm) {
1078 if (target_cpus & 1) {
1079 /* Flag the SGI as pending */
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001080 vgic_dist_irq_set_pending(vcpu, sgi);
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001081 *vgic_get_sgi_sources(dist, c, sgi) |= 1 << vcpu_id;
Marc Zyngierb47ef922013-01-21 19:36:14 -05001082 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
1083 }
1084
1085 target_cpus >>= 1;
1086 }
1087}
1088
Marc Zyngierac240952014-07-08 12:09:02 +01001089static int vgic_nr_shared_irqs(struct vgic_dist *dist)
1090{
1091 return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS;
1092}
1093
Marc Zyngierb47ef922013-01-21 19:36:14 -05001094static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
1095{
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001096 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1097 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
1098 unsigned long pending_private, pending_shared;
Marc Zyngierac240952014-07-08 12:09:02 +01001099 int nr_shared = vgic_nr_shared_irqs(dist);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001100 int vcpu_id;
1101
1102 vcpu_id = vcpu->vcpu_id;
1103 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
1104 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
1105
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001106 pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001107 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
1108 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
1109
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001110 pending = vgic_bitmap_get_shared_map(&dist->irq_pending);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001111 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
Marc Zyngierac240952014-07-08 12:09:02 +01001112 bitmap_and(pend_shared, pending, enabled, nr_shared);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001113 bitmap_and(pend_shared, pend_shared,
1114 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
Marc Zyngierac240952014-07-08 12:09:02 +01001115 nr_shared);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001116
1117 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
Marc Zyngierac240952014-07-08 12:09:02 +01001118 pending_shared = find_first_bit(pend_shared, nr_shared);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001119 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
Marc Zyngierac240952014-07-08 12:09:02 +01001120 pending_shared < vgic_nr_shared_irqs(dist));
Marc Zyngierb47ef922013-01-21 19:36:14 -05001121}
1122
1123/*
1124 * Update the interrupt state and determine which CPUs have pending
1125 * interrupts. Must be called with distributor lock held.
1126 */
1127static void vgic_update_state(struct kvm *kvm)
1128{
1129 struct vgic_dist *dist = &kvm->arch.vgic;
1130 struct kvm_vcpu *vcpu;
1131 int c;
1132
1133 if (!dist->enabled) {
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001134 set_bit(0, dist->irq_pending_on_cpu);
Marc Zyngierb47ef922013-01-21 19:36:14 -05001135 return;
1136 }
1137
1138 kvm_for_each_vcpu(c, vcpu, kvm) {
1139 if (compute_pending_for_cpu(vcpu)) {
1140 pr_debug("CPU%d has pending interrupts\n", c);
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001141 set_bit(c, dist->irq_pending_on_cpu);
Marc Zyngierb47ef922013-01-21 19:36:14 -05001142 }
1143 }
Marc Zyngier1a89dd92013-01-21 19:36:12 -05001144}
Christoffer Dall330690c2013-01-21 19:36:13 -05001145
Marc Zyngier9f92df72013-06-03 15:55:02 +01001146static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
1147{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001148 return vgic_ops->get_lr(vcpu, lr);
Marc Zyngier9f92df72013-06-03 15:55:02 +01001149}
1150
1151static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1152 struct vgic_lr vlr)
1153{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001154 vgic_ops->set_lr(vcpu, lr, vlr);
Marc Zyngier9f92df72013-06-03 15:55:02 +01001155}
1156
Marc Zyngier32d98f22013-06-04 10:29:39 +01001157static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1158 struct vgic_lr vlr)
1159{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001160 vgic_ops->sync_lr_elrsr(vcpu, lr, vlr);
Marc Zyngier32d98f22013-06-04 10:29:39 +01001161}
1162
1163static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1164{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001165 return vgic_ops->get_elrsr(vcpu);
Marc Zyngier32d98f22013-06-04 10:29:39 +01001166}
1167
Marc Zyngierb874bb52013-06-04 10:33:43 +01001168static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1169{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001170 return vgic_ops->get_eisr(vcpu);
Marc Zyngierb874bb52013-06-04 10:33:43 +01001171}
1172
Marc Zyngier3f79fb52013-06-04 11:02:10 +01001173static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu)
1174{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001175 return vgic_ops->get_interrupt_status(vcpu);
Marc Zyngier3f79fb52013-06-04 11:02:10 +01001176}
1177
Marc Zyngier900f2c62013-06-04 11:24:17 +01001178static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu)
1179{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001180 vgic_ops->enable_underflow(vcpu);
Marc Zyngier900f2c62013-06-04 11:24:17 +01001181}
1182
1183static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu)
1184{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001185 vgic_ops->disable_underflow(vcpu);
Marc Zyngier900f2c62013-06-04 11:24:17 +01001186}
1187
Marc Zyngier32a0e352014-02-04 17:48:10 +00001188static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1189{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001190 vgic_ops->get_vmcr(vcpu, vmcr);
Marc Zyngier32a0e352014-02-04 17:48:10 +00001191}
1192
1193static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1194{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001195 vgic_ops->set_vmcr(vcpu, vmcr);
Marc Zyngier32a0e352014-02-04 17:48:10 +00001196}
1197
Marc Zyngier6d6775f2013-06-04 11:36:38 +01001198static inline void vgic_enable(struct kvm_vcpu *vcpu)
1199{
Marc Zyngierab8bb402014-02-04 18:13:03 +00001200 vgic_ops->enable(vcpu);
Marc Zyngier6d6775f2013-06-04 11:36:38 +01001201}
1202
Marc Zyngier9f92df72013-06-03 15:55:02 +01001203static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1204{
1205 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1206 struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1207
1208 vlr.state = 0;
1209 vgic_set_lr(vcpu, lr_nr, vlr);
1210 clear_bit(lr_nr, vgic_cpu->lr_used);
1211 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1212}
Marc Zyngiera1fcb442013-01-21 19:36:15 -05001213
1214/*
1215 * An interrupt may have been disabled after being made pending on the
1216 * CPU interface (the classic case is a timer running while we're
1217 * rebooting the guest - the interrupt would kick as soon as the CPU
1218 * interface gets enabled, with deadly consequences).
1219 *
1220 * The solution is to examine already active LRs, and check the
1221 * interrupt is still enabled. If not, just retire it.
1222 */
1223static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1224{
1225 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1226 int lr;
1227
Marc Zyngierab8bb402014-02-04 18:13:03 +00001228 for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) {
Marc Zyngier9f92df72013-06-03 15:55:02 +01001229 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
Marc Zyngiera1fcb442013-01-21 19:36:15 -05001230
Marc Zyngier9f92df72013-06-03 15:55:02 +01001231 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1232 vgic_retire_lr(lr, vlr.irq, vcpu);
Christoffer Dall25b3fb82014-06-09 12:55:13 +02001233 if (vgic_irq_is_queued(vcpu, vlr.irq))
1234 vgic_irq_clear_queued(vcpu, vlr.irq);
Marc Zyngiera1fcb442013-01-21 19:36:15 -05001235 }
1236 }
1237}
1238
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001239/*
1240 * Queue an interrupt to a CPU virtual interface. Return true on success,
1241 * or false if it wasn't possible to queue it.
1242 */
1243static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1244{
1245 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
Marc Zyngier9f92df72013-06-03 15:55:02 +01001246 struct vgic_lr vlr;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001247 int lr;
1248
1249 /* Sanitize the input... */
1250 BUG_ON(sgi_source_id & ~7);
1251 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1252 BUG_ON(irq >= VGIC_NR_IRQS);
1253
1254 kvm_debug("Queue IRQ%d\n", irq);
1255
1256 lr = vgic_cpu->vgic_irq_lr_map[irq];
1257
1258 /* Do we have an active interrupt for the same CPUID? */
Marc Zyngier9f92df72013-06-03 15:55:02 +01001259 if (lr != LR_EMPTY) {
1260 vlr = vgic_get_lr(vcpu, lr);
1261 if (vlr.source == sgi_source_id) {
1262 kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1263 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1264 vlr.state |= LR_STATE_PENDING;
1265 vgic_set_lr(vcpu, lr, vlr);
1266 return true;
1267 }
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001268 }
1269
1270 /* Try to use another LR for this interrupt */
1271 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
Marc Zyngierab8bb402014-02-04 18:13:03 +00001272 vgic->nr_lr);
1273 if (lr >= vgic->nr_lr)
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001274 return false;
1275
1276 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001277 vgic_cpu->vgic_irq_lr_map[irq] = lr;
1278 set_bit(lr, vgic_cpu->lr_used);
1279
Marc Zyngier9f92df72013-06-03 15:55:02 +01001280 vlr.irq = irq;
1281 vlr.source = sgi_source_id;
1282 vlr.state = LR_STATE_PENDING;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001283 if (!vgic_irq_is_edge(vcpu, irq))
Marc Zyngier9f92df72013-06-03 15:55:02 +01001284 vlr.state |= LR_EOI_INT;
1285
1286 vgic_set_lr(vcpu, lr, vlr);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001287
1288 return true;
1289}
1290
1291static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
1292{
1293 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1294 unsigned long sources;
1295 int vcpu_id = vcpu->vcpu_id;
1296 int c;
1297
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001298 sources = *vgic_get_sgi_sources(dist, vcpu_id, irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001299
Marc Zyngier3e0fb552014-07-08 12:09:03 +01001300 for_each_set_bit(c, &sources, dist->nr_cpus) {
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001301 if (vgic_queue_irq(vcpu, c, irq))
1302 clear_bit(c, &sources);
1303 }
1304
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001305 *vgic_get_sgi_sources(dist, vcpu_id, irq) = sources;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001306
1307 /*
1308 * If the sources bitmap has been cleared it means that we
1309 * could queue all the SGIs onto link registers (see the
1310 * clear_bit above), and therefore we are done with them in
1311 * our emulated gic and can get rid of them.
1312 */
1313 if (!sources) {
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001314 vgic_dist_irq_clear_pending(vcpu, irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001315 vgic_cpu_irq_clear(vcpu, irq);
1316 return true;
1317 }
1318
1319 return false;
1320}
1321
1322static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1323{
Christoffer Dall25b3fb82014-06-09 12:55:13 +02001324 if (!vgic_can_sample_irq(vcpu, irq))
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001325 return true; /* level interrupt, already queued */
1326
1327 if (vgic_queue_irq(vcpu, 0, irq)) {
1328 if (vgic_irq_is_edge(vcpu, irq)) {
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001329 vgic_dist_irq_clear_pending(vcpu, irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001330 vgic_cpu_irq_clear(vcpu, irq);
1331 } else {
Christoffer Dall25b3fb82014-06-09 12:55:13 +02001332 vgic_irq_set_queued(vcpu, irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001333 }
1334
1335 return true;
1336 }
1337
1338 return false;
1339}
1340
1341/*
1342 * Fill the list registers with pending interrupts before running the
1343 * guest.
1344 */
1345static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1346{
1347 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1348 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1349 int i, vcpu_id;
1350 int overflow = 0;
1351
1352 vcpu_id = vcpu->vcpu_id;
1353
1354 /*
1355 * We may not have any pending interrupt, or the interrupts
1356 * may have been serviced from another vcpu. In all cases,
1357 * move along.
1358 */
1359 if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
1360 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
1361 goto epilog;
1362 }
1363
1364 /* SGIs */
1365 for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
1366 if (!vgic_queue_sgi(vcpu, i))
1367 overflow = 1;
1368 }
1369
1370 /* PPIs */
1371 for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
1372 if (!vgic_queue_hwirq(vcpu, i))
1373 overflow = 1;
1374 }
1375
1376 /* SPIs */
Marc Zyngierac240952014-07-08 12:09:02 +01001377 for_each_set_bit(i, vgic_cpu->pending_shared, vgic_nr_shared_irqs(dist)) {
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001378 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1379 overflow = 1;
1380 }
1381
1382epilog:
1383 if (overflow) {
Marc Zyngier900f2c62013-06-04 11:24:17 +01001384 vgic_enable_underflow(vcpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001385 } else {
Marc Zyngier900f2c62013-06-04 11:24:17 +01001386 vgic_disable_underflow(vcpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001387 /*
1388 * We're about to run this VCPU, and we've consumed
1389 * everything the distributor had in store for
1390 * us. Claim we don't have anything pending. We'll
1391 * adjust that if needed while exiting.
1392 */
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001393 clear_bit(vcpu_id, dist->irq_pending_on_cpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001394 }
1395}
1396
1397static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1398{
Marc Zyngier3f79fb52013-06-04 11:02:10 +01001399 u32 status = vgic_get_interrupt_status(vcpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001400 bool level_pending = false;
1401
Marc Zyngier3f79fb52013-06-04 11:02:10 +01001402 kvm_debug("STATUS = %08x\n", status);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001403
Marc Zyngier3f79fb52013-06-04 11:02:10 +01001404 if (status & INT_STATUS_EOI) {
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001405 /*
1406 * Some level interrupts have been EOIed. Clear their
1407 * active bit.
1408 */
Marc Zyngierb874bb52013-06-04 10:33:43 +01001409 u64 eisr = vgic_get_eisr(vcpu);
1410 unsigned long *eisr_ptr = (unsigned long *)&eisr;
Marc Zyngier9f92df72013-06-03 15:55:02 +01001411 int lr;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001412
Marc Zyngierab8bb402014-02-04 18:13:03 +00001413 for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) {
Marc Zyngier9f92df72013-06-03 15:55:02 +01001414 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001415 WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq));
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001416
Christoffer Dall25b3fb82014-06-09 12:55:13 +02001417 vgic_irq_clear_queued(vcpu, vlr.irq);
Marc Zyngier9f92df72013-06-03 15:55:02 +01001418 WARN_ON(vlr.state & LR_STATE_MASK);
1419 vlr.state = 0;
1420 vgic_set_lr(vcpu, lr, vlr);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001421
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001422 /*
1423 * If the IRQ was EOIed it was also ACKed and we we
1424 * therefore assume we can clear the soft pending
1425 * state (should it had been set) for this interrupt.
1426 *
1427 * Note: if the IRQ soft pending state was set after
1428 * the IRQ was acked, it actually shouldn't be
1429 * cleared, but we have no way of knowing that unless
1430 * we start trapping ACKs when the soft-pending state
1431 * is set.
1432 */
1433 vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq);
1434
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001435 /* Any additional pending interrupt? */
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001436 if (vgic_dist_irq_get_level(vcpu, vlr.irq)) {
Marc Zyngier9f92df72013-06-03 15:55:02 +01001437 vgic_cpu_irq_set(vcpu, vlr.irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001438 level_pending = true;
1439 } else {
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001440 vgic_dist_irq_clear_pending(vcpu, vlr.irq);
Marc Zyngier9f92df72013-06-03 15:55:02 +01001441 vgic_cpu_irq_clear(vcpu, vlr.irq);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001442 }
Marc Zyngier75da01e2013-01-31 11:25:52 +00001443
1444 /*
1445 * Despite being EOIed, the LR may not have
1446 * been marked as empty.
1447 */
Marc Zyngier32d98f22013-06-04 10:29:39 +01001448 vgic_sync_lr_elrsr(vcpu, lr, vlr);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001449 }
1450 }
1451
Marc Zyngier3f79fb52013-06-04 11:02:10 +01001452 if (status & INT_STATUS_UNDERFLOW)
Marc Zyngier900f2c62013-06-04 11:24:17 +01001453 vgic_disable_underflow(vcpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001454
1455 return level_pending;
1456}
1457
1458/*
Marc Zyngier33c83cb2013-02-01 18:28:30 +00001459 * Sync back the VGIC state after a guest run. The distributor lock is
1460 * needed so we don't get preempted in the middle of the state processing.
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001461 */
1462static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1463{
1464 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1465 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
Marc Zyngier32d98f22013-06-04 10:29:39 +01001466 u64 elrsr;
1467 unsigned long *elrsr_ptr;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001468 int lr, pending;
1469 bool level_pending;
1470
1471 level_pending = vgic_process_maintenance(vcpu);
Marc Zyngier32d98f22013-06-04 10:29:39 +01001472 elrsr = vgic_get_elrsr(vcpu);
1473 elrsr_ptr = (unsigned long *)&elrsr;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001474
1475 /* Clear mappings for empty LRs */
Marc Zyngierab8bb402014-02-04 18:13:03 +00001476 for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) {
Marc Zyngier9f92df72013-06-03 15:55:02 +01001477 struct vgic_lr vlr;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001478
1479 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1480 continue;
1481
Marc Zyngier9f92df72013-06-03 15:55:02 +01001482 vlr = vgic_get_lr(vcpu, lr);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001483
Marc Zyngier9f92df72013-06-03 15:55:02 +01001484 BUG_ON(vlr.irq >= VGIC_NR_IRQS);
1485 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001486 }
1487
1488 /* Check if we still have something up our sleeve... */
Marc Zyngierab8bb402014-02-04 18:13:03 +00001489 pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr);
1490 if (level_pending || pending < vgic->nr_lr)
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001491 set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001492}
1493
1494void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1495{
1496 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1497
1498 if (!irqchip_in_kernel(vcpu->kvm))
1499 return;
1500
1501 spin_lock(&dist->lock);
1502 __kvm_vgic_flush_hwstate(vcpu);
1503 spin_unlock(&dist->lock);
1504}
1505
1506void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1507{
Marc Zyngier33c83cb2013-02-01 18:28:30 +00001508 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1509
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001510 if (!irqchip_in_kernel(vcpu->kvm))
1511 return;
1512
Marc Zyngier33c83cb2013-02-01 18:28:30 +00001513 spin_lock(&dist->lock);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001514 __kvm_vgic_sync_hwstate(vcpu);
Marc Zyngier33c83cb2013-02-01 18:28:30 +00001515 spin_unlock(&dist->lock);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001516}
1517
1518int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1519{
1520 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1521
1522 if (!irqchip_in_kernel(vcpu->kvm))
1523 return 0;
1524
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001525 return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
Marc Zyngier9d949dc2013-01-21 19:36:14 -05001526}
1527
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001528static void vgic_kick_vcpus(struct kvm *kvm)
1529{
1530 struct kvm_vcpu *vcpu;
1531 int c;
1532
1533 /*
1534 * We've injected an interrupt, time to find out who deserves
1535 * a good kick...
1536 */
1537 kvm_for_each_vcpu(c, vcpu, kvm) {
1538 if (kvm_vgic_vcpu_pending_irq(vcpu))
1539 kvm_vcpu_kick(vcpu);
1540 }
1541}
1542
1543static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1544{
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001545 int edge_triggered = vgic_irq_is_edge(vcpu, irq);
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001546
1547 /*
1548 * Only inject an interrupt if:
1549 * - edge triggered and we have a rising edge
1550 * - level triggered and we change level
1551 */
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001552 if (edge_triggered) {
1553 int state = vgic_dist_irq_is_pending(vcpu, irq);
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001554 return level > state;
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001555 } else {
1556 int state = vgic_dist_irq_get_level(vcpu, irq);
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001557 return level != state;
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001558 }
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001559}
1560
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001561static bool vgic_update_irq_pending(struct kvm *kvm, int cpuid,
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001562 unsigned int irq_num, bool level)
1563{
1564 struct vgic_dist *dist = &kvm->arch.vgic;
1565 struct kvm_vcpu *vcpu;
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001566 int edge_triggered, level_triggered;
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001567 int enabled;
1568 bool ret = true;
1569
1570 spin_lock(&dist->lock);
1571
1572 vcpu = kvm_get_vcpu(kvm, cpuid);
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001573 edge_triggered = vgic_irq_is_edge(vcpu, irq_num);
1574 level_triggered = !edge_triggered;
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001575
1576 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1577 ret = false;
1578 goto out;
1579 }
1580
1581 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1582 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1583 vcpu = kvm_get_vcpu(kvm, cpuid);
1584 }
1585
1586 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1587
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001588 if (level) {
1589 if (level_triggered)
1590 vgic_dist_irq_set_level(vcpu, irq_num);
Christoffer Dallfa0603d2014-06-09 12:27:18 +02001591 vgic_dist_irq_set_pending(vcpu, irq_num);
Christoffer Dallfe8a7fe2014-06-14 21:54:51 +02001592 } else {
1593 if (level_triggered) {
1594 vgic_dist_irq_clear_level(vcpu, irq_num);
1595 if (!vgic_dist_irq_soft_pend(vcpu, irq_num))
1596 vgic_dist_irq_clear_pending(vcpu, irq_num);
1597 } else {
1598 vgic_dist_irq_clear_pending(vcpu, irq_num);
1599 }
1600 }
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001601
1602 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1603
1604 if (!enabled) {
1605 ret = false;
1606 goto out;
1607 }
1608
Christoffer Dall25b3fb82014-06-09 12:55:13 +02001609 if (!vgic_can_sample_irq(vcpu, irq_num)) {
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001610 /*
1611 * Level interrupt in progress, will be picked up
1612 * when EOId.
1613 */
1614 ret = false;
1615 goto out;
1616 }
1617
1618 if (level) {
1619 vgic_cpu_irq_set(vcpu, irq_num);
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001620 set_bit(cpuid, dist->irq_pending_on_cpu);
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001621 }
1622
1623out:
1624 spin_unlock(&dist->lock);
1625
1626 return ret;
1627}
1628
1629/**
1630 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1631 * @kvm: The VM structure pointer
1632 * @cpuid: The CPU for PPIs
1633 * @irq_num: The IRQ number that is assigned to the device
1634 * @level: Edge-triggered: true: to trigger the interrupt
1635 * false: to ignore the call
1636 * Level-sensitive true: activates an interrupt
1637 * false: deactivates an interrupt
1638 *
1639 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1640 * level-sensitive interrupts. You can think of the level parameter as 1
1641 * being HIGH and 0 being LOW and all devices being active-HIGH.
1642 */
1643int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1644 bool level)
1645{
Marc Zyngieraef14f42014-07-08 12:09:00 +01001646 if (likely(vgic_initialized(kvm)) &&
1647 vgic_update_irq_pending(kvm, cpuid, irq_num, level))
Marc Zyngier5863c2c2013-01-21 19:36:15 -05001648 vgic_kick_vcpus(kvm);
1649
1650 return 0;
1651}
1652
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001653static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1654{
1655 /*
1656 * We cannot rely on the vgic maintenance interrupt to be
1657 * delivered synchronously. This means we can only use it to
1658 * exit the VM, and we perform the handling of EOIed
1659 * interrupts on the exit path (see vgic_process_maintenance).
1660 */
1661 return IRQ_HANDLED;
1662}
1663
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001664void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
1665{
1666 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1667
1668 kfree(vgic_cpu->pending_shared);
1669 kfree(vgic_cpu->vgic_irq_lr_map);
1670 vgic_cpu->pending_shared = NULL;
1671 vgic_cpu->vgic_irq_lr_map = NULL;
1672}
1673
1674static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
1675{
1676 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1677
1678 int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8;
1679 vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL);
1680 vgic_cpu->vgic_irq_lr_map = kzalloc(nr_irqs, GFP_KERNEL);
1681
1682 if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) {
1683 kvm_vgic_vcpu_destroy(vcpu);
1684 return -ENOMEM;
1685 }
1686
1687 return 0;
1688}
1689
Christoffer Dalld90651f2013-09-23 14:55:55 -07001690/**
1691 * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1692 * @vcpu: pointer to the vcpu struct
1693 *
1694 * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1695 * this vcpu and enable the VGIC for this VCPU
1696 */
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001697int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
1698{
1699 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1700 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1701 int i;
1702
Marc Zyngier3e0fb552014-07-08 12:09:03 +01001703 if (vcpu->vcpu_id >= dist->nr_cpus)
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001704 return -EBUSY;
1705
1706 for (i = 0; i < VGIC_NR_IRQS; i++) {
1707 if (i < VGIC_NR_PPIS)
1708 vgic_bitmap_set_irq_val(&dist->irq_enabled,
1709 vcpu->vcpu_id, i, 1);
1710 if (i < VGIC_NR_PRIVATE_IRQS)
1711 vgic_bitmap_set_irq_val(&dist->irq_cfg,
1712 vcpu->vcpu_id, i, VGIC_CFG_EDGE);
1713
1714 vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
1715 }
1716
Marc Zyngier6e707c12013-06-18 19:17:28 +01001717 /*
1718 * Store the number of LRs per vcpu, so we don't have to go
1719 * all the way to the distributor structure to find out. Only
1720 * assembly code should use this one.
1721 */
Marc Zyngierab8bb402014-02-04 18:13:03 +00001722 vgic_cpu->nr_lr = vgic->nr_lr;
Marc Zyngier6d6775f2013-06-04 11:36:38 +01001723
1724 vgic_enable(vcpu);
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001725
1726 return 0;
1727}
1728
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001729void kvm_vgic_destroy(struct kvm *kvm)
1730{
1731 struct vgic_dist *dist = &kvm->arch.vgic;
1732 struct kvm_vcpu *vcpu;
1733 int i;
1734
1735 kvm_for_each_vcpu(i, vcpu, kvm)
1736 kvm_vgic_vcpu_destroy(vcpu);
1737
1738 vgic_free_bitmap(&dist->irq_enabled);
1739 vgic_free_bitmap(&dist->irq_level);
1740 vgic_free_bitmap(&dist->irq_pending);
1741 vgic_free_bitmap(&dist->irq_soft_pend);
1742 vgic_free_bitmap(&dist->irq_queued);
1743 vgic_free_bitmap(&dist->irq_cfg);
1744 vgic_free_bytemap(&dist->irq_priority);
1745 if (dist->irq_spi_target) {
1746 for (i = 0; i < dist->nr_cpus; i++)
1747 vgic_free_bitmap(&dist->irq_spi_target[i]);
1748 }
1749 kfree(dist->irq_sgi_sources);
1750 kfree(dist->irq_spi_cpu);
1751 kfree(dist->irq_spi_target);
1752 kfree(dist->irq_pending_on_cpu);
1753 dist->irq_sgi_sources = NULL;
1754 dist->irq_spi_cpu = NULL;
1755 dist->irq_spi_target = NULL;
1756 dist->irq_pending_on_cpu = NULL;
1757}
1758
1759/*
1760 * Allocate and initialize the various data structures. Must be called
1761 * with kvm->lock held!
1762 */
1763static int vgic_init_maps(struct kvm *kvm)
1764{
1765 struct vgic_dist *dist = &kvm->arch.vgic;
1766 struct kvm_vcpu *vcpu;
1767 int nr_cpus, nr_irqs;
1768 int ret, i;
1769
Marc Zyngier3e0fb552014-07-08 12:09:03 +01001770 nr_cpus = dist->nr_cpus = KVM_MAX_VCPUS;
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001771 nr_irqs = dist->nr_irqs = VGIC_NR_IRQS;
1772
1773 ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs);
1774 ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs);
1775 ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs);
1776 ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs);
1777 ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs);
1778 ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs);
1779 ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs);
1780
1781 if (ret)
1782 goto out;
1783
1784 dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL);
1785 dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL);
1786 dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus,
1787 GFP_KERNEL);
1788 dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
1789 GFP_KERNEL);
1790 if (!dist->irq_sgi_sources ||
1791 !dist->irq_spi_cpu ||
1792 !dist->irq_spi_target ||
1793 !dist->irq_pending_on_cpu) {
1794 ret = -ENOMEM;
1795 goto out;
1796 }
1797
1798 for (i = 0; i < nr_cpus; i++)
1799 ret |= vgic_init_bitmap(&dist->irq_spi_target[i],
1800 nr_cpus, nr_irqs);
1801
1802 if (ret)
1803 goto out;
1804
1805 kvm_for_each_vcpu(i, vcpu, kvm) {
1806 ret = vgic_vcpu_init_maps(vcpu, nr_irqs);
1807 if (ret) {
1808 kvm_err("VGIC: Failed to allocate vcpu memory\n");
1809 break;
1810 }
1811 }
1812
1813out:
1814 if (ret)
1815 kvm_vgic_destroy(kvm);
1816
1817 return ret;
1818}
1819
Christoffer Dalld90651f2013-09-23 14:55:55 -07001820/**
1821 * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1822 * @kvm: pointer to the kvm struct
1823 *
1824 * Map the virtual CPU interface into the VM before running any VCPUs. We
1825 * can't do this at creation time, because user space must first set the
1826 * virtual CPU interface address in the guest physical address space. Also
1827 * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1828 */
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001829int kvm_vgic_init(struct kvm *kvm)
1830{
1831 int ret = 0, i;
1832
Christoffer Dalld90651f2013-09-23 14:55:55 -07001833 if (!irqchip_in_kernel(kvm))
1834 return 0;
1835
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001836 mutex_lock(&kvm->lock);
1837
1838 if (vgic_initialized(kvm))
1839 goto out;
1840
1841 if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1842 IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1843 kvm_err("Need to set vgic cpu and dist addresses first\n");
1844 ret = -ENXIO;
1845 goto out;
1846 }
1847
1848 ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
Marc Zyngierab8bb402014-02-04 18:13:03 +00001849 vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE);
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001850 if (ret) {
1851 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1852 goto out;
1853 }
1854
1855 for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
1856 vgic_set_target_reg(kvm, 0, i);
1857
1858 kvm->arch.vgic.ready = true;
1859out:
1860 mutex_unlock(&kvm->lock);
1861 return ret;
1862}
1863
1864int kvm_vgic_create(struct kvm *kvm)
1865{
Christoffer Dall1032acb2013-10-25 17:29:18 +01001866 int i, vcpu_lock_idx = -1, ret = 0;
1867 struct kvm_vcpu *vcpu;
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001868
1869 mutex_lock(&kvm->lock);
1870
Christoffer Dall1032acb2013-10-25 17:29:18 +01001871 if (kvm->arch.vgic.vctrl_base) {
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001872 ret = -EEXIST;
1873 goto out;
1874 }
1875
Christoffer Dall1032acb2013-10-25 17:29:18 +01001876 /*
1877 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1878 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1879 * that no other VCPUs are run while we create the vgic.
1880 */
1881 kvm_for_each_vcpu(i, vcpu, kvm) {
1882 if (!mutex_trylock(&vcpu->mutex))
1883 goto out_unlock;
1884 vcpu_lock_idx = i;
1885 }
1886
1887 kvm_for_each_vcpu(i, vcpu, kvm) {
1888 if (vcpu->arch.has_run_once) {
1889 ret = -EBUSY;
1890 goto out_unlock;
1891 }
1892 }
1893
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001894 spin_lock_init(&kvm->arch.vgic.lock);
Marc Zyngier79f17b62014-05-15 10:03:25 +01001895 kvm->arch.vgic.in_kernel = true;
Marc Zyngierab8bb402014-02-04 18:13:03 +00001896 kvm->arch.vgic.vctrl_base = vgic->vctrl_base;
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001897 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1898 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1899
Marc Zyngier38cb2f72014-07-08 12:09:01 +01001900 ret = vgic_init_maps(kvm);
1901 if (ret)
1902 kvm_err("Unable to allocate maps\n");
1903
Christoffer Dall1032acb2013-10-25 17:29:18 +01001904out_unlock:
1905 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1906 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1907 mutex_unlock(&vcpu->mutex);
1908 }
1909
Marc Zyngier01ac5e32013-01-21 19:36:16 -05001910out:
1911 mutex_unlock(&kvm->lock);
1912 return ret;
1913}
1914
Will Deacon02b1b152014-08-26 15:13:24 +01001915static int vgic_ioaddr_overlap(struct kvm *kvm)
Christoffer Dall330690c2013-01-21 19:36:13 -05001916{
1917 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1918 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1919
1920 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1921 return 0;
1922 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1923 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1924 return -EBUSY;
1925 return 0;
1926}
1927
1928static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1929 phys_addr_t addr, phys_addr_t size)
1930{
1931 int ret;
1932
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07001933 if (addr & ~KVM_PHYS_MASK)
1934 return -E2BIG;
1935
1936 if (addr & (SZ_4K - 1))
1937 return -EINVAL;
1938
Christoffer Dall330690c2013-01-21 19:36:13 -05001939 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
1940 return -EEXIST;
1941 if (addr + size < addr)
1942 return -EINVAL;
1943
Haibin Wangde055bd2014-04-29 14:49:17 +08001944 *ioaddr = addr;
Christoffer Dall330690c2013-01-21 19:36:13 -05001945 ret = vgic_ioaddr_overlap(kvm);
1946 if (ret)
Haibin Wangde055bd2014-04-29 14:49:17 +08001947 *ioaddr = VGIC_ADDR_UNDEF;
1948
Christoffer Dall330690c2013-01-21 19:36:13 -05001949 return ret;
1950}
1951
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07001952/**
1953 * kvm_vgic_addr - set or get vgic VM base addresses
1954 * @kvm: pointer to the vm struct
1955 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1956 * @addr: pointer to address value
1957 * @write: if true set the address in the VM address space, if false read the
1958 * address
1959 *
1960 * Set or get the vgic base addresses for the distributor and the virtual CPU
1961 * interface in the VM physical address space. These addresses are properties
1962 * of the emulated core/SoC and therefore user space initially knows this
1963 * information.
1964 */
1965int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
Christoffer Dall330690c2013-01-21 19:36:13 -05001966{
1967 int r = 0;
1968 struct vgic_dist *vgic = &kvm->arch.vgic;
1969
Christoffer Dall330690c2013-01-21 19:36:13 -05001970 mutex_lock(&kvm->lock);
1971 switch (type) {
1972 case KVM_VGIC_V2_ADDR_TYPE_DIST:
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07001973 if (write) {
1974 r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
1975 *addr, KVM_VGIC_V2_DIST_SIZE);
1976 } else {
1977 *addr = vgic->vgic_dist_base;
1978 }
Christoffer Dall330690c2013-01-21 19:36:13 -05001979 break;
1980 case KVM_VGIC_V2_ADDR_TYPE_CPU:
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07001981 if (write) {
1982 r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
1983 *addr, KVM_VGIC_V2_CPU_SIZE);
1984 } else {
1985 *addr = vgic->vgic_cpu_base;
1986 }
Christoffer Dall330690c2013-01-21 19:36:13 -05001987 break;
1988 default:
1989 r = -ENODEV;
1990 }
1991
1992 mutex_unlock(&kvm->lock);
1993 return r;
1994}
Christoffer Dall1032acb2013-10-25 17:29:18 +01001995
Christoffer Dall0b3a5402013-10-25 21:17:31 +01001996static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
1997 struct kvm_exit_mmio *mmio, phys_addr_t offset)
1998{
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07001999 bool updated = false;
Marc Zyngier32a0e352014-02-04 17:48:10 +00002000 struct vgic_vmcr vmcr;
2001 u32 *vmcr_field;
2002 u32 reg;
2003
2004 vgic_get_vmcr(vcpu, &vmcr);
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002005
2006 switch (offset & ~0x3) {
2007 case GIC_CPU_CTRL:
Marc Zyngier32a0e352014-02-04 17:48:10 +00002008 vmcr_field = &vmcr.ctlr;
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002009 break;
2010 case GIC_CPU_PRIMASK:
Marc Zyngier32a0e352014-02-04 17:48:10 +00002011 vmcr_field = &vmcr.pmr;
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002012 break;
2013 case GIC_CPU_BINPOINT:
Marc Zyngier32a0e352014-02-04 17:48:10 +00002014 vmcr_field = &vmcr.bpr;
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002015 break;
2016 case GIC_CPU_ALIAS_BINPOINT:
Marc Zyngier32a0e352014-02-04 17:48:10 +00002017 vmcr_field = &vmcr.abpr;
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002018 break;
Marc Zyngier32a0e352014-02-04 17:48:10 +00002019 default:
2020 BUG();
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002021 }
2022
2023 if (!mmio->is_write) {
Marc Zyngier32a0e352014-02-04 17:48:10 +00002024 reg = *vmcr_field;
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002025 mmio_data_write(mmio, ~0, reg);
2026 } else {
2027 reg = mmio_data_read(mmio, ~0);
Marc Zyngier32a0e352014-02-04 17:48:10 +00002028 if (reg != *vmcr_field) {
2029 *vmcr_field = reg;
2030 vgic_set_vmcr(vcpu, &vmcr);
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002031 updated = true;
Marc Zyngier32a0e352014-02-04 17:48:10 +00002032 }
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002033 }
2034 return updated;
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002035}
2036
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002037static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
2038 struct kvm_exit_mmio *mmio, phys_addr_t offset)
2039{
2040 return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
2041}
2042
2043static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
2044 struct kvm_exit_mmio *mmio,
2045 phys_addr_t offset)
2046{
2047 u32 reg;
2048
2049 if (mmio->is_write)
2050 return false;
2051
2052 /* GICC_IIDR */
2053 reg = (PRODUCT_ID_KVM << 20) |
2054 (GICC_ARCH_VERSION_V2 << 16) |
2055 (IMPLEMENTER_ARM << 0);
2056 mmio_data_write(mmio, ~0, reg);
2057 return false;
2058}
2059
2060/*
2061 * CPU Interface Register accesses - these are not accessed by the VM, but by
2062 * user space for saving and restoring VGIC state.
2063 */
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002064static const struct mmio_range vgic_cpu_ranges[] = {
2065 {
2066 .base = GIC_CPU_CTRL,
2067 .len = 12,
2068 .handle_mmio = handle_cpu_mmio_misc,
2069 },
2070 {
2071 .base = GIC_CPU_ALIAS_BINPOINT,
2072 .len = 4,
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002073 .handle_mmio = handle_mmio_abpr,
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002074 },
2075 {
2076 .base = GIC_CPU_ACTIVEPRIO,
2077 .len = 16,
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002078 .handle_mmio = handle_mmio_raz_wi,
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002079 },
2080 {
2081 .base = GIC_CPU_IDENT,
2082 .len = 4,
Christoffer Dalla0a11ba2013-09-23 14:55:57 -07002083 .handle_mmio = handle_cpu_mmio_ident,
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002084 },
2085};
2086
2087static int vgic_attr_regs_access(struct kvm_device *dev,
2088 struct kvm_device_attr *attr,
2089 u32 *reg, bool is_write)
2090{
2091 const struct mmio_range *r = NULL, *ranges;
2092 phys_addr_t offset;
2093 int ret, cpuid, c;
2094 struct kvm_vcpu *vcpu, *tmp_vcpu;
2095 struct vgic_dist *vgic;
2096 struct kvm_exit_mmio mmio;
2097
2098 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2099 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
2100 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
2101
2102 mutex_lock(&dev->kvm->lock);
2103
2104 if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
2105 ret = -EINVAL;
2106 goto out;
2107 }
2108
2109 vcpu = kvm_get_vcpu(dev->kvm, cpuid);
2110 vgic = &dev->kvm->arch.vgic;
2111
2112 mmio.len = 4;
2113 mmio.is_write = is_write;
2114 if (is_write)
2115 mmio_data_write(&mmio, ~0, *reg);
2116 switch (attr->group) {
2117 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2118 mmio.phys_addr = vgic->vgic_dist_base + offset;
2119 ranges = vgic_dist_ranges;
2120 break;
2121 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2122 mmio.phys_addr = vgic->vgic_cpu_base + offset;
2123 ranges = vgic_cpu_ranges;
2124 break;
2125 default:
2126 BUG();
2127 }
2128 r = find_matching_range(ranges, &mmio, offset);
2129
2130 if (unlikely(!r || !r->handle_mmio)) {
2131 ret = -ENXIO;
2132 goto out;
2133 }
2134
2135
2136 spin_lock(&vgic->lock);
2137
2138 /*
2139 * Ensure that no other VCPU is running by checking the vcpu->cpu
2140 * field. If no other VPCUs are running we can safely access the VGIC
2141 * state, because even if another VPU is run after this point, that
2142 * VCPU will not touch the vgic state, because it will block on
2143 * getting the vgic->lock in kvm_vgic_sync_hwstate().
2144 */
2145 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) {
2146 if (unlikely(tmp_vcpu->cpu != -1)) {
2147 ret = -EBUSY;
2148 goto out_vgic_unlock;
2149 }
2150 }
2151
Christoffer Dall944b8a62013-11-15 20:51:31 -08002152 /*
2153 * Move all pending IRQs from the LRs on all VCPUs so the pending
2154 * state can be properly represented in the register state accessible
2155 * through this API.
2156 */
2157 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm)
2158 vgic_unqueue_irqs(tmp_vcpu);
2159
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002160 offset -= r->base;
2161 r->handle_mmio(vcpu, &mmio, offset);
2162
2163 if (!is_write)
2164 *reg = mmio_data_read(&mmio, ~0);
2165
2166 ret = 0;
2167out_vgic_unlock:
2168 spin_unlock(&vgic->lock);
2169out:
2170 mutex_unlock(&dev->kvm->lock);
2171 return ret;
2172}
2173
Christoffer Dall1032acb2013-10-25 17:29:18 +01002174static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2175{
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07002176 int r;
2177
2178 switch (attr->group) {
2179 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2180 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2181 u64 addr;
2182 unsigned long type = (unsigned long)attr->attr;
2183
2184 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2185 return -EFAULT;
2186
2187 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
2188 return (r == -ENODEV) ? -ENXIO : r;
2189 }
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002190
2191 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2192 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2193 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2194 u32 reg;
2195
2196 if (get_user(reg, uaddr))
2197 return -EFAULT;
2198
2199 return vgic_attr_regs_access(dev, attr, &reg, true);
2200 }
2201
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07002202 }
2203
Christoffer Dall1032acb2013-10-25 17:29:18 +01002204 return -ENXIO;
2205}
2206
2207static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2208{
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07002209 int r = -ENXIO;
2210
2211 switch (attr->group) {
2212 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2213 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2214 u64 addr;
2215 unsigned long type = (unsigned long)attr->attr;
2216
2217 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
2218 if (r)
2219 return (r == -ENODEV) ? -ENXIO : r;
2220
2221 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2222 return -EFAULT;
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002223 break;
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07002224 }
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002225
2226 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2227 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2228 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2229 u32 reg = 0;
2230
2231 r = vgic_attr_regs_access(dev, attr, &reg, false);
2232 if (r)
2233 return r;
2234 r = put_user(reg, uaddr);
2235 break;
2236 }
2237
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07002238 }
2239
2240 return r;
Christoffer Dall1032acb2013-10-25 17:29:18 +01002241}
2242
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002243static int vgic_has_attr_regs(const struct mmio_range *ranges,
2244 phys_addr_t offset)
2245{
2246 struct kvm_exit_mmio dev_attr_mmio;
2247
2248 dev_attr_mmio.len = 4;
2249 if (find_matching_range(ranges, &dev_attr_mmio, offset))
2250 return 0;
2251 else
2252 return -ENXIO;
2253}
2254
Christoffer Dall1032acb2013-10-25 17:29:18 +01002255static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2256{
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002257 phys_addr_t offset;
2258
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07002259 switch (attr->group) {
2260 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2261 switch (attr->attr) {
2262 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2263 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2264 return 0;
2265 }
2266 break;
Christoffer Dall0b3a5402013-10-25 21:17:31 +01002267 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2268 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2269 return vgic_has_attr_regs(vgic_dist_ranges, offset);
2270 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2271 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2272 return vgic_has_attr_regs(vgic_cpu_ranges, offset);
Christoffer Dallc4ad31f2013-09-23 14:55:56 -07002273 }
Christoffer Dall1032acb2013-10-25 17:29:18 +01002274 return -ENXIO;
2275}
2276
2277static void vgic_destroy(struct kvm_device *dev)
2278{
2279 kfree(dev);
2280}
2281
2282static int vgic_create(struct kvm_device *dev, u32 type)
2283{
2284 return kvm_vgic_create(dev->kvm);
2285}
2286
Will Deacon9e95eca2014-09-02 10:27:34 +01002287static struct kvm_device_ops kvm_arm_vgic_v2_ops = {
Christoffer Dall1032acb2013-10-25 17:29:18 +01002288 .name = "kvm-arm-vgic",
2289 .create = vgic_create,
2290 .destroy = vgic_destroy,
2291 .set_attr = vgic_set_attr,
2292 .get_attr = vgic_get_attr,
2293 .has_attr = vgic_has_attr,
2294};
Will Deacon9e95eca2014-09-02 10:27:34 +01002295
2296static void vgic_init_maintenance_interrupt(void *info)
2297{
2298 enable_percpu_irq(vgic->maint_irq, 0);
2299}
2300
2301static int vgic_cpu_notify(struct notifier_block *self,
2302 unsigned long action, void *cpu)
2303{
2304 switch (action) {
2305 case CPU_STARTING:
2306 case CPU_STARTING_FROZEN:
2307 vgic_init_maintenance_interrupt(NULL);
2308 break;
2309 case CPU_DYING:
2310 case CPU_DYING_FROZEN:
2311 disable_percpu_irq(vgic->maint_irq);
2312 break;
2313 }
2314
2315 return NOTIFY_OK;
2316}
2317
2318static struct notifier_block vgic_cpu_nb = {
2319 .notifier_call = vgic_cpu_notify,
2320};
2321
2322static const struct of_device_id vgic_ids[] = {
2323 { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
2324 { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
2325 {},
2326};
2327
2328int kvm_vgic_hyp_init(void)
2329{
2330 const struct of_device_id *matched_id;
2331 int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
2332 const struct vgic_params **);
2333 struct device_node *vgic_node;
2334 int ret;
2335
2336 vgic_node = of_find_matching_node_and_match(NULL,
2337 vgic_ids, &matched_id);
2338 if (!vgic_node) {
2339 kvm_err("error: no compatible GIC node found\n");
2340 return -ENODEV;
2341 }
2342
2343 vgic_probe = matched_id->data;
2344 ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
2345 if (ret)
2346 return ret;
2347
2348 ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
2349 "vgic", kvm_get_running_vcpus());
2350 if (ret) {
2351 kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
2352 return ret;
2353 }
2354
2355 ret = __register_cpu_notifier(&vgic_cpu_nb);
2356 if (ret) {
2357 kvm_err("Cannot register vgic CPU notifier\n");
2358 goto out_free_irq;
2359 }
2360
2361 /* Callback into for arch code for setup */
2362 vgic_arch_setup(vgic);
2363
2364 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
2365
2366 return kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
2367 KVM_DEV_TYPE_ARM_VGIC_V2);
2368
2369out_free_irq:
2370 free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());
2371 return ret;
2372}