drm/i915: introduce pipe_config->dither|pipe_bpp
We want to compute this earlier. To avoid a big complicated patch,
this patch here just does the big search&replace and still calls the
old functions at the same places.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dfcdfca..4cc46ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4665,6 +4665,10 @@
const intel_limit_t *limit;
int ret;
+ /* temporary hack */
+ intel_crtc->config.dither =
+ adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC;
+
for_each_encoder_on_crtc(dev, crtc, encoder) {
switch (encoder->type) {
case INTEL_OUTPUT_LVDS:
@@ -4765,7 +4769,7 @@
/* default to 8bpc */
pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
if (is_dp) {
- if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
+ if (intel_crtc->config.dither) {
pipeconf |= PIPECONF_6BPC |
PIPECONF_DITHER_EN |
PIPECONF_DITHER_TYPE_SP;
@@ -4773,7 +4777,7 @@
}
if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
- if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
+ if (intel_crtc->config.dither) {
pipeconf |= PIPECONF_6BPC |
PIPECONF_ENABLE |
I965_PIPECONF_ACTIVE;
@@ -5162,7 +5166,7 @@
val = I915_READ(PIPECONF(pipe));
val &= ~PIPECONF_BPC_MASK;
- switch (intel_crtc->bpp) {
+ switch (intel_crtc->config.pipe_bpp) {
case 18:
val |= PIPECONF_6BPC;
break;
@@ -5499,13 +5503,14 @@
if (!lane)
lane = ironlake_get_lanes_required(target_clock, link_bw,
- intel_crtc->bpp);
+ intel_crtc->config.pipe_bpp);
intel_crtc->fdi_lanes = lane;
if (intel_crtc->config.pixel_multiplier > 1)
link_bw *= intel_crtc->config.pixel_multiplier;
- intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
+ intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
+ link_bw, &m_n);
I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
@@ -5668,8 +5673,10 @@
intel_crtc_update_cursor(crtc, true);
/* determine panel color depth */
- dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
+ dither = intel_choose_pipe_bpp_dither(crtc, fb,
+ &intel_crtc->config.pipe_bpp,
adjusted_mode);
+ intel_crtc->config.dither = dither;
if (is_lvds && dev_priv->lvds_dither)
dither = true;
@@ -5834,8 +5841,10 @@
intel_crtc_update_cursor(crtc, true);
/* determine panel color depth */
- dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
+ dither = intel_choose_pipe_bpp_dither(crtc, fb,
+ &intel_crtc->config.pipe_bpp,
adjusted_mode);
+ intel_crtc->config.dither = dither;
DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
drm_mode_debug_printmodeline(mode);
@@ -8296,7 +8305,7 @@
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
- intel_crtc->bpp = 24; /* default for pre-Ironlake */
+ intel_crtc->config.pipe_bpp = 24; /* default for pre-Ironlake */
drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
}